amiro-blt / Target / Modules / DiWheelDrive_1-1 / Boot / lib / STM32F10x_StdPeriph_Driver / inc / stm32f10x_rcc.h @ 367c0652
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| 1 | 69661903 | Thomas Schöpping | /**
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| 2 | ******************************************************************************
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| 3 | * @file stm32f10x_rcc.h
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| 4 | * @author MCD Application Team
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| 5 | * @version V3.5.0
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| 6 | * @date 11-March-2011
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| 7 | * @brief This file contains all the functions prototypes for the RCC firmware
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| 8 | * library.
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| 9 | ******************************************************************************
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| 10 | * @attention
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| 11 | *
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| 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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| 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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| 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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| 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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| 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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| 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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| 18 | *
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| 19 | * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
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| 20 | ******************************************************************************
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| 21 | */
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| 22 | |||
| 23 | /* Define to prevent recursive inclusion -------------------------------------*/
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| 24 | #ifndef __STM32F10x_RCC_H
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| 25 | #define __STM32F10x_RCC_H
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| 26 | |||
| 27 | #ifdef __cplusplus
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| 28 | extern "C" { |
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| 29 | #endif
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| 30 | |||
| 31 | /* Includes ------------------------------------------------------------------*/
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| 32 | #include "stm32f10x.h" |
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| 33 | |||
| 34 | /** @addtogroup STM32F10x_StdPeriph_Driver
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| 35 | * @{
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| 36 | */
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| 37 | |||
| 38 | /** @addtogroup RCC
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| 39 | * @{
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| 40 | */
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| 41 | |||
| 42 | /** @defgroup RCC_Exported_Types
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| 43 | * @{
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| 44 | */
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| 45 | |||
| 46 | typedef struct |
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| 47 | {
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| 48 | uint32_t SYSCLK_Frequency; /*!< returns SYSCLK clock frequency expressed in Hz */
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| 49 | uint32_t HCLK_Frequency; /*!< returns HCLK clock frequency expressed in Hz */
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| 50 | uint32_t PCLK1_Frequency; /*!< returns PCLK1 clock frequency expressed in Hz */
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| 51 | uint32_t PCLK2_Frequency; /*!< returns PCLK2 clock frequency expressed in Hz */
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| 52 | uint32_t ADCCLK_Frequency; /*!< returns ADCCLK clock frequency expressed in Hz */
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| 53 | }RCC_ClocksTypeDef; |
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| 54 | |||
| 55 | /**
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| 56 | * @}
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| 57 | */
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| 58 | |||
| 59 | /** @defgroup RCC_Exported_Constants
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| 60 | * @{
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| 61 | */
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| 62 | |||
| 63 | /** @defgroup HSE_configuration
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| 64 | * @{
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| 65 | */
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| 66 | |||
| 67 | #define RCC_HSE_OFF ((uint32_t)0x00000000) |
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| 68 | #define RCC_HSE_ON ((uint32_t)0x00010000) |
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| 69 | #define RCC_HSE_Bypass ((uint32_t)0x00040000) |
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| 70 | #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
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| 71 | ((HSE) == RCC_HSE_Bypass)) |
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| 72 | |||
| 73 | /**
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| 74 | * @}
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| 75 | */
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| 76 | |||
| 77 | /** @defgroup PLL_entry_clock_source
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| 78 | * @{
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| 79 | */
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| 80 | |||
| 81 | #define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000) |
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| 82 | |||
| 83 | #if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_CL)
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| 84 | #define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000) |
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| 85 | #define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000) |
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| 86 | #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
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| 87 | ((SOURCE) == RCC_PLLSource_HSE_Div1) || \ |
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| 88 | ((SOURCE) == RCC_PLLSource_HSE_Div2)) |
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| 89 | #else
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| 90 | #define RCC_PLLSource_PREDIV1 ((uint32_t)0x00010000) |
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| 91 | #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
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| 92 | ((SOURCE) == RCC_PLLSource_PREDIV1)) |
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| 93 | #endif /* STM32F10X_CL */ |
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| 94 | |||
| 95 | /**
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| 96 | * @}
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| 97 | */
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| 98 | |||
| 99 | /** @defgroup PLL_multiplication_factor
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| 100 | * @{
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| 101 | */
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| 102 | #ifndef STM32F10X_CL
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| 103 | #define RCC_PLLMul_2 ((uint32_t)0x00000000) |
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| 104 | #define RCC_PLLMul_3 ((uint32_t)0x00040000) |
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| 105 | #define RCC_PLLMul_4 ((uint32_t)0x00080000) |
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| 106 | #define RCC_PLLMul_5 ((uint32_t)0x000C0000) |
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| 107 | #define RCC_PLLMul_6 ((uint32_t)0x00100000) |
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| 108 | #define RCC_PLLMul_7 ((uint32_t)0x00140000) |
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| 109 | #define RCC_PLLMul_8 ((uint32_t)0x00180000) |
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| 110 | #define RCC_PLLMul_9 ((uint32_t)0x001C0000) |
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| 111 | #define RCC_PLLMul_10 ((uint32_t)0x00200000) |
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| 112 | #define RCC_PLLMul_11 ((uint32_t)0x00240000) |
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| 113 | #define RCC_PLLMul_12 ((uint32_t)0x00280000) |
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| 114 | #define RCC_PLLMul_13 ((uint32_t)0x002C0000) |
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| 115 | #define RCC_PLLMul_14 ((uint32_t)0x00300000) |
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| 116 | #define RCC_PLLMul_15 ((uint32_t)0x00340000) |
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| 117 | #define RCC_PLLMul_16 ((uint32_t)0x00380000) |
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| 118 | #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \
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| 119 | ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ |
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| 120 | ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ |
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| 121 | ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ |
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| 122 | ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \ |
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| 123 | ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \ |
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| 124 | ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \ |
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| 125 | ((MUL) == RCC_PLLMul_16)) |
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| 126 | |||
| 127 | #else
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| 128 | #define RCC_PLLMul_4 ((uint32_t)0x00080000) |
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| 129 | #define RCC_PLLMul_5 ((uint32_t)0x000C0000) |
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| 130 | #define RCC_PLLMul_6 ((uint32_t)0x00100000) |
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| 131 | #define RCC_PLLMul_7 ((uint32_t)0x00140000) |
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| 132 | #define RCC_PLLMul_8 ((uint32_t)0x00180000) |
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| 133 | #define RCC_PLLMul_9 ((uint32_t)0x001C0000) |
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| 134 | #define RCC_PLLMul_6_5 ((uint32_t)0x00340000) |
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| 135 | |||
| 136 | #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
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| 137 | ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ |
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| 138 | ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ |
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| 139 | ((MUL) == RCC_PLLMul_6_5)) |
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| 140 | #endif /* STM32F10X_CL */ |
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| 141 | /**
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| 142 | * @}
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| 143 | */
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| 144 | |||
| 145 | /** @defgroup PREDIV1_division_factor
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| 146 | * @{
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| 147 | */
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| 148 | #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)
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| 149 | #define RCC_PREDIV1_Div1 ((uint32_t)0x00000000) |
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| 150 | #define RCC_PREDIV1_Div2 ((uint32_t)0x00000001) |
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| 151 | #define RCC_PREDIV1_Div3 ((uint32_t)0x00000002) |
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| 152 | #define RCC_PREDIV1_Div4 ((uint32_t)0x00000003) |
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| 153 | #define RCC_PREDIV1_Div5 ((uint32_t)0x00000004) |
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| 154 | #define RCC_PREDIV1_Div6 ((uint32_t)0x00000005) |
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| 155 | #define RCC_PREDIV1_Div7 ((uint32_t)0x00000006) |
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| 156 | #define RCC_PREDIV1_Div8 ((uint32_t)0x00000007) |
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| 157 | #define RCC_PREDIV1_Div9 ((uint32_t)0x00000008) |
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| 158 | #define RCC_PREDIV1_Div10 ((uint32_t)0x00000009) |
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| 159 | #define RCC_PREDIV1_Div11 ((uint32_t)0x0000000A) |
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| 160 | #define RCC_PREDIV1_Div12 ((uint32_t)0x0000000B) |
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| 161 | #define RCC_PREDIV1_Div13 ((uint32_t)0x0000000C) |
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| 162 | #define RCC_PREDIV1_Div14 ((uint32_t)0x0000000D) |
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| 163 | #define RCC_PREDIV1_Div15 ((uint32_t)0x0000000E) |
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| 164 | #define RCC_PREDIV1_Div16 ((uint32_t)0x0000000F) |
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| 165 | |||
| 166 | #define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \
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| 167 | ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \ |
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| 168 | ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \ |
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| 169 | ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \ |
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| 170 | ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \ |
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| 171 | ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \ |
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| 172 | ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \ |
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| 173 | ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16)) |
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| 174 | #endif
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| 175 | /**
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| 176 | * @}
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| 177 | */
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| 178 | |||
| 179 | |||
| 180 | /** @defgroup PREDIV1_clock_source
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| 181 | * @{
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| 182 | */
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| 183 | #ifdef STM32F10X_CL
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| 184 | /* PREDIV1 clock source (for STM32 connectivity line devices) */
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| 185 | #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000) |
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| 186 | #define RCC_PREDIV1_Source_PLL2 ((uint32_t)0x00010000) |
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| 187 | |||
| 188 | #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE) || \
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| 189 | ((SOURCE) == RCC_PREDIV1_Source_PLL2)) |
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| 190 | #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
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| 191 | /* PREDIV1 clock source (for STM32 Value line devices) */
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| 192 | #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000) |
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| 193 | |||
| 194 | #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE))
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| 195 | #endif
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| 196 | /**
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| 197 | * @}
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| 198 | */
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| 199 | |||
| 200 | #ifdef STM32F10X_CL
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| 201 | /** @defgroup PREDIV2_division_factor
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| 202 | * @{
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| 203 | */
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| 204 | |||
| 205 | #define RCC_PREDIV2_Div1 ((uint32_t)0x00000000) |
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| 206 | #define RCC_PREDIV2_Div2 ((uint32_t)0x00000010) |
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| 207 | #define RCC_PREDIV2_Div3 ((uint32_t)0x00000020) |
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| 208 | #define RCC_PREDIV2_Div4 ((uint32_t)0x00000030) |
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| 209 | #define RCC_PREDIV2_Div5 ((uint32_t)0x00000040) |
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| 210 | #define RCC_PREDIV2_Div6 ((uint32_t)0x00000050) |
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| 211 | #define RCC_PREDIV2_Div7 ((uint32_t)0x00000060) |
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| 212 | #define RCC_PREDIV2_Div8 ((uint32_t)0x00000070) |
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| 213 | #define RCC_PREDIV2_Div9 ((uint32_t)0x00000080) |
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| 214 | #define RCC_PREDIV2_Div10 ((uint32_t)0x00000090) |
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| 215 | #define RCC_PREDIV2_Div11 ((uint32_t)0x000000A0) |
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| 216 | #define RCC_PREDIV2_Div12 ((uint32_t)0x000000B0) |
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| 217 | #define RCC_PREDIV2_Div13 ((uint32_t)0x000000C0) |
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| 218 | #define RCC_PREDIV2_Div14 ((uint32_t)0x000000D0) |
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| 219 | #define RCC_PREDIV2_Div15 ((uint32_t)0x000000E0) |
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| 220 | #define RCC_PREDIV2_Div16 ((uint32_t)0x000000F0) |
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| 221 | |||
| 222 | #define IS_RCC_PREDIV2(PREDIV2) (((PREDIV2) == RCC_PREDIV2_Div1) || ((PREDIV2) == RCC_PREDIV2_Div2) || \
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| 223 | ((PREDIV2) == RCC_PREDIV2_Div3) || ((PREDIV2) == RCC_PREDIV2_Div4) || \ |
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| 224 | ((PREDIV2) == RCC_PREDIV2_Div5) || ((PREDIV2) == RCC_PREDIV2_Div6) || \ |
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| 225 | ((PREDIV2) == RCC_PREDIV2_Div7) || ((PREDIV2) == RCC_PREDIV2_Div8) || \ |
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| 226 | ((PREDIV2) == RCC_PREDIV2_Div9) || ((PREDIV2) == RCC_PREDIV2_Div10) || \ |
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| 227 | ((PREDIV2) == RCC_PREDIV2_Div11) || ((PREDIV2) == RCC_PREDIV2_Div12) || \ |
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| 228 | ((PREDIV2) == RCC_PREDIV2_Div13) || ((PREDIV2) == RCC_PREDIV2_Div14) || \ |
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| 229 | ((PREDIV2) == RCC_PREDIV2_Div15) || ((PREDIV2) == RCC_PREDIV2_Div16)) |
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| 230 | /**
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| 231 | * @}
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| 232 | */
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| 233 | |||
| 234 | |||
| 235 | /** @defgroup PLL2_multiplication_factor
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| 236 | * @{
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| 237 | */
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| 238 | |||
| 239 | #define RCC_PLL2Mul_8 ((uint32_t)0x00000600) |
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| 240 | #define RCC_PLL2Mul_9 ((uint32_t)0x00000700) |
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| 241 | #define RCC_PLL2Mul_10 ((uint32_t)0x00000800) |
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| 242 | #define RCC_PLL2Mul_11 ((uint32_t)0x00000900) |
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| 243 | #define RCC_PLL2Mul_12 ((uint32_t)0x00000A00) |
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| 244 | #define RCC_PLL2Mul_13 ((uint32_t)0x00000B00) |
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| 245 | #define RCC_PLL2Mul_14 ((uint32_t)0x00000C00) |
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| 246 | #define RCC_PLL2Mul_16 ((uint32_t)0x00000E00) |
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| 247 | #define RCC_PLL2Mul_20 ((uint32_t)0x00000F00) |
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| 248 | |||
| 249 | #define IS_RCC_PLL2_MUL(MUL) (((MUL) == RCC_PLL2Mul_8) || ((MUL) == RCC_PLL2Mul_9) || \
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| 250 | ((MUL) == RCC_PLL2Mul_10) || ((MUL) == RCC_PLL2Mul_11) || \ |
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| 251 | ((MUL) == RCC_PLL2Mul_12) || ((MUL) == RCC_PLL2Mul_13) || \ |
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| 252 | ((MUL) == RCC_PLL2Mul_14) || ((MUL) == RCC_PLL2Mul_16) || \ |
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| 253 | ((MUL) == RCC_PLL2Mul_20)) |
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| 254 | /**
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| 255 | * @}
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| 256 | */
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| 257 | |||
| 258 | |||
| 259 | /** @defgroup PLL3_multiplication_factor
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| 260 | * @{
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| 261 | */
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| 262 | |||
| 263 | #define RCC_PLL3Mul_8 ((uint32_t)0x00006000) |
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| 264 | #define RCC_PLL3Mul_9 ((uint32_t)0x00007000) |
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| 265 | #define RCC_PLL3Mul_10 ((uint32_t)0x00008000) |
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| 266 | #define RCC_PLL3Mul_11 ((uint32_t)0x00009000) |
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| 267 | #define RCC_PLL3Mul_12 ((uint32_t)0x0000A000) |
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| 268 | #define RCC_PLL3Mul_13 ((uint32_t)0x0000B000) |
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| 269 | #define RCC_PLL3Mul_14 ((uint32_t)0x0000C000) |
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| 270 | #define RCC_PLL3Mul_16 ((uint32_t)0x0000E000) |
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| 271 | #define RCC_PLL3Mul_20 ((uint32_t)0x0000F000) |
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| 272 | |||
| 273 | #define IS_RCC_PLL3_MUL(MUL) (((MUL) == RCC_PLL3Mul_8) || ((MUL) == RCC_PLL3Mul_9) || \
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| 274 | ((MUL) == RCC_PLL3Mul_10) || ((MUL) == RCC_PLL3Mul_11) || \ |
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| 275 | ((MUL) == RCC_PLL3Mul_12) || ((MUL) == RCC_PLL3Mul_13) || \ |
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| 276 | ((MUL) == RCC_PLL3Mul_14) || ((MUL) == RCC_PLL3Mul_16) || \ |
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| 277 | ((MUL) == RCC_PLL3Mul_20)) |
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| 278 | /**
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| 279 | * @}
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| 280 | */
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| 281 | |||
| 282 | #endif /* STM32F10X_CL */ |
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| 283 | |||
| 284 | |||
| 285 | /** @defgroup System_clock_source
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| 286 | * @{
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| 287 | */
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| 288 | |||
| 289 | #define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) |
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| 290 | #define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) |
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| 291 | #define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) |
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| 292 | #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
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| 293 | ((SOURCE) == RCC_SYSCLKSource_HSE) || \ |
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| 294 | ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) |
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| 295 | /**
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| 296 | * @}
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| 297 | */
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| 298 | |||
| 299 | /** @defgroup AHB_clock_source
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| 300 | * @{
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| 301 | */
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| 302 | |||
| 303 | #define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) |
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| 304 | #define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) |
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| 305 | #define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) |
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| 306 | #define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) |
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| 307 | #define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) |
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| 308 | #define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) |
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| 309 | #define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) |
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| 310 | #define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) |
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| 311 | #define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) |
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| 312 | #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
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| 313 | ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ |
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| 314 | ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ |
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| 315 | ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ |
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| 316 | ((HCLK) == RCC_SYSCLK_Div512)) |
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| 317 | /**
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| 318 | * @}
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| 319 | */
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| 320 | |||
| 321 | /** @defgroup APB1_APB2_clock_source
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| 322 | * @{
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| 323 | */
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| 324 | |||
| 325 | #define RCC_HCLK_Div1 ((uint32_t)0x00000000) |
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| 326 | #define RCC_HCLK_Div2 ((uint32_t)0x00000400) |
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| 327 | #define RCC_HCLK_Div4 ((uint32_t)0x00000500) |
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| 328 | #define RCC_HCLK_Div8 ((uint32_t)0x00000600) |
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| 329 | #define RCC_HCLK_Div16 ((uint32_t)0x00000700) |
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| 330 | #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
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| 331 | ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ |
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| 332 | ((PCLK) == RCC_HCLK_Div16)) |
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| 333 | /**
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| 334 | * @}
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| 335 | */
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| 336 | |||
| 337 | /** @defgroup RCC_Interrupt_source
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| 338 | * @{
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| 339 | */
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| 340 | |||
| 341 | #define RCC_IT_LSIRDY ((uint8_t)0x01) |
||
| 342 | #define RCC_IT_LSERDY ((uint8_t)0x02) |
||
| 343 | #define RCC_IT_HSIRDY ((uint8_t)0x04) |
||
| 344 | #define RCC_IT_HSERDY ((uint8_t)0x08) |
||
| 345 | #define RCC_IT_PLLRDY ((uint8_t)0x10) |
||
| 346 | #define RCC_IT_CSS ((uint8_t)0x80) |
||
| 347 | |||
| 348 | #ifndef STM32F10X_CL
|
||
| 349 | #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00)) |
||
| 350 | #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
|
||
| 351 | ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ |
||
| 352 | ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS)) |
||
| 353 | #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00)) |
||
| 354 | #else
|
||
| 355 | #define RCC_IT_PLL2RDY ((uint8_t)0x20) |
||
| 356 | #define RCC_IT_PLL3RDY ((uint8_t)0x40) |
||
| 357 | #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00)) |
||
| 358 | #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
|
||
| 359 | ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ |
||
| 360 | ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \ |
||
| 361 | ((IT) == RCC_IT_PLL2RDY) || ((IT) == RCC_IT_PLL3RDY)) |
||
| 362 | #define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00) |
||
| 363 | #endif /* STM32F10X_CL */ |
||
| 364 | |||
| 365 | |||
| 366 | /**
|
||
| 367 | * @}
|
||
| 368 | */
|
||
| 369 | |||
| 370 | #ifndef STM32F10X_CL
|
||
| 371 | /** @defgroup USB_Device_clock_source
|
||
| 372 | * @{
|
||
| 373 | */
|
||
| 374 | |||
| 375 | #define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00) |
||
| 376 | #define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01) |
||
| 377 | |||
| 378 | #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \
|
||
| 379 | ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1)) |
||
| 380 | /**
|
||
| 381 | * @}
|
||
| 382 | */
|
||
| 383 | #else
|
||
| 384 | /** @defgroup USB_OTG_FS_clock_source
|
||
| 385 | * @{
|
||
| 386 | */
|
||
| 387 | #define RCC_OTGFSCLKSource_PLLVCO_Div3 ((uint8_t)0x00) |
||
| 388 | #define RCC_OTGFSCLKSource_PLLVCO_Div2 ((uint8_t)0x01) |
||
| 389 | |||
| 390 | #define IS_RCC_OTGFSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div3) || \
|
||
| 391 | ((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div2)) |
||
| 392 | /**
|
||
| 393 | * @}
|
||
| 394 | */
|
||
| 395 | #endif /* STM32F10X_CL */ |
||
| 396 | |||
| 397 | |||
| 398 | #ifdef STM32F10X_CL
|
||
| 399 | /** @defgroup I2S2_clock_source
|
||
| 400 | * @{
|
||
| 401 | */
|
||
| 402 | #define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00) |
||
| 403 | #define RCC_I2S2CLKSource_PLL3_VCO ((uint8_t)0x01) |
||
| 404 | |||
| 405 | #define IS_RCC_I2S2CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || \
|
||
| 406 | ((SOURCE) == RCC_I2S2CLKSource_PLL3_VCO)) |
||
| 407 | /**
|
||
| 408 | * @}
|
||
| 409 | */
|
||
| 410 | |||
| 411 | /** @defgroup I2S3_clock_source
|
||
| 412 | * @{
|
||
| 413 | */
|
||
| 414 | #define RCC_I2S3CLKSource_SYSCLK ((uint8_t)0x00) |
||
| 415 | #define RCC_I2S3CLKSource_PLL3_VCO ((uint8_t)0x01) |
||
| 416 | |||
| 417 | #define IS_RCC_I2S3CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S3CLKSource_SYSCLK) || \
|
||
| 418 | ((SOURCE) == RCC_I2S3CLKSource_PLL3_VCO)) |
||
| 419 | /**
|
||
| 420 | * @}
|
||
| 421 | */
|
||
| 422 | #endif /* STM32F10X_CL */ |
||
| 423 | |||
| 424 | |||
| 425 | /** @defgroup ADC_clock_source
|
||
| 426 | * @{
|
||
| 427 | */
|
||
| 428 | |||
| 429 | #define RCC_PCLK2_Div2 ((uint32_t)0x00000000) |
||
| 430 | #define RCC_PCLK2_Div4 ((uint32_t)0x00004000) |
||
| 431 | #define RCC_PCLK2_Div6 ((uint32_t)0x00008000) |
||
| 432 | #define RCC_PCLK2_Div8 ((uint32_t)0x0000C000) |
||
| 433 | #define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \
|
||
| 434 | ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8)) |
||
| 435 | /**
|
||
| 436 | * @}
|
||
| 437 | */
|
||
| 438 | |||
| 439 | /** @defgroup LSE_configuration
|
||
| 440 | * @{
|
||
| 441 | */
|
||
| 442 | |||
| 443 | #define RCC_LSE_OFF ((uint8_t)0x00) |
||
| 444 | #define RCC_LSE_ON ((uint8_t)0x01) |
||
| 445 | #define RCC_LSE_Bypass ((uint8_t)0x04) |
||
| 446 | #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
|
||
| 447 | ((LSE) == RCC_LSE_Bypass)) |
||
| 448 | /**
|
||
| 449 | * @}
|
||
| 450 | */
|
||
| 451 | |||
| 452 | /** @defgroup RTC_clock_source
|
||
| 453 | * @{
|
||
| 454 | */
|
||
| 455 | |||
| 456 | #define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) |
||
| 457 | #define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) |
||
| 458 | #define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300) |
||
| 459 | #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
|
||
| 460 | ((SOURCE) == RCC_RTCCLKSource_LSI) || \ |
||
| 461 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div128)) |
||
| 462 | /**
|
||
| 463 | * @}
|
||
| 464 | */
|
||
| 465 | |||
| 466 | /** @defgroup AHB_peripheral
|
||
| 467 | * @{
|
||
| 468 | */
|
||
| 469 | |||
| 470 | #define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001) |
||
| 471 | #define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002) |
||
| 472 | #define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) |
||
| 473 | #define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010) |
||
| 474 | #define RCC_AHBPeriph_CRC ((uint32_t)0x00000040) |
||
| 475 | |||
| 476 | #ifndef STM32F10X_CL
|
||
| 477 | #define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100) |
||
| 478 | #define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400) |
||
| 479 | #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00)) |
||
| 480 | #else
|
||
| 481 | #define RCC_AHBPeriph_OTG_FS ((uint32_t)0x00001000) |
||
| 482 | #define RCC_AHBPeriph_ETH_MAC ((uint32_t)0x00004000) |
||
| 483 | #define RCC_AHBPeriph_ETH_MAC_Tx ((uint32_t)0x00008000) |
||
| 484 | #define RCC_AHBPeriph_ETH_MAC_Rx ((uint32_t)0x00010000) |
||
| 485 | |||
| 486 | #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFE2FA8) == 0x00) && ((PERIPH) != 0x00)) |
||
| 487 | #define IS_RCC_AHB_PERIPH_RESET(PERIPH) ((((PERIPH) & 0xFFFFAFFF) == 0x00) && ((PERIPH) != 0x00)) |
||
| 488 | #endif /* STM32F10X_CL */ |
||
| 489 | /**
|
||
| 490 | * @}
|
||
| 491 | */
|
||
| 492 | |||
| 493 | /** @defgroup APB2_peripheral
|
||
| 494 | * @{
|
||
| 495 | */
|
||
| 496 | |||
| 497 | #define RCC_APB2Periph_AFIO ((uint32_t)0x00000001) |
||
| 498 | #define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004) |
||
| 499 | #define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008) |
||
| 500 | #define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010) |
||
| 501 | #define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020) |
||
| 502 | #define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040) |
||
| 503 | #define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080) |
||
| 504 | #define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100) |
||
| 505 | #define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200) |
||
| 506 | #define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400) |
||
| 507 | #define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800) |
||
| 508 | #define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) |
||
| 509 | #define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000) |
||
| 510 | #define RCC_APB2Periph_USART1 ((uint32_t)0x00004000) |
||
| 511 | #define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000) |
||
| 512 | #define RCC_APB2Periph_TIM15 ((uint32_t)0x00010000) |
||
| 513 | #define RCC_APB2Periph_TIM16 ((uint32_t)0x00020000) |
||
| 514 | #define RCC_APB2Periph_TIM17 ((uint32_t)0x00040000) |
||
| 515 | #define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000) |
||
| 516 | #define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000) |
||
| 517 | #define RCC_APB2Periph_TIM11 ((uint32_t)0x00200000) |
||
| 518 | |||
| 519 | #define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFC00002) == 0x00) && ((PERIPH) != 0x00)) |
||
| 520 | /**
|
||
| 521 | * @}
|
||
| 522 | */
|
||
| 523 | |||
| 524 | /** @defgroup APB1_peripheral
|
||
| 525 | * @{
|
||
| 526 | */
|
||
| 527 | |||
| 528 | #define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) |
||
| 529 | #define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) |
||
| 530 | #define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) |
||
| 531 | #define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) |
||
| 532 | #define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) |
||
| 533 | #define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) |
||
| 534 | #define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040) |
||
| 535 | #define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080) |
||
| 536 | #define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100) |
||
| 537 | #define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) |
||
| 538 | #define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) |
||
| 539 | #define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) |
||
| 540 | #define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) |
||
| 541 | #define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) |
||
| 542 | #define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) |
||
| 543 | #define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) |
||
| 544 | #define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) |
||
| 545 | #define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) |
||
| 546 | #define RCC_APB1Periph_USB ((uint32_t)0x00800000) |
||
| 547 | #define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) |
||
| 548 | #define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) |
||
| 549 | #define RCC_APB1Periph_BKP ((uint32_t)0x08000000) |
||
| 550 | #define RCC_APB1Periph_PWR ((uint32_t)0x10000000) |
||
| 551 | #define RCC_APB1Periph_DAC ((uint32_t)0x20000000) |
||
| 552 | #define RCC_APB1Periph_CEC ((uint32_t)0x40000000) |
||
| 553 | |||
| 554 | #define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x81013600) == 0x00) && ((PERIPH) != 0x00)) |
||
| 555 | |||
| 556 | /**
|
||
| 557 | * @}
|
||
| 558 | */
|
||
| 559 | |||
| 560 | /** @defgroup Clock_source_to_output_on_MCO_pin
|
||
| 561 | * @{
|
||
| 562 | */
|
||
| 563 | |||
| 564 | #define RCC_MCO_NoClock ((uint8_t)0x00) |
||
| 565 | #define RCC_MCO_SYSCLK ((uint8_t)0x04) |
||
| 566 | #define RCC_MCO_HSI ((uint8_t)0x05) |
||
| 567 | #define RCC_MCO_HSE ((uint8_t)0x06) |
||
| 568 | #define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07) |
||
| 569 | |||
| 570 | #ifndef STM32F10X_CL
|
||
| 571 | #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \
|
||
| 572 | ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \ |
||
| 573 | ((MCO) == RCC_MCO_PLLCLK_Div2)) |
||
| 574 | #else
|
||
| 575 | #define RCC_MCO_PLL2CLK ((uint8_t)0x08) |
||
| 576 | #define RCC_MCO_PLL3CLK_Div2 ((uint8_t)0x09) |
||
| 577 | #define RCC_MCO_XT1 ((uint8_t)0x0A) |
||
| 578 | #define RCC_MCO_PLL3CLK ((uint8_t)0x0B) |
||
| 579 | |||
| 580 | #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \
|
||
| 581 | ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \ |
||
| 582 | ((MCO) == RCC_MCO_PLLCLK_Div2) || ((MCO) == RCC_MCO_PLL2CLK) || \ |
||
| 583 | ((MCO) == RCC_MCO_PLL3CLK_Div2) || ((MCO) == RCC_MCO_XT1) || \ |
||
| 584 | ((MCO) == RCC_MCO_PLL3CLK)) |
||
| 585 | #endif /* STM32F10X_CL */ |
||
| 586 | |||
| 587 | /**
|
||
| 588 | * @}
|
||
| 589 | */
|
||
| 590 | |||
| 591 | /** @defgroup RCC_Flag
|
||
| 592 | * @{
|
||
| 593 | */
|
||
| 594 | |||
| 595 | #define RCC_FLAG_HSIRDY ((uint8_t)0x21) |
||
| 596 | #define RCC_FLAG_HSERDY ((uint8_t)0x31) |
||
| 597 | #define RCC_FLAG_PLLRDY ((uint8_t)0x39) |
||
| 598 | #define RCC_FLAG_LSERDY ((uint8_t)0x41) |
||
| 599 | #define RCC_FLAG_LSIRDY ((uint8_t)0x61) |
||
| 600 | #define RCC_FLAG_PINRST ((uint8_t)0x7A) |
||
| 601 | #define RCC_FLAG_PORRST ((uint8_t)0x7B) |
||
| 602 | #define RCC_FLAG_SFTRST ((uint8_t)0x7C) |
||
| 603 | #define RCC_FLAG_IWDGRST ((uint8_t)0x7D) |
||
| 604 | #define RCC_FLAG_WWDGRST ((uint8_t)0x7E) |
||
| 605 | #define RCC_FLAG_LPWRRST ((uint8_t)0x7F) |
||
| 606 | |||
| 607 | #ifndef STM32F10X_CL
|
||
| 608 | #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
|
||
| 609 | ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ |
||
| 610 | ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \ |
||
| 611 | ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \ |
||
| 612 | ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \ |
||
| 613 | ((FLAG) == RCC_FLAG_LPWRRST)) |
||
| 614 | #else
|
||
| 615 | #define RCC_FLAG_PLL2RDY ((uint8_t)0x3B) |
||
| 616 | #define RCC_FLAG_PLL3RDY ((uint8_t)0x3D) |
||
| 617 | #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
|
||
| 618 | ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ |
||
| 619 | ((FLAG) == RCC_FLAG_PLL2RDY) || ((FLAG) == RCC_FLAG_PLL3RDY) || \ |
||
| 620 | ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \ |
||
| 621 | ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \ |
||
| 622 | ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \ |
||
| 623 | ((FLAG) == RCC_FLAG_LPWRRST)) |
||
| 624 | #endif /* STM32F10X_CL */ |
||
| 625 | |||
| 626 | #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) |
||
| 627 | /**
|
||
| 628 | * @}
|
||
| 629 | */
|
||
| 630 | |||
| 631 | /**
|
||
| 632 | * @}
|
||
| 633 | */
|
||
| 634 | |||
| 635 | /** @defgroup RCC_Exported_Macros
|
||
| 636 | * @{
|
||
| 637 | */
|
||
| 638 | |||
| 639 | /**
|
||
| 640 | * @}
|
||
| 641 | */
|
||
| 642 | |||
| 643 | /** @defgroup RCC_Exported_Functions
|
||
| 644 | * @{
|
||
| 645 | */
|
||
| 646 | |||
| 647 | void RCC_DeInit(void); |
||
| 648 | void RCC_HSEConfig(uint32_t RCC_HSE);
|
||
| 649 | ErrorStatus RCC_WaitForHSEStartUp(void);
|
||
| 650 | void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
|
||
| 651 | void RCC_HSICmd(FunctionalState NewState);
|
||
| 652 | void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
|
||
| 653 | void RCC_PLLCmd(FunctionalState NewState);
|
||
| 654 | |||
| 655 | #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)
|
||
| 656 | void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div);
|
||
| 657 | #endif
|
||
| 658 | |||
| 659 | #ifdef STM32F10X_CL
|
||
| 660 | void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div);
|
||
| 661 | void RCC_PLL2Config(uint32_t RCC_PLL2Mul);
|
||
| 662 | void RCC_PLL2Cmd(FunctionalState NewState);
|
||
| 663 | void RCC_PLL3Config(uint32_t RCC_PLL3Mul);
|
||
| 664 | void RCC_PLL3Cmd(FunctionalState NewState);
|
||
| 665 | #endif /* STM32F10X_CL */ |
||
| 666 | |||
| 667 | void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
|
||
| 668 | uint8_t RCC_GetSYSCLKSource(void);
|
||
| 669 | void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
|
||
| 670 | void RCC_PCLK1Config(uint32_t RCC_HCLK);
|
||
| 671 | void RCC_PCLK2Config(uint32_t RCC_HCLK);
|
||
| 672 | void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
|
||
| 673 | |||
| 674 | #ifndef STM32F10X_CL
|
||
| 675 | void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource);
|
||
| 676 | #else
|
||
| 677 | void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource);
|
||
| 678 | #endif /* STM32F10X_CL */ |
||
| 679 | |||
| 680 | void RCC_ADCCLKConfig(uint32_t RCC_PCLK2);
|
||
| 681 | |||
| 682 | #ifdef STM32F10X_CL
|
||
| 683 | void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource);
|
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| 684 | void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource);
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| 685 | #endif /* STM32F10X_CL */ |
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| 686 | |||
| 687 | void RCC_LSEConfig(uint8_t RCC_LSE);
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| 688 | void RCC_LSICmd(FunctionalState NewState);
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| 689 | void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
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| 690 | void RCC_RTCCLKCmd(FunctionalState NewState);
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| 691 | void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
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| 692 | void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
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| 693 | void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
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| 694 | void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
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| 695 | |||
| 696 | #ifdef STM32F10X_CL
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| 697 | void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
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| 698 | #endif /* STM32F10X_CL */ |
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| 699 | |||
| 700 | void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
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| 701 | void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
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| 702 | void RCC_BackupResetCmd(FunctionalState NewState);
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| 703 | void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
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| 704 | void RCC_MCOConfig(uint8_t RCC_MCO);
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| 705 | FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); |
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| 706 | void RCC_ClearFlag(void); |
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| 707 | ITStatus RCC_GetITStatus(uint8_t RCC_IT); |
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| 708 | void RCC_ClearITPendingBit(uint8_t RCC_IT);
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| 709 | |||
| 710 | #ifdef __cplusplus
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| 711 | } |
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| 712 | #endif
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| 713 | |||
| 714 | #endif /* __STM32F10x_RCC_H */ |
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| 715 | /**
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| 716 | * @}
|
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| 717 | */
|
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| 718 | |||
| 719 | /**
|
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| 720 | * @}
|
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| 721 | */
|
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| 722 | |||
| 723 | /**
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| 724 | * @}
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| 725 | */
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| 726 | |||
| 727 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|