AMiRo-OS

/**

  ******************************************************************************

  * @file    stm32_eth.c

  * @author  MCD Application Team

  * @version V1.0.0

  * @date    06/19/2009

  * @brief   This file provides all the ETH firmware functions.

  ******************************************************************************

  * @copy

  *

  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS

  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE

  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY

  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING

  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE

  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

  *

  * <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>

  */ 

/* Includes ------------------------------------------------------------------*/

#include "stm32_eth.h"

#include "stm32f4xx_rcc.h"

/** @addtogroup STM32_ETH_Driver

  * @brief ETH driver modules

  * @{

  */

/** @defgroup ETH_Private_TypesDefinitions

  * @{

  */ 

/**

  * @}

  */ 

/** @defgroup ETH_Private_Defines

  * @{

  */ 

/* Global pointers on Tx and Rx descriptor used to track transmit and receive descriptors */

ETH_DMADESCTypeDef  *DMATxDescToSet;

ETH_DMADESCTypeDef  *DMARxDescToGet;

ETH_DMADESCTypeDef  *DMAPTPTxDescToSet;

ETH_DMADESCTypeDef  *DMAPTPRxDescToGet;

/* ETHERNET MAC address offsets */

#define ETH_MAC_AddrHighBase   (ETH_MAC_BASE + 0x40)  /* ETHERNET MAC address high offset */

#define ETH_MAC_AddrLowBase    (ETH_MAC_BASE + 0x44)  /* ETHERNET MAC address low offset */

/* ETHERNET MACMIIAR register Mask */

#define MACMIIAR_CR_Mask    ((uint32_t)0xFFFFFFE3) 

/* ETHERNET MACCR register Mask */

#define MACCR_CLEAR_Mask    ((uint32_t)0xFF20810F)  

/* ETHERNET MACFCR register Mask */

#define MACFCR_CLEAR_Mask   ((uint32_t)0x0000FF41)

/* ETHERNET DMAOMR register Mask */

#define DMAOMR_CLEAR_Mask   ((uint32_t)0xF8DE3F23)

/* ETHERNET Remote Wake-up frame register length */

#define ETH_WakeupRegisterLength      8

/* ETHERNET Missed frames counter Shift */

#define  ETH_DMA_RxOverflowMissedFramesCounterShift     17

/* ETHERNET DMA Tx descriptors Collision Count Shift */

#define  ETH_DMATxDesc_CollisionCountShift        3

/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */

#define  ETH_DMATxDesc_BufferSize2Shift           16

/* ETHERNET DMA Rx descriptors Frame Length Shift */

#define  ETH_DMARxDesc_FrameLengthShift           16

/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */

#define  ETH_DMARxDesc_Buffer2SizeShift           16

/* ETHERNET errors */

#define  ETH_ERROR              ((uint32_t)0)

#define  ETH_SUCCESS            ((uint32_t)1)

/**

  * @}

  */

/** @defgroup ETH_Private_Macros

  * @{

  */ 

/**

  * @}

  */

/** @defgroup ETH_Private_Variables

  * @{

  */ 

/**

  * @}

  */

/** @defgroup ETH_Private_FunctionPrototypes

  * @{

  */ 

/**

  * @}

  */

/** @defgroup ETH_Private_Functions

  * @{

  */

/**

  * @brief  Deinitializes the ETHERNET peripheral registers to their

  *   default reset values.

  * @param  None 

  * @retval : None

  */

void ETH_DeInit(void)

{

  RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_ETH_MAC, ENABLE);

  RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_ETH_MAC, DISABLE);

}

/**

  * @brief  Initializes the ETHERNET peripheral according to the specified

  *   parameters in the ETH_InitStruct .

  * @param ETH_InitStruct: pointer to a ETH_InitTypeDef structure

  *   that contains the configuration information for the

  *   specified ETHERNET peripheral.

  * @param PHYAddress: external PHY address                    

  * @retval : ETH_ERROR: Ethernet initialization failed

  *   ETH_SUCCESS: Ethernet successfully initialized                 

  */

uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress)

{

  uint32_t RegValue = 0, tmpreg = 0;

  __IO uint32_t i = 0;

  RCC_ClocksTypeDef  rcc_clocks;

  uint32_t hclk = 120000000;

  __IO uint32_t timeout = 0;

  /* Check the parameters */

  /* MAC --------------------------*/ 

  assert_param(IS_ETH_AUTONEGOTIATION(ETH_InitStruct->ETH_AutoNegotiation));

  assert_param(IS_ETH_WATCHDOG(ETH_InitStruct->ETH_Watchdog));

  assert_param(IS_ETH_JABBER(ETH_InitStruct->ETH_Jabber));

  assert_param(IS_ETH_INTER_FRAME_GAP(ETH_InitStruct->ETH_InterFrameGap));

  assert_param(IS_ETH_CARRIER_SENSE(ETH_InitStruct->ETH_CarrierSense));

  assert_param(IS_ETH_SPEED(ETH_InitStruct->ETH_Speed));

  assert_param(IS_ETH_RECEIVE_OWN(ETH_InitStruct->ETH_ReceiveOwn));

  assert_param(IS_ETH_LOOPBACK_MODE(ETH_InitStruct->ETH_LoopbackMode));

  assert_param(IS_ETH_DUPLEX_MODE(ETH_InitStruct->ETH_Mode));

  assert_param(IS_ETH_CHECKSUM_OFFLOAD(ETH_InitStruct->ETH_ChecksumOffload));

  assert_param(IS_ETH_RETRY_TRANSMISSION(ETH_InitStruct->ETH_RetryTransmission));

  assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(ETH_InitStruct->ETH_AutomaticPadCRCStrip));

  assert_param(IS_ETH_BACKOFF_LIMIT(ETH_InitStruct->ETH_BackOffLimit));

  assert_param(IS_ETH_DEFERRAL_CHECK(ETH_InitStruct->ETH_DeferralCheck));

  assert_param(IS_ETH_RECEIVE_ALL(ETH_InitStruct->ETH_ReceiveAll));

  assert_param(IS_ETH_SOURCE_ADDR_FILTER(ETH_InitStruct->ETH_SourceAddrFilter));

  assert_param(IS_ETH_CONTROL_FRAMES(ETH_InitStruct->ETH_PassControlFrames));

  assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(ETH_InitStruct->ETH_BroadcastFramesReception));

  assert_param(IS_ETH_DESTINATION_ADDR_FILTER(ETH_InitStruct->ETH_DestinationAddrFilter));

  assert_param(IS_ETH_PROMISCUOUS_MODE(ETH_InitStruct->ETH_PromiscuousMode));

  assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(ETH_InitStruct->ETH_MulticastFramesFilter));  

  assert_param(IS_ETH_UNICAST_FRAMES_FILTER(ETH_InitStruct->ETH_UnicastFramesFilter));

  assert_param(IS_ETH_PAUSE_TIME(ETH_InitStruct->ETH_PauseTime));

  assert_param(IS_ETH_ZEROQUANTA_PAUSE(ETH_InitStruct->ETH_ZeroQuantaPause));

  assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(ETH_InitStruct->ETH_PauseLowThreshold));

  assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(ETH_InitStruct->ETH_UnicastPauseFrameDetect));

  assert_param(IS_ETH_RECEIVE_FLOWCONTROL(ETH_InitStruct->ETH_ReceiveFlowControl));

  assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(ETH_InitStruct->ETH_TransmitFlowControl));

  assert_param(IS_ETH_VLAN_TAG_COMPARISON(ETH_InitStruct->ETH_VLANTagComparison));

  assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(ETH_InitStruct->ETH_VLANTagIdentifier));

  /* DMA --------------------------*/

  assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame));

  assert_param(IS_ETH_RECEIVE_STORE_FORWARD(ETH_InitStruct->ETH_ReceiveStoreForward));

  assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(ETH_InitStruct->ETH_FlushReceivedFrame));

  assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(ETH_InitStruct->ETH_TransmitStoreForward));

  assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(ETH_InitStruct->ETH_TransmitThresholdControl));

  assert_param(IS_ETH_FORWARD_ERROR_FRAMES(ETH_InitStruct->ETH_ForwardErrorFrames));

  assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(ETH_InitStruct->ETH_ForwardUndersizedGoodFrames));

  assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(ETH_InitStruct->ETH_ReceiveThresholdControl));

  assert_param(IS_ETH_SECOND_FRAME_OPERATE(ETH_InitStruct->ETH_SecondFrameOperate));

  assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(ETH_InitStruct->ETH_AddressAlignedBeats));

  assert_param(IS_ETH_FIXED_BURST(ETH_InitStruct->ETH_FixedBurst));

  assert_param(IS_ETH_RXDMA_BURST_LENGTH(ETH_InitStruct->ETH_RxDMABurstLength));

  assert_param(IS_ETH_TXDMA_BURST_LENGTH(ETH_InitStruct->ETH_TxDMABurstLength)); 

  assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(ETH_InitStruct->ETH_DescriptorSkipLength));  

  assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(ETH_InitStruct->ETH_DMAArbitration));       

  /*-------------------------------- MAC Config ------------------------------*/   

  /*---------------------- ETHERNET MACMIIAR Configuration -------------------*/

  /* Get the ETHERNET MACMIIAR value */

  tmpreg = ETH->MACMIIAR;

  /* Clear CSR Clock Range CR[2:0] bits */

  tmpreg &= MACMIIAR_CR_Mask;

  /* Get hclk frequency value */

  RCC_GetClocksFreq(&rcc_clocks);

  hclk = rcc_clocks.HCLK_Frequency;

  /* Set CR bits depending on hclk value */

  if((hclk >= 20000000)&&(hclk < 35000000))

  {

    /* CSR Clock Range between 20-35 MHz */

    tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div16;

  }

  else if((hclk >= 35000000)&&(hclk < 60000000))

  {

    /* CSR Clock Range between 35-60 MHz */ 

    tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div26;    

  }  

  else if((hclk >= 60000000)&&(hclk <= 100000000)) 

  {

    /* CSR Clock Range between 60-100 MHz */   

    tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42;    

  }

  else /*if((hclk >= 100000000)&&(hclk <= 120000000)) */

  {

    /* CSR Clock Range between 100-120 MHz */   

    tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div62;    

  }

  /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */

  ETH->MACMIIAR = (uint32_t)tmpreg;  

  /*-------------------- PHY initialization and configuration ----------------*/

  /* Put the PHY in reset mode */

  if(!(ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_Reset)))

  {

    /* Return ERROR in case of write timeout */

    return ETH_ERROR;

  }

  /* Delay to assure PHY reset */

  for(i = PHY_ResetDelay; i != 0; i--)

  {

  }

  if(ETH_InitStruct->ETH_AutoNegotiation != ETH_AutoNegotiation_Disable)

  {  

    /* We wait for linked satus... */

    do

    {

      timeout++;

    } while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_Linked_Status) && (timeout < PHY_READ_TO));

    /* Return ERROR in case of timeout */

    if(timeout == PHY_READ_TO)

    {

      return ETH_ERROR;

    }

    /* Reset Timeout counter */

    timeout = 0;

    /* Enable Auto-Negotiation */

    if(!(ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_AutoNegotiation)))

    {

      /* Return ERROR in case of write timeout */

      return ETH_ERROR;

    }

    /* Wait until the autonegotiation will be completed */

    do

    {

      timeout++;

    } while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_AutoNego_Complete) && (timeout < (uint32_t)PHY_READ_TO));  

    /* Return ERROR in case of timeout */

    if(timeout == PHY_READ_TO)

    {

      return ETH_ERROR;

    }

    /* Reset Timeout counter */

    timeout = 0;

    /* Read the result of the autonegotiation */

    RegValue = ETH_ReadPHYRegister(PHYAddress, PHY_SR);

    /* Configure the MAC with the Duplex Mode fixed by the autonegotiation process */

    if((RegValue & PHY_Duplex_Status) != (uint32_t)RESET)

    {

      /* Set Ethernet duplex mode to FullDuplex following the autonegotiation */

      ETH_InitStruct->ETH_Mode = ETH_Mode_FullDuplex;

    }

    else

    {

      /* Set Ethernet duplex mode to HalfDuplex following the autonegotiation */

      ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex;           

    }

    /* Configure the MAC with the speed fixed by the autonegotiation process */

    if(RegValue & PHY_Speed_Status)

    {  

      /* Set Ethernet speed to 10M following the autonegotiation */    

      ETH_InitStruct->ETH_Speed = ETH_Speed_10M; 

    }

    else

    {   

      /* Set Ethernet speed to 100M following the autonegotiation */ 

      ETH_InitStruct->ETH_Speed = ETH_Speed_100M;      

    }    

  }

  else

  {

    if(!ETH_WritePHYRegister(PHYAddress, PHY_BCR, ((uint16_t)(ETH_InitStruct->ETH_Mode >> 3) |

                                                   (uint16_t)(ETH_InitStruct->ETH_Speed >> 1))))

    {

      /* Return ERROR in case of write timeout */

      return ETH_ERROR;

    }

    /* Delay to assure PHY configuration */

    for(i = PHY_ConfigDelay; i != 0; i--)

    {

    }

  }

  /*------------------------ ETHERNET MACCR Configuration --------------------*/

  /* Get the ETHERNET MACCR value */  

  tmpreg = ETH->MACCR;

  /* Clear WD, PCE, PS, TE and RE bits */

  tmpreg &= MACCR_CLEAR_Mask;

  /* Set the WD bit according to ETH_Watchdog value */

  /* Set the JD: bit according to ETH_Jabber value */

  /* Set the IFG bit according to ETH_InterFrameGap value */ 

  /* Set the DCRS bit according to ETH_CarrierSense value */  

  /* Set the FES bit according to ETH_Speed value */ 

  /* Set the DO bit according to ETH_ReceiveOwn value */ 

  /* Set the LM bit according to ETH_LoopbackMode value */ 

  /* Set the DM bit according to ETH_Mode value */ 

  /* Set the IPC bit according to ETH_ChecksumOffload value */                   

  /* Set the DR bit according to ETH_RetryTransmission value */ 

  /* Set the ACS bit according to ETH_AutomaticPadCRCStrip value */ 

  /* Set the BL bit according to ETH_BackOffLimit value */ 

  /* Set the DC bit according to ETH_DeferralCheck value */                          

  tmpreg |= (uint32_t)(ETH_InitStruct->ETH_Watchdog | 

                  ETH_InitStruct->ETH_Jabber | 

                  ETH_InitStruct->ETH_InterFrameGap |

                  ETH_InitStruct->ETH_CarrierSense |

                  ETH_InitStruct->ETH_Speed | 

                  ETH_InitStruct->ETH_ReceiveOwn |

                  ETH_InitStruct->ETH_LoopbackMode |

                  ETH_InitStruct->ETH_Mode | 

                  ETH_InitStruct->ETH_ChecksumOffload |    

                  ETH_InitStruct->ETH_RetryTransmission | 

                  ETH_InitStruct->ETH_AutomaticPadCRCStrip | 

                  ETH_InitStruct->ETH_BackOffLimit | 

                  ETH_InitStruct->ETH_DeferralCheck);

  /* Write to ETHERNET MACCR */

  ETH->MACCR = (uint32_t)tmpreg;

  /*----------------------- ETHERNET MACFFR Configuration --------------------*/ 

  /* Set the RA bit according to ETH_ReceiveAll value */

  /* Set the SAF and SAIF bits according to ETH_SourceAddrFilter value */

  /* Set the PCF bit according to ETH_PassControlFrames value */

  /* Set the DBF bit according to ETH_BroadcastFramesReception value */

  /* Set the DAIF bit according to ETH_DestinationAddrFilter value */

  /* Set the PR bit according to ETH_PromiscuousMode value */

  /* Set the PM, HMC and HPF bits according to ETH_MulticastFramesFilter value */

  /* Set the HUC and HPF bits according to ETH_UnicastFramesFilter value */

  /* Write to ETHERNET MACFFR */  

  ETH->MACFFR = (uint32_t)(ETH_InitStruct->ETH_ReceiveAll | 

                          ETH_InitStruct->ETH_SourceAddrFilter |

                          ETH_InitStruct->ETH_PassControlFrames |

                          ETH_InitStruct->ETH_BroadcastFramesReception | 

                          ETH_InitStruct->ETH_DestinationAddrFilter |

                          ETH_InitStruct->ETH_PromiscuousMode |

                          ETH_InitStruct->ETH_MulticastFramesFilter |

                          ETH_InitStruct->ETH_UnicastFramesFilter); 

  /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/

  /* Write to ETHERNET MACHTHR */

  ETH->MACHTHR = (uint32_t)ETH_InitStruct->ETH_HashTableHigh;

  /* Write to ETHERNET MACHTLR */

  ETH->MACHTLR = (uint32_t)ETH_InitStruct->ETH_HashTableLow;

  /*----------------------- ETHERNET MACFCR Configuration --------------------*/

  /* Get the ETHERNET MACFCR value */  

  tmpreg = ETH->MACFCR;

  /* Clear xx bits */

  tmpreg &= MACFCR_CLEAR_Mask;

  /* Set the PT bit according to ETH_PauseTime value */

  /* Set the DZPQ bit according to ETH_ZeroQuantaPause value */

  /* Set the PLT bit according to ETH_PauseLowThreshold value */

  /* Set the UP bit according to ETH_UnicastPauseFrameDetect value */

  /* Set the RFE bit according to ETH_ReceiveFlowControl value */

  /* Set the TFE bit according to ETH_TransmitFlowControl value */  

  tmpreg |= (uint32_t)((ETH_InitStruct->ETH_PauseTime << 16) | 

                   ETH_InitStruct->ETH_ZeroQuantaPause |

                   ETH_InitStruct->ETH_PauseLowThreshold |

                   ETH_InitStruct->ETH_UnicastPauseFrameDetect | 

                   ETH_InitStruct->ETH_ReceiveFlowControl |

                   ETH_InitStruct->ETH_TransmitFlowControl); 

  /* Write to ETHERNET MACFCR */

  ETH->MACFCR = (uint32_t)tmpreg;

  /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/

  /* Set the ETV bit according to ETH_VLANTagComparison value */

  /* Set the VL bit according to ETH_VLANTagIdentifier value */  

  ETH->MACVLANTR = (uint32_t)(ETH_InitStruct->ETH_VLANTagComparison | 

                             ETH_InitStruct->ETH_VLANTagIdentifier); 

  /*-------------------------------- DMA Config ------------------------------*/

  /*----------------------- ETHERNET DMAOMR Configuration --------------------*/

  /* Get the ETHERNET DMAOMR value */  

  tmpreg = ETH->DMAOMR;

  /* Clear xx bits */

  tmpreg &= DMAOMR_CLEAR_Mask;

  /* Set the DT bit according to ETH_DropTCPIPChecksumErrorFrame value */

  /* Set the RSF bit according to ETH_ReceiveStoreForward value */

  /* Set the DFF bit according to ETH_FlushReceivedFrame value */

  /* Set the TSF bit according to ETH_TransmitStoreForward value */

  /* Set the TTC bit according to ETH_TransmitThresholdControl value */

  /* Set the FEF bit according to ETH_ForwardErrorFrames value */

  /* Set the FUF bit according to ETH_ForwardUndersizedGoodFrames value */

  /* Set the RTC bit according to ETH_ReceiveThresholdControl value */

  /* Set the OSF bit according to ETH_SecondFrameOperate value */

  tmpreg |= (uint32_t)(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame | 

                  ETH_InitStruct->ETH_ReceiveStoreForward |

                  ETH_InitStruct->ETH_FlushReceivedFrame |

                  ETH_InitStruct->ETH_TransmitStoreForward | 

                  ETH_InitStruct->ETH_TransmitThresholdControl |

                  ETH_InitStruct->ETH_ForwardErrorFrames |

                  ETH_InitStruct->ETH_ForwardUndersizedGoodFrames |

                  ETH_InitStruct->ETH_ReceiveThresholdControl |                                   

                  ETH_InitStruct->ETH_SecondFrameOperate); 

  /* Write to ETHERNET DMAOMR */

  ETH->DMAOMR = (uint32_t)tmpreg;

  /*----------------------- ETHERNET DMABMR Configuration --------------------*/ 

  /* Set the AAL bit according to ETH_AddressAlignedBeats value */

  /* Set the FB bit according to ETH_FixedBurst value */

  /* Set the RPBL and 4*PBL bits according to ETH_RxDMABurstLength value */

  /* Set the PBL and 4*PBL bits according to ETH_TxDMABurstLength value */

  /* Set the DSL bit according to ETH_DesciptorSkipLength value */

  /* Set the PR and DA bits according to ETH_DMAArbitration value */         

  ETH->DMABMR = (uint32_t)(ETH_InitStruct->ETH_AddressAlignedBeats | 

                          ETH_InitStruct->ETH_FixedBurst |

                          ETH_InitStruct->ETH_RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */

                          ETH_InitStruct->ETH_TxDMABurstLength | 

                         (ETH_InitStruct->ETH_DescriptorSkipLength << 2) |

                          ETH_InitStruct->ETH_DMAArbitration |

                          ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */  

  /* Return Ethernet configuration success */

  return ETH_SUCCESS;

}

/**

  * @brief  Fills each ETH_InitStruct member with its default value.

  * @param ETH_InitStruct: pointer to a ETH_InitTypeDef structure

  *   which will be initialized.

  * @retval : None

  */

void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct)

{

  /* ETH_InitStruct members default value */

  /*------------------------   MAC   -----------------------------------*/     

  ETH_InitStruct->ETH_AutoNegotiation = ETH_AutoNegotiation_Disable;           

  ETH_InitStruct->ETH_Watchdog = ETH_Watchdog_Enable;                   

  ETH_InitStruct->ETH_Jabber = ETH_Jabber_Enable;                                                     

  ETH_InitStruct->ETH_InterFrameGap = ETH_InterFrameGap_96Bit;                                                                                                                          

  ETH_InitStruct->ETH_CarrierSense = ETH_CarrierSense_Enable;                              

  ETH_InitStruct->ETH_Speed = ETH_Speed_10M;                       

  ETH_InitStruct->ETH_ReceiveOwn = ETH_ReceiveOwn_Enable;               

  ETH_InitStruct->ETH_LoopbackMode = ETH_LoopbackMode_Disable;              

  ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex;                       

  ETH_InitStruct->ETH_ChecksumOffload = ETH_ChecksumOffload_Disable;                                                            

  ETH_InitStruct->ETH_RetryTransmission = ETH_RetryTransmission_Enable;                                                                                  

  ETH_InitStruct->ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable;                                                         

  ETH_InitStruct->ETH_BackOffLimit = ETH_BackOffLimit_10;                                                                

  ETH_InitStruct->ETH_DeferralCheck = ETH_DeferralCheck_Disable;                                                                                                                  

  ETH_InitStruct->ETH_ReceiveAll = ETH_ReceiveAll_Disable;                                                               

  ETH_InitStruct->ETH_SourceAddrFilter = ETH_SourceAddrFilter_Disable;                                

  ETH_InitStruct->ETH_PassControlFrames = ETH_PassControlFrames_BlockAll;          

  ETH_InitStruct->ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable;

  ETH_InitStruct->ETH_DestinationAddrFilter = ETH_DestinationAddrFilter_Normal;      

  ETH_InitStruct->ETH_PromiscuousMode = ETH_PromiscuousMode_Disable;                                                             

  ETH_InitStruct->ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect;      

  ETH_InitStruct->ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect;      

  ETH_InitStruct->ETH_HashTableHigh = 0x0;                

  ETH_InitStruct->ETH_HashTableLow = 0x0;                     

  ETH_InitStruct->ETH_PauseTime = 0x0;                 

  ETH_InitStruct->ETH_ZeroQuantaPause = ETH_ZeroQuantaPause_Disable;            

  ETH_InitStruct->ETH_PauseLowThreshold = ETH_PauseLowThreshold_Minus4;         

  ETH_InitStruct->ETH_UnicastPauseFrameDetect = ETH_UnicastPauseFrameDetect_Disable;   

  ETH_InitStruct->ETH_ReceiveFlowControl = ETH_ReceiveFlowControl_Disable;        

  ETH_InitStruct->ETH_TransmitFlowControl = ETH_TransmitFlowControl_Disable;      

  ETH_InitStruct->ETH_VLANTagComparison = ETH_VLANTagComparison_16Bit;          

  ETH_InitStruct->ETH_VLANTagIdentifier = 0x0;          

  /*------------------------   DMA   -----------------------------------*/  

  ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Disable; 

  ETH_InitStruct->ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable;       

  ETH_InitStruct->ETH_FlushReceivedFrame = ETH_FlushReceivedFrame_Disable;       

  ETH_InitStruct->ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable;     

  ETH_InitStruct->ETH_TransmitThresholdControl = ETH_TransmitThresholdControl_64Bytes;  

  ETH_InitStruct->ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable;       

  ETH_InitStruct->ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable; 

  ETH_InitStruct->ETH_ReceiveThresholdControl = ETH_ReceiveThresholdControl_64Bytes;   

  ETH_InitStruct->ETH_SecondFrameOperate = ETH_SecondFrameOperate_Disable;

  ETH_InitStruct->ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable;

  ETH_InitStruct->ETH_FixedBurst = ETH_FixedBurst_Disable;

  ETH_InitStruct->ETH_RxDMABurstLength = ETH_RxDMABurstLength_1Beat;

  ETH_InitStruct->ETH_TxDMABurstLength = ETH_TxDMABurstLength_1Beat;

  ETH_InitStruct->ETH_DescriptorSkipLength = 0x0;

  ETH_InitStruct->ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_1_1;

}

/**

  * @brief  Enables ENET MAC and DMA reception/transmission 

  * @param  None

  * @retval : None

  */

void ETH_Start(void)

{

  /* Enable transmit state machine of the MAC for transmission on the MII */  

  ETH_MACTransmissionCmd(ENABLE);

  /* Flush Transmit FIFO */

  ETH_FlushTransmitFIFO();

  /* Enable receive state machine of the MAC for reception from the MII */  

  ETH_MACReceptionCmd(ENABLE);

  /* Start DMA transmission */

  ETH_DMATransmissionCmd(ENABLE); 

  /* Start DMA reception */

  ETH_DMAReceptionCmd(ENABLE);   

}

/**

  * @brief  Transmits a packet, from application buffer, pointed by ppkt.

  * @param ppkt: pointer to application packet buffer to transmit.

  * @param FrameLength: Tx Packet size.

  * @retval : ETH_ERROR: in case of Tx desc owned by DMA

  *   ETH_SUCCESS: for correct transmission

  */

uint32_t ETH_HandleTxPkt(uint8_t *ppkt, uint16_t FrameLength)

{ 

  uint32_t offset = 0;

  /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */

  if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET)

  {

    /* Return ERROR: OWN bit set */

    return ETH_ERROR;

  }

  /* Copy the frame to be sent into memory pointed by the current ETHERNET DMA Tx descriptor */      

  for(offset=0; offset<FrameLength; offset++)       

  {

    (*(__IO uint8_t *)((DMATxDescToSet->Buffer1Addr) + offset)) = (*(ppkt + offset));

  }

  /* Setting the Frame Length: bits[12:0] */

  DMATxDescToSet->ControlBufferSize = (FrameLength & ETH_DMATxDesc_TBS1);

  /* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */    

  DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS;

  /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */

  DMATxDescToSet->Status |= ETH_DMATxDesc_OWN;

  /* When Tx Buffer unavailable flag is set: clear it and resume transmission */

  if ((ETH->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)

  {

    /* Clear TBUS ETHERNET DMA flag */

    ETH->DMASR = ETH_DMASR_TBUS;

    /* Resume DMA transmission*/

    ETH->DMATPDR = 0;

  }

  /* Update the ETHERNET DMA global Tx descriptor with next Tx decriptor */  

  /* Chained Mode */

  if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (uint32_t)RESET)

  {     

    /* Selects the next DMA Tx descriptor list for next buffer to send */ 

    DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMATxDescToSet->Buffer2NextDescAddr);    

  }

  else /* Ring Mode */

  {  

    if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (uint32_t)RESET)

    {

      /* Selects the first DMA Tx descriptor for next buffer to send: last Tx descriptor was used */

      DMATxDescToSet = (ETH_DMADESCTypeDef*) (ETH->DMATDLAR);      

    }

    else

    {  

      /* Selects the next DMA Tx descriptor list for next buffer to send */

      DMATxDescToSet = (ETH_DMADESCTypeDef*) ((uint32_t)DMATxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2));      

    }

  }

  /* Return SUCCESS */

  return ETH_SUCCESS;   

}

/**

  * @brief  Receives a packet and copies it to memory pointed by ppkt.

  * @param  ppkt: pointer to application packet receive buffer.

  * @retval : ETH_ERROR: if there is error in reception

  *   framelength: received packet size if packet reception is correct

  */

uint32_t ETH_HandleRxPkt(uint8_t *ppkt)

{ 

  uint32_t offset = 0, framelength = 0;

  /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */

  if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET)

  {

    /* Return error: OWN bit set */

    return ETH_ERROR; 

  }

  if(((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) && 

     ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) &&  

     ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET))  

  {      

    /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */

    framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARxDesc_FrameLengthShift) - 4;

    /* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */

    for(offset=0; offset<framelength; offset++)       

    {

      (*(ppkt + offset)) = (*(__IO uint8_t *)((DMARxDescToGet->Buffer1Addr) + offset));

    }

  }

  else

  {

    /* Return ERROR */

    framelength = ETH_ERROR;

  }

  /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */

  DMARxDescToGet->Status = ETH_DMARxDesc_OWN; 

  /* When Rx Buffer unavailable flag is set: clear it and resume reception */

  if ((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET)  

  {

    /* Clear RBUS ETHERNET DMA flag */

    ETH->DMASR = ETH_DMASR_RBUS;

    /* Resume DMA reception */

    ETH->DMARPDR = 0;

  }

  /* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */      

  /* Chained Mode */

  if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET)

  {     

    /* Selects the next DMA Rx descriptor list for next buffer to read */ 

    DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr);    

  }

  else /* Ring Mode */

  {   

    if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET)

    {

      /* Selects the first DMA Rx descriptor for next buffer to read: last Rx descriptor was used */

      DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR);      

    }

    else

    { 

      /* Selects the next DMA Rx descriptor list for next buffer to read */

      DMARxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2));      

    }

  }

  /* Return Frame Length/ERROR */

  return (framelength);  

}

/**

  * @brief  Get the size of received the received packet.

  * @param  None

  * @retval : framelength: received packet size 

  */

uint32_t ETH_GetRxPktSize(void)

{

  uint32_t frameLength = 0;

  if(((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) == (uint32_t)RESET) &&

     ((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) &&

     ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) &&

     ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET))

  {

    /* Get the size of the packet: including 4 bytes of the CRC */

    frameLength = ETH_GetDMARxDescFrameLength(DMARxDescToGet);

  }

 /* Return Frame Length */ 

 return frameLength;

}

/**

  * @brief  Drop a Received packet (too small packet, etc...)

  * @param  None

  * @retval : None

  */

void ETH_DropRxPkt(void)

{

  /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */

  DMARxDescToGet->Status = ETH_DMARxDesc_OWN;  

  /* Chained Mode */

  if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET)

  {

    /* Selects the next DMA Rx descriptor list for next buffer read */

    DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr);

  }

  else /* Ring Mode */

  {

    if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET)

    {

      /* Selects the next DMA Rx descriptor list for next buffer read: this will

         be the first Rx descriptor in this case */

      DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR);

    }

    else

    {

      /* Selects the next DMA Rx descriptor list for next buffer read */

      DMARxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2));

    }

  }

}

/*---------------------------------  PHY  ------------------------------------*/

/**

  * @brief  Read a PHY register

  * @param PHYAddress: PHY device address, is the index of one of supported

  *   32 PHY devices. 

  *   This parameter can be one of the following values: 0,..,31                  

  * @param PHYReg: PHY register address, is the index of one of the 32

  *   PHY register. 

  *   This parameter can be one of the following values: 

  * @arg PHY_BCR    : Tranceiver Basic Control Register 

  * @arg PHY_BSR    : Tranceiver Basic Status Register 

  * @arg PHY_SR     : Tranceiver Status Register    

  * @arg More PHY register could be read depending on the used PHY

  * @retval : ETH_ERROR: in case of timeout

  *   MAC MIIDR register value: Data read from the selected PHY register (correct read )

  */

uint16_t ETH_ReadPHYRegister(uint16_t PHYAddress, uint16_t PHYReg)

{

  uint32_t tmpreg = 0;     

__IO uint32_t timeout = 0;

  /* Check the parameters */

  assert_param(IS_ETH_PHY_ADDRESS(PHYAddress));

  assert_param(IS_ETH_PHY_REG(PHYReg));

  /* Get the ETHERNET MACMIIAR value */

  tmpreg = ETH->MACMIIAR;

  /* Keep only the CSR Clock Range CR[2:0] bits value */

  tmpreg &= ~MACMIIAR_CR_Mask;

  /* Prepare the MII address register value */

  tmpreg |=(((uint32_t)PHYAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */

  tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR);      /* Set the PHY register address */

  tmpreg &= ~ETH_MACMIIAR_MW;                              /* Set the read mode */

  tmpreg |= ETH_MACMIIAR_MB;                               /* Set the MII Busy bit */

  /* Write the result value into the MII Address register */

  ETH->MACMIIAR = tmpreg;

  /* Check for the Busy flag */

  do

  {

    timeout++;

    tmpreg = ETH->MACMIIAR;

  } while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_READ_TO));

  /* Return ERROR in case of timeout */

  if(timeout == PHY_READ_TO)

  {

    return (uint16_t)ETH_ERROR;

  }

  /* Return data register value */

  return (uint16_t)(ETH->MACMIIDR);

}

/**

  * @brief  Write to a PHY register

  * @param PHYAddress: PHY device address, is the index of one of supported

  *   32 PHY devices. 

  *   This parameter can be one of the following values: 0,..,31

  * @param PHYReg: PHY register address, is the index of one of the 32

  *   PHY register. 

  *   This parameter can be one of the following values: 

  * @arg PHY_BCR    : Tranceiver Control Register  

  * @arg More PHY register could be written depending on the used PHY

  * @param PHYValue: the value to write

  * @retval : ETH_ERROR: in case of timeout

  *   ETH_SUCCESS: for correct write

  */

uint32_t ETH_WritePHYRegister(uint16_t PHYAddress, uint16_t PHYReg, uint16_t PHYValue)

{

  uint32_t tmpreg = 0;     

  __IO uint32_t timeout = 0;

  /* Check the parameters */

  assert_param(IS_ETH_PHY_ADDRESS(PHYAddress));

  assert_param(IS_ETH_PHY_REG(PHYReg));

  /* Get the ETHERNET MACMIIAR value */

  tmpreg = ETH->MACMIIAR;

  /* Keep only the CSR Clock Range CR[2:0] bits value */

  tmpreg &= ~MACMIIAR_CR_Mask;

  /* Prepare the MII register address value */

  tmpreg |=(((uint32_t)PHYAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */

  tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR);      /* Set the PHY register address */

  tmpreg |= ETH_MACMIIAR_MW;                               /* Set the write mode */

  tmpreg |= ETH_MACMIIAR_MB;                               /* Set the MII Busy bit */

  /* Give the value to the MII data register */

  ETH->MACMIIDR = PHYValue;

  /* Write the result value into the MII Address register */

  ETH->MACMIIAR = tmpreg;

  /* Check for the Busy flag */

  do

  {

    timeout++;

    tmpreg = ETH->MACMIIAR;

  } while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_WRITE_TO));

  /* Return ERROR in case of timeout */

  if(timeout == PHY_WRITE_TO)

  {

    return ETH_ERROR;

  }

  /* Return SUCCESS */

  return ETH_SUCCESS;  

}

/**

  * @brief  Enables or disables the PHY loopBack mode.

  * @param PHYAddress: PHY device address, is the index of one of supported

  *   32 PHY devices. 

  *   This parameter can be one of the following values:                   

  * @param NewState: new state of the PHY loopBack mode.

  *   This parameter can be: ENABLE or DISABLE.    

  *   Note: Don't be confused with ETH_MACLoopBackCmd function

  *   which enables internal loopback at MII level

  * @retval : ETH_ERROR: in case of bad PHY configuration

  *   ETH_SUCCESS: for correct PHY configuration

  */

uint32_t ETH_PHYLoopBackCmd(uint16_t PHYAddress, FunctionalState NewState)

{

  uint16_t tmpreg = 0;

  /* Check the parameters */

  assert_param(IS_ETH_PHY_ADDRESS(PHYAddress));

  assert_param(IS_FUNCTIONAL_STATE(NewState));

  /* Get the PHY configuration to update it */

  tmpreg = ETH_ReadPHYRegister(PHYAddress, PHY_BCR); 

  if (NewState != DISABLE)

  {

    /* Enable the PHY loopback mode */

    tmpreg |= PHY_Loopback;  

  }

  else

  {

    /* Disable the PHY loopback mode: normal mode */

    tmpreg &= (uint16_t)(~(uint16_t)PHY_Loopback);

  }

  /* Update the PHY control register with the new configuration */

  if(ETH_WritePHYRegister(PHYAddress, PHY_BCR, tmpreg) != (uint32_t)RESET)

  {

    return ETH_SUCCESS;

  }

  else

  {

    /* Return SUCCESS */

    return ETH_ERROR; 

  }   

}

/*---------------------------------  MAC  ------------------------------------*/

/**

  * @brief  Enables or disables the MAC transmission.

  * @param NewState: new state of the MAC transmission.

  *   This parameter can be: ENABLE or DISABLE.

  * @retval : None

  */

void ETH_MACTransmissionCmd(FunctionalState NewState)

{ 

  /* Check the parameters */

  assert_param(IS_FUNCTIONAL_STATE(NewState));

  if (NewState != DISABLE)

  {

    /* Enable the MAC transmission */

    ETH->MACCR |= ETH_MACCR_TE;  

  }

  else

  {

    /* Disable the MAC transmission */

    ETH->MACCR &= ~ETH_MACCR_TE;

  }

}

/**

  * @brief  Enables or disables the MAC reception.

  * @param NewState: new state of the MAC reception.

  *   This parameter can be: ENABLE or DISABLE.

  * @retval : None

  */

void ETH_MACReceptionCmd(FunctionalState NewState)

{ 

  /* Check the parameters */

  assert_param(IS_FUNCTIONAL_STATE(NewState));

  if (NewState != DISABLE)

  {

    /* Enable the MAC reception */

    ETH->MACCR |= ETH_MACCR_RE;  

  }

  else

  {

    /* Disable the MAC reception */

    ETH->MACCR &= ~ETH_MACCR_RE;

  }

}

/**

  * @brief  Checks whether the ETHERNET flow control busy bit is set or not.

  * @param  None

  * @retval : The new state of flow control busy status bit (SET or RESET).

  */

FlagStatus ETH_GetFlowControlBusyStatus(void)

{

  FlagStatus bitstatus = RESET;

  /* The Flow Control register should not be written to until this bit is cleared */

  if ((ETH->MACFCR & ETH_MACFCR_FCBBPA) != (uint32_t)RESET)

  {

    bitstatus = SET;

  }

  else

  {

    bitstatus = RESET;

  }

  return bitstatus;

}

/**

  * @brief  Initiate a Pause Control Frame (Full-duplex only).

  * @param  None

  * @retval : None

  */

void ETH_InitiatePauseControlFrame(void)  

{ 

  /* When Set In full duplex MAC initiates pause control frame */

  ETH->MACFCR |= ETH_MACFCR_FCBBPA;  

}

/**

  * @brief  Enables or disables the MAC BackPressure operation activation (Half-duplex only).

  * @param NewState: new state of the MAC BackPressure operation activation.

  *   This parameter can be: ENABLE or DISABLE.

  * @retval : None

  */

void ETH_BackPressureActivationCmd(FunctionalState NewState)   

{ 

  /* Check the parameters */

  assert_param(IS_FUNCTIONAL_STATE(NewState));

  if (NewState != DISABLE)

  {

    /* Activate the MAC BackPressure operation */

    /* In Half duplex: during backpressure, when the MAC receives a new frame,

    the transmitter starts sending a JAM pattern resulting in a collision */

    ETH->MACFCR |= ETH_MACFCR_FCBBPA; 

  }

  else

  {

    /* Desactivate the MAC BackPressure operation */

    ETH->MACFCR &= ~ETH_MACFCR_FCBBPA; 

  } 

}

/**

  * @brief  Checks whether the specified ETHERNET MAC flag is set or not.

  * @param ETH_MAC_FLAG: specifies the flag to check.

  *   This parameter can be one of the following values:

  * @arg ETH_MAC_FLAG_TST  : Time stamp trigger flag   

  * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag  

  * @arg ETH_MAC_FLAG_MMCR : MMC receive flag   

  * @arg ETH_MAC_FLAG_MMC  : MMC flag  

  * @arg ETH_MAC_FLAG_PMT  : PMT flag  

  * @retval : The new state of ETHERNET MAC flag (SET or RESET).

  */

FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG)

{

  FlagStatus bitstatus = RESET;

  /* Check the parameters */

  assert_param(IS_ETH_MAC_GET_FLAG(ETH_MAC_FLAG)); 

  if ((ETH->MACSR & ETH_MAC_FLAG) != (uint32_t)RESET)

  {

    bitstatus = SET;

  }

  else

  {

    bitstatus = RESET;

  }

  return bitstatus;

}

/**

  * @brief  Checks whether the specified ETHERNET MAC interrupt has occurred or not.

  * @param ETH_MAC_IT: specifies the interrupt source to check.

  *   This parameter can be one of the following values:

  * @arg ETH_MAC_IT_TST   : Time stamp trigger interrupt  

  * @arg ETH_MAC_IT_MMCT : MMC transmit interrupt 

  * @arg ETH_MAC_IT_MMCR : MMC receive interrupt  

  * @arg ETH_MAC_IT_MMC  : MMC interrupt 

  * @arg ETH_MAC_IT_PMT  : PMT interrupt 

  * @retval : The new state of ETHERNET MAC interrupt (SET or RESET).

  */

ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT)

{

  ITStatus bitstatus = RESET;

  /* Check the parameters */

  assert_param(IS_ETH_MAC_GET_IT(ETH_MAC_IT)); 

  if ((ETH->MACSR & ETH_MAC_IT) != (uint32_t)RESET)

  {

    bitstatus = SET;

  }

  else

  {

    bitstatus = RESET;

  }

  return bitstatus;

}

/**

  * @brief  Enables or disables the specified ETHERNET MAC interrupts.

  * @param ETH_MAC_IT: specifies the ETHERNET MAC interrupt sources to be

  *   enabled or disabled.

  *   This parameter can be any combination of the following values:

  * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt 

  * @arg ETH_MAC_IT_PMT : PMT interrupt 

  * @param NewState: new state of the specified ETHERNET MAC interrupts.

  *   This parameter can be: ENABLE or DISABLE.

  * @retval : None

  */

void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState)

{

  /* Check the parameters */

  assert_param(IS_ETH_MAC_IT(ETH_MAC_IT));

  assert_param(IS_FUNCTIONAL_STATE(NewState));  

  if (NewState != DISABLE)

  {

    /* Enable the selected ETHERNET MAC interrupts */

    ETH->MACIMR &= (~(uint32_t)ETH_MAC_IT);

  }

  else

  {

    /* Disable the selected ETHERNET MAC interrupts */

    ETH->MACIMR |= ETH_MAC_IT;

  }

}

/**

  * @brief  Configures the selected MAC address.

  * @param MacAddr: The MAC addres to configure.

  *   This parameter can be one of the following values:

  * @arg ETH_MAC_Address0 : MAC Address0 

  * @arg ETH_MAC_Address1 : MAC Address1 

  * @arg ETH_MAC_Address2 : MAC Address2

  * @arg ETH_MAC_Address3 : MAC Address3

  * @param Addr: Pointer on MAC address buffer data (6 bytes).

  * @retval : None

  */

void ETH_MACAddressConfig(uint32_t MacAddr, uint8_t *Addr)

{

  uint32_t tmpreg;

  /* Check the parameters */

  assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));

  /* Calculate the selectecd MAC address high register */