amiro-blt / Target / Demo / ARMCM3_STM32F103_DiWheelDrive_GCC / Boot / lib / STM32F10x_StdPeriph_Driver / src / stm32f10x_gpio.c @ 69661903
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1 | 69661903 | Thomas Schöpping | /**
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2 | ******************************************************************************
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3 | * @file stm32f10x_gpio.c
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4 | * @author MCD Application Team
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5 | * @version V3.5.0
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6 | * @date 11-March-2011
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7 | * @brief This file provides all the GPIO firmware functions.
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8 | ******************************************************************************
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9 | * @attention
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10 | *
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11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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17 | *
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18 | * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
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19 | ******************************************************************************
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20 | */
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21 | |||
22 | /* Includes ------------------------------------------------------------------*/
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23 | #include "stm32f10x_gpio.h" |
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24 | #include "stm32f10x_rcc.h" |
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25 | |||
26 | /** @addtogroup STM32F10x_StdPeriph_Driver
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27 | * @{
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28 | */
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29 | |||
30 | /** @defgroup GPIO
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31 | * @brief GPIO driver modules
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32 | * @{
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33 | */
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34 | |||
35 | /** @defgroup GPIO_Private_TypesDefinitions
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36 | * @{
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37 | */
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38 | |||
39 | /**
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40 | * @}
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41 | */
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42 | |||
43 | /** @defgroup GPIO_Private_Defines
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44 | * @{
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45 | */
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46 | |||
47 | /* ------------ RCC registers bit address in the alias region ----------------*/
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48 | #define AFIO_OFFSET (AFIO_BASE - PERIPH_BASE)
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49 | |||
50 | /* --- EVENTCR Register -----*/
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51 | |||
52 | /* Alias word address of EVOE bit */
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53 | #define EVCR_OFFSET (AFIO_OFFSET + 0x00) |
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54 | #define EVOE_BitNumber ((uint8_t)0x07) |
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55 | #define EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4)) |
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56 | |||
57 | |||
58 | /* --- MAPR Register ---*/
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59 | /* Alias word address of MII_RMII_SEL bit */
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60 | #define MAPR_OFFSET (AFIO_OFFSET + 0x04) |
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61 | #define MII_RMII_SEL_BitNumber ((u8)0x17) |
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62 | #define MAPR_MII_RMII_SEL_BB (PERIPH_BB_BASE + (MAPR_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4)) |
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63 | |||
64 | |||
65 | #define EVCR_PORTPINCONFIG_MASK ((uint16_t)0xFF80) |
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66 | #define LSB_MASK ((uint16_t)0xFFFF) |
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67 | #define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000) |
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68 | #define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF) |
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69 | #define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000) |
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70 | #define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000) |
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71 | /**
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72 | * @}
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73 | */
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74 | |||
75 | /** @defgroup GPIO_Private_Macros
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76 | * @{
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77 | */
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78 | |||
79 | /**
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80 | * @}
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81 | */
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82 | |||
83 | /** @defgroup GPIO_Private_Variables
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84 | * @{
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85 | */
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86 | |||
87 | /**
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88 | * @}
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89 | */
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90 | |||
91 | /** @defgroup GPIO_Private_FunctionPrototypes
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92 | * @{
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93 | */
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94 | |||
95 | /**
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96 | * @}
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97 | */
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98 | |||
99 | /** @defgroup GPIO_Private_Functions
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100 | * @{
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101 | */
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102 | |||
103 | /**
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104 | * @brief Deinitializes the GPIOx peripheral registers to their default reset values.
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105 | * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
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106 | * @retval None
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107 | */
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108 | void GPIO_DeInit(GPIO_TypeDef* GPIOx)
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109 | { |
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110 | /* Check the parameters */
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111 | assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); |
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112 | |||
113 | if (GPIOx == GPIOA)
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114 | { |
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115 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE); |
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116 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE); |
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117 | } |
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118 | else if (GPIOx == GPIOB) |
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119 | { |
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120 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE); |
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121 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE); |
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122 | } |
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123 | else if (GPIOx == GPIOC) |
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124 | { |
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125 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE); |
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126 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE); |
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127 | } |
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128 | else if (GPIOx == GPIOD) |
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129 | { |
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130 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE); |
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131 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE); |
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132 | } |
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133 | else if (GPIOx == GPIOE) |
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134 | { |
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135 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE); |
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136 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE); |
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137 | } |
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138 | else if (GPIOx == GPIOF) |
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139 | { |
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140 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, ENABLE); |
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141 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, DISABLE); |
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142 | } |
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143 | else
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144 | { |
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145 | if (GPIOx == GPIOG)
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146 | { |
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147 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, ENABLE); |
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148 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, DISABLE); |
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149 | } |
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150 | } |
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151 | } |
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152 | |||
153 | /**
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154 | * @brief Deinitializes the Alternate Functions (remap, event control
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155 | * and EXTI configuration) registers to their default reset values.
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156 | * @param None
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157 | * @retval None
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158 | */
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159 | void GPIO_AFIODeInit(void) |
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160 | { |
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161 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE); |
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162 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE); |
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163 | } |
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164 | |||
165 | /**
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166 | * @brief Initializes the GPIOx peripheral according to the specified
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167 | * parameters in the GPIO_InitStruct.
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168 | * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
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169 | * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that
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170 | * contains the configuration information for the specified GPIO peripheral.
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171 | * @retval None
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172 | */
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173 | void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
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174 | { |
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175 | uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00; |
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176 | uint32_t tmpreg = 0x00, pinmask = 0x00; |
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177 | /* Check the parameters */
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178 | assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); |
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179 | assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); |
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180 | assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); |
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181 | |||
182 | /*---------------------------- GPIO Mode Configuration -----------------------*/
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183 | currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F);
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184 | if ((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00) |
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185 | { |
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186 | /* Check the parameters */
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187 | assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed)); |
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188 | /* Output mode */
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189 | currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed; |
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190 | } |
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191 | /*---------------------------- GPIO CRL Configuration ------------------------*/
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192 | /* Configure the eight low port pins */
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193 | if (((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00) |
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194 | { |
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195 | tmpreg = GPIOx->CRL; |
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196 | for (pinpos = 0x00; pinpos < 0x08; pinpos++) |
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197 | { |
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198 | pos = ((uint32_t)0x01) << pinpos;
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199 | /* Get the port pins position */
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200 | currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; |
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201 | if (currentpin == pos)
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202 | { |
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203 | pos = pinpos << 2;
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204 | /* Clear the corresponding low control register bits */
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205 | pinmask = ((uint32_t)0x0F) << pos;
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206 | tmpreg &= ~pinmask; |
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207 | /* Write the mode configuration in the corresponding bits */
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208 | tmpreg |= (currentmode << pos); |
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209 | /* Reset the corresponding ODR bit */
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210 | if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
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211 | { |
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212 | GPIOx->BRR = (((uint32_t)0x01) << pinpos);
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213 | } |
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214 | else
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215 | { |
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216 | /* Set the corresponding ODR bit */
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217 | if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
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218 | { |
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219 | GPIOx->BSRR = (((uint32_t)0x01) << pinpos);
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220 | } |
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221 | } |
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222 | } |
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223 | } |
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224 | GPIOx->CRL = tmpreg; |
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225 | } |
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226 | /*---------------------------- GPIO CRH Configuration ------------------------*/
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227 | /* Configure the eight high port pins */
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228 | if (GPIO_InitStruct->GPIO_Pin > 0x00FF) |
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229 | { |
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230 | tmpreg = GPIOx->CRH; |
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231 | for (pinpos = 0x00; pinpos < 0x08; pinpos++) |
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232 | { |
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233 | pos = (((uint32_t)0x01) << (pinpos + 0x08)); |
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234 | /* Get the port pins position */
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235 | currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos); |
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236 | if (currentpin == pos)
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237 | { |
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238 | pos = pinpos << 2;
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239 | /* Clear the corresponding high control register bits */
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240 | pinmask = ((uint32_t)0x0F) << pos;
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241 | tmpreg &= ~pinmask; |
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242 | /* Write the mode configuration in the corresponding bits */
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243 | tmpreg |= (currentmode << pos); |
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244 | /* Reset the corresponding ODR bit */
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245 | if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
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246 | { |
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247 | GPIOx->BRR = (((uint32_t)0x01) << (pinpos + 0x08)); |
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248 | } |
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249 | /* Set the corresponding ODR bit */
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250 | if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
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251 | { |
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252 | GPIOx->BSRR = (((uint32_t)0x01) << (pinpos + 0x08)); |
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253 | } |
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254 | } |
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255 | } |
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256 | GPIOx->CRH = tmpreg; |
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257 | } |
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258 | } |
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259 | |||
260 | /**
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261 | * @brief Fills each GPIO_InitStruct member with its default value.
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262 | * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will
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263 | * be initialized.
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264 | * @retval None
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265 | */
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266 | void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
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267 | { |
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268 | /* Reset GPIO init structure parameters values */
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269 | GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; |
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270 | GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; |
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271 | GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING; |
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272 | } |
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273 | |||
274 | /**
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275 | * @brief Reads the specified input port pin.
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276 | * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
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277 | * @param GPIO_Pin: specifies the port bit to read.
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278 | * This parameter can be GPIO_Pin_x where x can be (0..15).
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279 | * @retval The input port pin value.
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280 | */
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281 | uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) |
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282 | { |
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283 | uint8_t bitstatus = 0x00;
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284 | |||
285 | /* Check the parameters */
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286 | assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); |
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287 | assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); |
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288 | |||
289 | if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)
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290 | { |
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291 | bitstatus = (uint8_t)Bit_SET; |
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292 | } |
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293 | else
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294 | { |
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295 | bitstatus = (uint8_t)Bit_RESET; |
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296 | } |
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297 | return bitstatus;
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298 | } |
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299 | |||
300 | /**
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301 | * @brief Reads the specified GPIO input data port.
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302 | * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
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303 | * @retval GPIO input data port value.
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304 | */
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305 | uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx) |
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306 | { |
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307 | /* Check the parameters */
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308 | assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); |
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309 | |||
310 | return ((uint16_t)GPIOx->IDR);
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311 | } |
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312 | |||
313 | /**
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314 | * @brief Reads the specified output data port bit.
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315 | * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
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316 | * @param GPIO_Pin: specifies the port bit to read.
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317 | * This parameter can be GPIO_Pin_x where x can be (0..15).
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318 | * @retval The output port pin value.
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319 | */
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320 | uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) |
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321 | { |
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322 | uint8_t bitstatus = 0x00;
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323 | /* Check the parameters */
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324 | assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); |
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325 | assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); |
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326 | |||
327 | if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)
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328 | { |
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329 | bitstatus = (uint8_t)Bit_SET; |
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330 | } |
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331 | else
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332 | { |
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333 | bitstatus = (uint8_t)Bit_RESET; |
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334 | } |
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335 | return bitstatus;
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336 | } |
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337 | |||
338 | /**
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339 | * @brief Reads the specified GPIO output data port.
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340 | * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
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341 | * @retval GPIO output data port value.
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342 | */
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343 | uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx) |
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344 | { |
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345 | /* Check the parameters */
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346 | assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); |
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347 | |||
348 | return ((uint16_t)GPIOx->ODR);
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349 | } |
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350 | |||
351 | /**
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352 | * @brief Sets the selected data port bits.
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353 | * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
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354 | * @param GPIO_Pin: specifies the port bits to be written.
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355 | * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
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356 | * @retval None
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357 | */
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358 | void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
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359 | { |
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360 | /* Check the parameters */
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361 | assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); |
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362 | assert_param(IS_GPIO_PIN(GPIO_Pin)); |
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363 | |||
364 | GPIOx->BSRR = GPIO_Pin; |
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365 | } |
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366 | |||
367 | /**
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368 | * @brief Clears the selected data port bits.
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369 | * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
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370 | * @param GPIO_Pin: specifies the port bits to be written.
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371 | * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
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372 | * @retval None
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373 | */
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374 | void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
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375 | { |
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376 | /* Check the parameters */
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377 | assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); |
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378 | assert_param(IS_GPIO_PIN(GPIO_Pin)); |
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379 | |||
380 | GPIOx->BRR = GPIO_Pin; |
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381 | } |
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382 | |||
383 | /**
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384 | * @brief Sets or clears the selected data port bit.
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385 | * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
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386 | * @param GPIO_Pin: specifies the port bit to be written.
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387 | * This parameter can be one of GPIO_Pin_x where x can be (0..15).
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388 | * @param BitVal: specifies the value to be written to the selected bit.
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389 | * This parameter can be one of the BitAction enum values:
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390 | * @arg Bit_RESET: to clear the port pin
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391 | * @arg Bit_SET: to set the port pin
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392 | * @retval None
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393 | */
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394 | void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
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395 | { |
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396 | /* Check the parameters */
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397 | assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); |
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398 | assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); |
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399 | assert_param(IS_GPIO_BIT_ACTION(BitVal)); |
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400 | |||
401 | if (BitVal != Bit_RESET)
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402 | { |
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403 | GPIOx->BSRR = GPIO_Pin; |
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404 | } |
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405 | else
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406 | { |
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407 | GPIOx->BRR = GPIO_Pin; |
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408 | } |
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409 | } |
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410 | |||
411 | /**
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412 | * @brief Writes data to the specified GPIO data port.
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413 | * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
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414 | * @param PortVal: specifies the value to be written to the port output data register.
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415 | * @retval None
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416 | */
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417 | void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
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418 | { |
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419 | /* Check the parameters */
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420 | assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); |
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421 | |||
422 | GPIOx->ODR = PortVal; |
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423 | } |
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424 | |||
425 | /**
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426 | * @brief Locks GPIO Pins configuration registers.
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427 | * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
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428 | * @param GPIO_Pin: specifies the port bit to be written.
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429 | * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
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430 | * @retval None
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431 | */
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432 | void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
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433 | { |
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434 | uint32_t tmp = 0x00010000;
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435 | |||
436 | /* Check the parameters */
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437 | assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); |
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438 | assert_param(IS_GPIO_PIN(GPIO_Pin)); |
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439 | |||
440 | tmp |= GPIO_Pin; |
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441 | /* Set LCKK bit */
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442 | GPIOx->LCKR = tmp; |
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443 | /* Reset LCKK bit */
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444 | GPIOx->LCKR = GPIO_Pin; |
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445 | /* Set LCKK bit */
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446 | GPIOx->LCKR = tmp; |
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447 | /* Read LCKK bit*/
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448 | tmp = GPIOx->LCKR; |
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449 | /* Read LCKK bit*/
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450 | tmp = GPIOx->LCKR; |
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451 | } |
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452 | |||
453 | /**
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454 | * @brief Selects the GPIO pin used as Event output.
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455 | * @param GPIO_PortSource: selects the GPIO port to be used as source
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456 | * for Event output.
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457 | * This parameter can be GPIO_PortSourceGPIOx where x can be (A..E).
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458 | * @param GPIO_PinSource: specifies the pin for the Event output.
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459 | * This parameter can be GPIO_PinSourcex where x can be (0..15).
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460 | * @retval None
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461 | */
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462 | void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
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463 | { |
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464 | uint32_t tmpreg = 0x00;
|
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465 | /* Check the parameters */
|
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466 | assert_param(IS_GPIO_EVENTOUT_PORT_SOURCE(GPIO_PortSource)); |
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467 | assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); |
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468 | |||
469 | tmpreg = AFIO->EVCR; |
||
470 | /* Clear the PORT[6:4] and PIN[3:0] bits */
|
||
471 | tmpreg &= EVCR_PORTPINCONFIG_MASK; |
||
472 | tmpreg |= (uint32_t)GPIO_PortSource << 0x04;
|
||
473 | tmpreg |= GPIO_PinSource; |
||
474 | AFIO->EVCR = tmpreg; |
||
475 | } |
||
476 | |||
477 | /**
|
||
478 | * @brief Enables or disables the Event Output.
|
||
479 | * @param NewState: new state of the Event output.
|
||
480 | * This parameter can be: ENABLE or DISABLE.
|
||
481 | * @retval None
|
||
482 | */
|
||
483 | void GPIO_EventOutputCmd(FunctionalState NewState)
|
||
484 | { |
||
485 | /* Check the parameters */
|
||
486 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
||
487 | |||
488 | *(__IO uint32_t *) EVCR_EVOE_BB = (uint32_t)NewState; |
||
489 | } |
||
490 | |||
491 | /**
|
||
492 | * @brief Changes the mapping of the specified pin.
|
||
493 | * @param GPIO_Remap: selects the pin to remap.
|
||
494 | * This parameter can be one of the following values:
|
||
495 | * @arg GPIO_Remap_SPI1 : SPI1 Alternate Function mapping
|
||
496 | * @arg GPIO_Remap_I2C1 : I2C1 Alternate Function mapping
|
||
497 | * @arg GPIO_Remap_USART1 : USART1 Alternate Function mapping
|
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498 | * @arg GPIO_Remap_USART2 : USART2 Alternate Function mapping
|
||
499 | * @arg GPIO_PartialRemap_USART3 : USART3 Partial Alternate Function mapping
|
||
500 | * @arg GPIO_FullRemap_USART3 : USART3 Full Alternate Function mapping
|
||
501 | * @arg GPIO_PartialRemap_TIM1 : TIM1 Partial Alternate Function mapping
|
||
502 | * @arg GPIO_FullRemap_TIM1 : TIM1 Full Alternate Function mapping
|
||
503 | * @arg GPIO_PartialRemap1_TIM2 : TIM2 Partial1 Alternate Function mapping
|
||
504 | * @arg GPIO_PartialRemap2_TIM2 : TIM2 Partial2 Alternate Function mapping
|
||
505 | * @arg GPIO_FullRemap_TIM2 : TIM2 Full Alternate Function mapping
|
||
506 | * @arg GPIO_PartialRemap_TIM3 : TIM3 Partial Alternate Function mapping
|
||
507 | * @arg GPIO_FullRemap_TIM3 : TIM3 Full Alternate Function mapping
|
||
508 | * @arg GPIO_Remap_TIM4 : TIM4 Alternate Function mapping
|
||
509 | * @arg GPIO_Remap1_CAN1 : CAN1 Alternate Function mapping
|
||
510 | * @arg GPIO_Remap2_CAN1 : CAN1 Alternate Function mapping
|
||
511 | * @arg GPIO_Remap_PD01 : PD01 Alternate Function mapping
|
||
512 | * @arg GPIO_Remap_TIM5CH4_LSI : LSI connected to TIM5 Channel4 input capture for calibration
|
||
513 | * @arg GPIO_Remap_ADC1_ETRGINJ : ADC1 External Trigger Injected Conversion remapping
|
||
514 | * @arg GPIO_Remap_ADC1_ETRGREG : ADC1 External Trigger Regular Conversion remapping
|
||
515 | * @arg GPIO_Remap_ADC2_ETRGINJ : ADC2 External Trigger Injected Conversion remapping
|
||
516 | * @arg GPIO_Remap_ADC2_ETRGREG : ADC2 External Trigger Regular Conversion remapping
|
||
517 | * @arg GPIO_Remap_ETH : Ethernet remapping (only for Connectivity line devices)
|
||
518 | * @arg GPIO_Remap_CAN2 : CAN2 remapping (only for Connectivity line devices)
|
||
519 | * @arg GPIO_Remap_SWJ_NoJTRST : Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST
|
||
520 | * @arg GPIO_Remap_SWJ_JTAGDisable : JTAG-DP Disabled and SW-DP Enabled
|
||
521 | * @arg GPIO_Remap_SWJ_Disable : Full SWJ Disabled (JTAG-DP + SW-DP)
|
||
522 | * @arg GPIO_Remap_SPI3 : SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices)
|
||
523 | * When the SPI3/I2S3 is remapped using this function, the SWJ is configured
|
||
524 | * to Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST.
|
||
525 | * @arg GPIO_Remap_TIM2ITR1_PTP_SOF : Ethernet PTP output or USB OTG SOF (Start of Frame) connected
|
||
526 | * to TIM2 Internal Trigger 1 for calibration (only for Connectivity line devices)
|
||
527 | * If the GPIO_Remap_TIM2ITR1_PTP_SOF is enabled the TIM2 ITR1 is connected to
|
||
528 | * Ethernet PTP output. When Reset TIM2 ITR1 is connected to USB OTG SOF output.
|
||
529 | * @arg GPIO_Remap_PTP_PPS : Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices)
|
||
530 | * @arg GPIO_Remap_TIM15 : TIM15 Alternate Function mapping (only for Value line devices)
|
||
531 | * @arg GPIO_Remap_TIM16 : TIM16 Alternate Function mapping (only for Value line devices)
|
||
532 | * @arg GPIO_Remap_TIM17 : TIM17 Alternate Function mapping (only for Value line devices)
|
||
533 | * @arg GPIO_Remap_CEC : CEC Alternate Function mapping (only for Value line devices)
|
||
534 | * @arg GPIO_Remap_TIM1_DMA : TIM1 DMA requests mapping (only for Value line devices)
|
||
535 | * @arg GPIO_Remap_TIM9 : TIM9 Alternate Function mapping (only for XL-density devices)
|
||
536 | * @arg GPIO_Remap_TIM10 : TIM10 Alternate Function mapping (only for XL-density devices)
|
||
537 | * @arg GPIO_Remap_TIM11 : TIM11 Alternate Function mapping (only for XL-density devices)
|
||
538 | * @arg GPIO_Remap_TIM13 : TIM13 Alternate Function mapping (only for High density Value line and XL-density devices)
|
||
539 | * @arg GPIO_Remap_TIM14 : TIM14 Alternate Function mapping (only for High density Value line and XL-density devices)
|
||
540 | * @arg GPIO_Remap_FSMC_NADV : FSMC_NADV Alternate Function mapping (only for High density Value line and XL-density devices)
|
||
541 | * @arg GPIO_Remap_TIM67_DAC_DMA : TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices)
|
||
542 | * @arg GPIO_Remap_TIM12 : TIM12 Alternate Function mapping (only for High density Value line devices)
|
||
543 | * @arg GPIO_Remap_MISC : Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping,
|
||
544 | * only for High density Value line devices)
|
||
545 | * @param NewState: new state of the port pin remapping.
|
||
546 | * This parameter can be: ENABLE or DISABLE.
|
||
547 | * @retval None
|
||
548 | */
|
||
549 | void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState)
|
||
550 | { |
||
551 | uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00; |
||
552 | |||
553 | /* Check the parameters */
|
||
554 | assert_param(IS_GPIO_REMAP(GPIO_Remap)); |
||
555 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
||
556 | |||
557 | if((GPIO_Remap & 0x80000000) == 0x80000000) |
||
558 | { |
||
559 | tmpreg = AFIO->MAPR2; |
||
560 | } |
||
561 | else
|
||
562 | { |
||
563 | tmpreg = AFIO->MAPR; |
||
564 | } |
||
565 | |||
566 | tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10;
|
||
567 | tmp = GPIO_Remap & LSB_MASK; |
||
568 | |||
569 | if ((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK))
|
||
570 | { |
||
571 | tmpreg &= DBGAFR_SWJCFG_MASK; |
||
572 | AFIO->MAPR &= DBGAFR_SWJCFG_MASK; |
||
573 | } |
||
574 | else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) |
||
575 | { |
||
576 | tmp1 = ((uint32_t)0x03) << tmpmask;
|
||
577 | tmpreg &= ~tmp1; |
||
578 | tmpreg |= ~DBGAFR_SWJCFG_MASK; |
||
579 | } |
||
580 | else
|
||
581 | { |
||
582 | tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15)*0x10)); |
||
583 | tmpreg |= ~DBGAFR_SWJCFG_MASK; |
||
584 | } |
||
585 | |||
586 | if (NewState != DISABLE)
|
||
587 | { |
||
588 | tmpreg |= (tmp << ((GPIO_Remap >> 0x15)*0x10)); |
||
589 | } |
||
590 | |||
591 | if((GPIO_Remap & 0x80000000) == 0x80000000) |
||
592 | { |
||
593 | AFIO->MAPR2 = tmpreg; |
||
594 | } |
||
595 | else
|
||
596 | { |
||
597 | AFIO->MAPR = tmpreg; |
||
598 | } |
||
599 | } |
||
600 | |||
601 | /**
|
||
602 | * @brief Selects the GPIO pin used as EXTI Line.
|
||
603 | * @param GPIO_PortSource: selects the GPIO port to be used as source for EXTI lines.
|
||
604 | * This parameter can be GPIO_PortSourceGPIOx where x can be (A..G).
|
||
605 | * @param GPIO_PinSource: specifies the EXTI line to be configured.
|
||
606 | * This parameter can be GPIO_PinSourcex where x can be (0..15).
|
||
607 | * @retval None
|
||
608 | */
|
||
609 | void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
|
||
610 | { |
||
611 | uint32_t tmp = 0x00;
|
||
612 | /* Check the parameters */
|
||
613 | assert_param(IS_GPIO_EXTI_PORT_SOURCE(GPIO_PortSource)); |
||
614 | assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); |
||
615 | |||
616 | tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)); |
||
617 | AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp;
|
||
618 | AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03))); |
||
619 | } |
||
620 | |||
621 | /**
|
||
622 | * @brief Selects the Ethernet media interface.
|
||
623 | * @note This function applies only to STM32 Connectivity line devices.
|
||
624 | * @param GPIO_ETH_MediaInterface: specifies the Media Interface mode.
|
||
625 | * This parameter can be one of the following values:
|
||
626 | * @arg GPIO_ETH_MediaInterface_MII: MII mode
|
||
627 | * @arg GPIO_ETH_MediaInterface_RMII: RMII mode
|
||
628 | * @retval None
|
||
629 | */
|
||
630 | void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface)
|
||
631 | { |
||
632 | assert_param(IS_GPIO_ETH_MEDIA_INTERFACE(GPIO_ETH_MediaInterface)); |
||
633 | |||
634 | /* Configure MII_RMII selection bit */
|
||
635 | *(__IO uint32_t *) MAPR_MII_RMII_SEL_BB = GPIO_ETH_MediaInterface; |
||
636 | } |
||
637 | |||
638 | /**
|
||
639 | * @}
|
||
640 | */
|
||
641 | |||
642 | /**
|
||
643 | * @}
|
||
644 | */
|
||
645 | |||
646 | /**
|
||
647 | * @}
|
||
648 | */
|
||
649 | |||
650 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|