amiro-blt / Target / Demo / ARMCM3_STM32F103_DiWheelDrive_GCC / Boot / lib / STM32F10x_StdPeriph_Driver / src / stm32f10x_pwr.c @ 69661903
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1 | 69661903 | Thomas Schöpping | /**
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2 | ******************************************************************************
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3 | * @file stm32f10x_pwr.c
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4 | * @author MCD Application Team
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5 | * @version V3.5.0
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6 | * @date 11-March-2011
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7 | * @brief This file provides all the PWR firmware functions.
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8 | ******************************************************************************
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9 | * @attention
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10 | *
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11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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17 | *
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18 | * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
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19 | ******************************************************************************
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20 | */
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21 | |||
22 | /* Includes ------------------------------------------------------------------*/
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23 | #include "stm32f10x_pwr.h" |
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24 | #include "stm32f10x_rcc.h" |
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25 | |||
26 | /** @addtogroup STM32F10x_StdPeriph_Driver
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27 | * @{
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28 | */
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29 | |||
30 | /** @defgroup PWR
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31 | * @brief PWR driver modules
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32 | * @{
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33 | */
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34 | |||
35 | /** @defgroup PWR_Private_TypesDefinitions
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36 | * @{
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37 | */
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38 | |||
39 | /**
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40 | * @}
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41 | */
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42 | |||
43 | /** @defgroup PWR_Private_Defines
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44 | * @{
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45 | */
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46 | |||
47 | /* --------- PWR registers bit address in the alias region ---------- */
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48 | #define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
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49 | |||
50 | /* --- CR Register ---*/
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51 | |||
52 | /* Alias word address of DBP bit */
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53 | #define CR_OFFSET (PWR_OFFSET + 0x00) |
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54 | #define DBP_BitNumber 0x08 |
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55 | #define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4)) |
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56 | |||
57 | /* Alias word address of PVDE bit */
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58 | #define PVDE_BitNumber 0x04 |
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59 | #define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4)) |
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60 | |||
61 | /* --- CSR Register ---*/
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62 | |||
63 | /* Alias word address of EWUP bit */
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64 | #define CSR_OFFSET (PWR_OFFSET + 0x04) |
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65 | #define EWUP_BitNumber 0x08 |
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66 | #define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4)) |
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67 | |||
68 | /* ------------------ PWR registers bit mask ------------------------ */
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69 | |||
70 | /* CR register bit mask */
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71 | #define CR_DS_MASK ((uint32_t)0xFFFFFFFC) |
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72 | #define CR_PLS_MASK ((uint32_t)0xFFFFFF1F) |
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73 | |||
74 | |||
75 | /**
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76 | * @}
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77 | */
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78 | |||
79 | /** @defgroup PWR_Private_Macros
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80 | * @{
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81 | */
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82 | |||
83 | /**
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84 | * @}
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85 | */
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86 | |||
87 | /** @defgroup PWR_Private_Variables
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88 | * @{
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89 | */
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90 | |||
91 | /**
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92 | * @}
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93 | */
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94 | |||
95 | /** @defgroup PWR_Private_FunctionPrototypes
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96 | * @{
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97 | */
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98 | |||
99 | /**
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100 | * @}
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101 | */
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102 | |||
103 | /** @defgroup PWR_Private_Functions
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104 | * @{
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105 | */
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106 | |||
107 | /**
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108 | * @brief Deinitializes the PWR peripheral registers to their default reset values.
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109 | * @param None
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110 | * @retval None
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111 | */
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112 | void PWR_DeInit(void) |
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113 | { |
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114 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); |
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115 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); |
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116 | } |
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117 | |||
118 | /**
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119 | * @brief Enables or disables access to the RTC and backup registers.
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120 | * @param NewState: new state of the access to the RTC and backup registers.
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121 | * This parameter can be: ENABLE or DISABLE.
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122 | * @retval None
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123 | */
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124 | void PWR_BackupAccessCmd(FunctionalState NewState)
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125 | { |
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126 | /* Check the parameters */
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127 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
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128 | *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState; |
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129 | } |
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130 | |||
131 | /**
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132 | * @brief Enables or disables the Power Voltage Detector(PVD).
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133 | * @param NewState: new state of the PVD.
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134 | * This parameter can be: ENABLE or DISABLE.
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135 | * @retval None
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136 | */
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137 | void PWR_PVDCmd(FunctionalState NewState)
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138 | { |
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139 | /* Check the parameters */
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140 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
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141 | *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState; |
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142 | } |
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143 | |||
144 | /**
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145 | * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
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146 | * @param PWR_PVDLevel: specifies the PVD detection level
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147 | * This parameter can be one of the following values:
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148 | * @arg PWR_PVDLevel_2V2: PVD detection level set to 2.2V
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149 | * @arg PWR_PVDLevel_2V3: PVD detection level set to 2.3V
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150 | * @arg PWR_PVDLevel_2V4: PVD detection level set to 2.4V
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151 | * @arg PWR_PVDLevel_2V5: PVD detection level set to 2.5V
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152 | * @arg PWR_PVDLevel_2V6: PVD detection level set to 2.6V
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153 | * @arg PWR_PVDLevel_2V7: PVD detection level set to 2.7V
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154 | * @arg PWR_PVDLevel_2V8: PVD detection level set to 2.8V
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155 | * @arg PWR_PVDLevel_2V9: PVD detection level set to 2.9V
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156 | * @retval None
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157 | */
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158 | void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
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159 | { |
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160 | uint32_t tmpreg = 0;
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161 | /* Check the parameters */
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162 | assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel)); |
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163 | tmpreg = PWR->CR; |
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164 | /* Clear PLS[7:5] bits */
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165 | tmpreg &= CR_PLS_MASK; |
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166 | /* Set PLS[7:5] bits according to PWR_PVDLevel value */
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167 | tmpreg |= PWR_PVDLevel; |
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168 | /* Store the new value */
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169 | PWR->CR = tmpreg; |
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170 | } |
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171 | |||
172 | /**
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173 | * @brief Enables or disables the WakeUp Pin functionality.
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174 | * @param NewState: new state of the WakeUp Pin functionality.
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175 | * This parameter can be: ENABLE or DISABLE.
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176 | * @retval None
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177 | */
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178 | void PWR_WakeUpPinCmd(FunctionalState NewState)
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179 | { |
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180 | /* Check the parameters */
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181 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
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182 | *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState; |
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183 | } |
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184 | |||
185 | /**
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186 | * @brief Enters STOP mode.
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187 | * @param PWR_Regulator: specifies the regulator state in STOP mode.
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188 | * This parameter can be one of the following values:
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189 | * @arg PWR_Regulator_ON: STOP mode with regulator ON
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190 | * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode
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191 | * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
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192 | * This parameter can be one of the following values:
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193 | * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
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194 | * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
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195 | * @retval None
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196 | */
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197 | void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
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198 | { |
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199 | uint32_t tmpreg = 0;
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200 | /* Check the parameters */
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201 | assert_param(IS_PWR_REGULATOR(PWR_Regulator)); |
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202 | assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); |
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203 | |||
204 | /* Select the regulator state in STOP mode ---------------------------------*/
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205 | tmpreg = PWR->CR; |
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206 | /* Clear PDDS and LPDS bits */
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207 | tmpreg &= CR_DS_MASK; |
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208 | /* Set LPDS bit according to PWR_Regulator value */
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209 | tmpreg |= PWR_Regulator; |
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210 | /* Store the new value */
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211 | PWR->CR = tmpreg; |
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212 | /* Set SLEEPDEEP bit of Cortex System Control Register */
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213 | SCB->SCR |= SCB_SCR_SLEEPDEEP; |
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214 | |||
215 | /* Select STOP mode entry --------------------------------------------------*/
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216 | if(PWR_STOPEntry == PWR_STOPEntry_WFI)
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217 | { |
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218 | /* Request Wait For Interrupt */
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219 | __WFI(); |
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220 | } |
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221 | else
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222 | { |
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223 | /* Request Wait For Event */
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224 | __WFE(); |
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225 | } |
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226 | |||
227 | /* Reset SLEEPDEEP bit of Cortex System Control Register */
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228 | SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP); |
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229 | } |
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230 | |||
231 | /**
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232 | * @brief Enters STANDBY mode.
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233 | * @param None
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234 | * @retval None
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235 | */
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236 | void PWR_EnterSTANDBYMode(void) |
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237 | { |
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238 | /* Clear Wake-up flag */
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239 | PWR->CR |= PWR_CR_CWUF; |
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240 | /* Select STANDBY mode */
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241 | PWR->CR |= PWR_CR_PDDS; |
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242 | /* Set SLEEPDEEP bit of Cortex System Control Register */
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243 | SCB->SCR |= SCB_SCR_SLEEPDEEP; |
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244 | /* This option is used to ensure that store operations are completed */
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245 | #if defined ( __CC_ARM )
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246 | __force_stores(); |
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247 | #endif
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248 | /* Request Wait For Interrupt */
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249 | __WFI(); |
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250 | } |
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251 | |||
252 | /**
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253 | * @brief Checks whether the specified PWR flag is set or not.
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254 | * @param PWR_FLAG: specifies the flag to check.
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255 | * This parameter can be one of the following values:
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256 | * @arg PWR_FLAG_WU: Wake Up flag
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257 | * @arg PWR_FLAG_SB: StandBy flag
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258 | * @arg PWR_FLAG_PVDO: PVD Output
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259 | * @retval The new state of PWR_FLAG (SET or RESET).
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260 | */
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261 | FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) |
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262 | { |
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263 | FlagStatus bitstatus = RESET; |
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264 | /* Check the parameters */
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265 | assert_param(IS_PWR_GET_FLAG(PWR_FLAG)); |
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266 | |||
267 | if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
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268 | { |
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269 | bitstatus = SET; |
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270 | } |
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271 | else
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272 | { |
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273 | bitstatus = RESET; |
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274 | } |
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275 | /* Return the flag status */
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276 | return bitstatus;
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277 | } |
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278 | |||
279 | /**
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280 | * @brief Clears the PWR's pending flags.
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281 | * @param PWR_FLAG: specifies the flag to clear.
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282 | * This parameter can be one of the following values:
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283 | * @arg PWR_FLAG_WU: Wake Up flag
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284 | * @arg PWR_FLAG_SB: StandBy flag
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285 | * @retval None
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286 | */
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287 | void PWR_ClearFlag(uint32_t PWR_FLAG)
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288 | { |
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289 | /* Check the parameters */
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290 | assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG)); |
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291 | |||
292 | PWR->CR |= PWR_FLAG << 2;
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293 | } |
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294 | |||
295 | /**
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296 | * @}
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297 | */
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298 | |||
299 | /**
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300 | * @}
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301 | */
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302 | |||
303 | /**
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304 | * @}
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305 | */
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306 | |||
307 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
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