amiro-blt / Target / Demo / ARMCM3_STM32F103_LightRing_GCC / Boot / lib / STM32F10x_StdPeriph_Driver / src / stm32f10x_spi.c @ 69661903
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1 | 69661903 | Thomas Schöpping | /**
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2 | ******************************************************************************
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3 | * @file stm32f10x_spi.c
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4 | * @author MCD Application Team
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5 | * @version V3.5.0
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6 | * @date 11-March-2011
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7 | * @brief This file provides all the SPI firmware functions.
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8 | ******************************************************************************
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9 | * @attention
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10 | *
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11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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17 | *
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18 | * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
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19 | ******************************************************************************
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20 | */
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21 | |||
22 | /* Includes ------------------------------------------------------------------*/
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23 | #include "stm32f10x_spi.h" |
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24 | #include "stm32f10x_rcc.h" |
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25 | |||
26 | /** @addtogroup STM32F10x_StdPeriph_Driver
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27 | * @{
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28 | */
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29 | |||
30 | /** @defgroup SPI
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31 | * @brief SPI driver modules
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32 | * @{
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33 | */
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34 | |||
35 | /** @defgroup SPI_Private_TypesDefinitions
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36 | * @{
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37 | */
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38 | |||
39 | /**
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40 | * @}
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41 | */
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42 | |||
43 | |||
44 | /** @defgroup SPI_Private_Defines
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45 | * @{
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46 | */
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47 | |||
48 | /* SPI SPE mask */
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49 | #define CR1_SPE_Set ((uint16_t)0x0040) |
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50 | #define CR1_SPE_Reset ((uint16_t)0xFFBF) |
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51 | |||
52 | /* I2S I2SE mask */
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53 | #define I2SCFGR_I2SE_Set ((uint16_t)0x0400) |
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54 | #define I2SCFGR_I2SE_Reset ((uint16_t)0xFBFF) |
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55 | |||
56 | /* SPI CRCNext mask */
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57 | #define CR1_CRCNext_Set ((uint16_t)0x1000) |
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58 | |||
59 | /* SPI CRCEN mask */
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60 | #define CR1_CRCEN_Set ((uint16_t)0x2000) |
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61 | #define CR1_CRCEN_Reset ((uint16_t)0xDFFF) |
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62 | |||
63 | /* SPI SSOE mask */
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64 | #define CR2_SSOE_Set ((uint16_t)0x0004) |
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65 | #define CR2_SSOE_Reset ((uint16_t)0xFFFB) |
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66 | |||
67 | /* SPI registers Masks */
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68 | #define CR1_CLEAR_Mask ((uint16_t)0x3040) |
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69 | #define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040) |
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70 | |||
71 | /* SPI or I2S mode selection masks */
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72 | #define SPI_Mode_Select ((uint16_t)0xF7FF) |
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73 | #define I2S_Mode_Select ((uint16_t)0x0800) |
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74 | |||
75 | /* I2S clock source selection masks */
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76 | #define I2S2_CLOCK_SRC ((uint32_t)(0x00020000)) |
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77 | #define I2S3_CLOCK_SRC ((uint32_t)(0x00040000)) |
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78 | #define I2S_MUL_MASK ((uint32_t)(0x0000F000)) |
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79 | #define I2S_DIV_MASK ((uint32_t)(0x000000F0)) |
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80 | |||
81 | /**
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82 | * @}
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83 | */
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84 | |||
85 | /** @defgroup SPI_Private_Macros
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86 | * @{
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87 | */
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88 | |||
89 | /**
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90 | * @}
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91 | */
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92 | |||
93 | /** @defgroup SPI_Private_Variables
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94 | * @{
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95 | */
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96 | |||
97 | /**
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98 | * @}
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99 | */
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100 | |||
101 | /** @defgroup SPI_Private_FunctionPrototypes
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102 | * @{
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103 | */
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104 | |||
105 | /**
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106 | * @}
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107 | */
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108 | |||
109 | /** @defgroup SPI_Private_Functions
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110 | * @{
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111 | */
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112 | |||
113 | /**
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114 | * @brief Deinitializes the SPIx peripheral registers to their default
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115 | * reset values (Affects also the I2Ss).
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116 | * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
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117 | * @retval None
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118 | */
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119 | void SPI_I2S_DeInit(SPI_TypeDef* SPIx)
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120 | { |
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121 | /* Check the parameters */
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122 | assert_param(IS_SPI_ALL_PERIPH(SPIx)); |
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123 | |||
124 | if (SPIx == SPI1)
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125 | { |
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126 | /* Enable SPI1 reset state */
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127 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); |
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128 | /* Release SPI1 from reset state */
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129 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); |
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130 | } |
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131 | else if (SPIx == SPI2) |
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132 | { |
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133 | /* Enable SPI2 reset state */
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134 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE); |
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135 | /* Release SPI2 from reset state */
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136 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE); |
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137 | } |
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138 | else
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139 | { |
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140 | if (SPIx == SPI3)
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141 | { |
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142 | /* Enable SPI3 reset state */
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143 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE); |
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144 | /* Release SPI3 from reset state */
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145 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE); |
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146 | } |
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147 | } |
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148 | } |
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149 | |||
150 | /**
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151 | * @brief Initializes the SPIx peripheral according to the specified
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152 | * parameters in the SPI_InitStruct.
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153 | * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
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154 | * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that
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155 | * contains the configuration information for the specified SPI peripheral.
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156 | * @retval None
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157 | */
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158 | void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
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159 | { |
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160 | uint16_t tmpreg = 0;
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161 | |||
162 | /* check the parameters */
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163 | assert_param(IS_SPI_ALL_PERIPH(SPIx)); |
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164 | |||
165 | /* Check the SPI parameters */
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166 | assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction)); |
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167 | assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode)); |
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168 | assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize)); |
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169 | assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL)); |
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170 | assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA)); |
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171 | assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS)); |
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172 | assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler)); |
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173 | assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit)); |
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174 | assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial)); |
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175 | |||
176 | /*---------------------------- SPIx CR1 Configuration ------------------------*/
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177 | /* Get the SPIx CR1 value */
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178 | tmpreg = SPIx->CR1; |
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179 | /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
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180 | tmpreg &= CR1_CLEAR_Mask; |
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181 | /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
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182 | master/salve mode, CPOL and CPHA */
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183 | /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
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184 | /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */
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185 | /* Set LSBFirst bit according to SPI_FirstBit value */
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186 | /* Set BR bits according to SPI_BaudRatePrescaler value */
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187 | /* Set CPOL bit according to SPI_CPOL value */
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188 | /* Set CPHA bit according to SPI_CPHA value */
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189 | tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | |
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190 | SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | |
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191 | SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | |
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192 | SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); |
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193 | /* Write to SPIx CR1 */
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194 | SPIx->CR1 = tmpreg; |
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195 | |||
196 | /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
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197 | SPIx->I2SCFGR &= SPI_Mode_Select; |
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198 | |||
199 | /*---------------------------- SPIx CRCPOLY Configuration --------------------*/
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200 | /* Write to SPIx CRCPOLY */
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201 | SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial; |
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202 | } |
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203 | |||
204 | /**
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205 | * @brief Initializes the SPIx peripheral according to the specified
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206 | * parameters in the I2S_InitStruct.
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207 | * @param SPIx: where x can be 2 or 3 to select the SPI peripheral
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208 | * (configured in I2S mode).
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209 | * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that
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210 | * contains the configuration information for the specified SPI peripheral
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211 | * configured in I2S mode.
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212 | * @note
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213 | * The function calculates the optimal prescaler needed to obtain the most
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214 | * accurate audio frequency (depending on the I2S clock source, the PLL values
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215 | * and the product configuration). But in case the prescaler value is greater
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216 | * than 511, the default value (0x02) will be configured instead. *
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217 | * @retval None
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218 | */
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219 | void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)
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220 | { |
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221 | uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1; |
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222 | uint32_t tmp = 0;
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223 | RCC_ClocksTypeDef RCC_Clocks; |
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224 | uint32_t sourceclock = 0;
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225 | |||
226 | /* Check the I2S parameters */
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227 | assert_param(IS_SPI_23_PERIPH(SPIx)); |
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228 | assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode)); |
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229 | assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard)); |
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230 | assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat)); |
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231 | assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput)); |
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232 | assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq)); |
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233 | assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL)); |
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234 | |||
235 | /*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
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236 | /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
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237 | SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask; |
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238 | SPIx->I2SPR = 0x0002;
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239 | |||
240 | /* Get the I2SCFGR register value */
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241 | tmpreg = SPIx->I2SCFGR; |
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242 | |||
243 | /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
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244 | if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)
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245 | { |
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246 | i2sodd = (uint16_t)0;
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247 | i2sdiv = (uint16_t)2;
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248 | } |
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249 | /* If the requested audio frequency is not the default, compute the prescaler */
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250 | else
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251 | { |
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252 | /* Check the frame length (For the Prescaler computing) */
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253 | if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)
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254 | { |
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255 | /* Packet length is 16 bits */
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256 | packetlength = 1;
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257 | } |
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258 | else
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259 | { |
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260 | /* Packet length is 32 bits */
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261 | packetlength = 2;
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262 | } |
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263 | |||
264 | /* Get the I2S clock source mask depending on the peripheral number */
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265 | if(((uint32_t)SPIx) == SPI2_BASE)
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266 | { |
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267 | /* The mask is relative to I2S2 */
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268 | tmp = I2S2_CLOCK_SRC; |
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269 | } |
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270 | else
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271 | { |
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272 | /* The mask is relative to I2S3 */
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273 | tmp = I2S3_CLOCK_SRC; |
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274 | } |
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275 | |||
276 | /* Check the I2S clock source configuration depending on the Device:
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277 | Only Connectivity line devices have the PLL3 VCO clock */
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278 | #ifdef STM32F10X_CL
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279 | if((RCC->CFGR2 & tmp) != 0) |
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280 | { |
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281 | /* Get the configuration bits of RCC PLL3 multiplier */
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282 | tmp = (uint32_t)((RCC->CFGR2 & I2S_MUL_MASK) >> 12);
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283 | |||
284 | /* Get the value of the PLL3 multiplier */
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285 | if((tmp > 5) && (tmp < 15)) |
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286 | { |
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287 | /* Multiplier is between 8 and 14 (value 15 is forbidden) */
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288 | tmp += 2;
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289 | } |
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290 | else
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291 | { |
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292 | if (tmp == 15) |
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293 | { |
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294 | /* Multiplier is 20 */
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295 | tmp = 20;
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296 | } |
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297 | } |
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298 | /* Get the PREDIV2 value */
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299 | sourceclock = (uint32_t)(((RCC->CFGR2 & I2S_DIV_MASK) >> 4) + 1); |
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300 | |||
301 | /* Calculate the Source Clock frequency based on PLL3 and PREDIV2 values */
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302 | sourceclock = (uint32_t) ((HSE_Value / sourceclock) * tmp * 2);
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303 | } |
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304 | else
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305 | { |
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306 | /* I2S Clock source is System clock: Get System Clock frequency */
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307 | RCC_GetClocksFreq(&RCC_Clocks); |
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308 | |||
309 | /* Get the source clock value: based on System Clock value */
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310 | sourceclock = RCC_Clocks.SYSCLK_Frequency; |
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311 | } |
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312 | #else /* STM32F10X_HD */ |
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313 | /* I2S Clock source is System clock: Get System Clock frequency */
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314 | RCC_GetClocksFreq(&RCC_Clocks); |
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315 | |||
316 | /* Get the source clock value: based on System Clock value */
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317 | sourceclock = RCC_Clocks.SYSCLK_Frequency; |
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318 | #endif /* STM32F10X_CL */ |
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319 | |||
320 | /* Compute the Real divider depending on the MCLK output state with a floating point */
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321 | if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)
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322 | { |
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323 | /* MCLK output is enabled */
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324 | tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5); |
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325 | } |
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326 | else
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327 | { |
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328 | /* MCLK output is disabled */
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329 | tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5); |
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330 | } |
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331 | |||
332 | /* Remove the floating point */
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333 | tmp = tmp / 10;
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334 | |||
335 | /* Check the parity of the divider */
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336 | i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
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337 | |||
338 | /* Compute the i2sdiv prescaler */
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339 | i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
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340 | |||
341 | /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
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342 | i2sodd = (uint16_t) (i2sodd << 8);
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343 | } |
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344 | |||
345 | /* Test if the divider is 1 or 0 or greater than 0xFF */
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346 | if ((i2sdiv < 2) || (i2sdiv > 0xFF)) |
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347 | { |
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348 | /* Set the default values */
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349 | i2sdiv = 2;
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350 | i2sodd = 0;
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351 | } |
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352 | |||
353 | /* Write to SPIx I2SPR register the computed value */
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354 | SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput)); |
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355 | |||
356 | /* Configure the I2S with the SPI_InitStruct values */
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357 | tmpreg |= (uint16_t)(I2S_Mode_Select | (uint16_t)(I2S_InitStruct->I2S_Mode | \ |
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358 | (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \ |
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359 | (uint16_t)I2S_InitStruct->I2S_CPOL)))); |
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360 | |||
361 | /* Write to SPIx I2SCFGR */
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362 | SPIx->I2SCFGR = tmpreg; |
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363 | } |
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364 | |||
365 | /**
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366 | * @brief Fills each SPI_InitStruct member with its default value.
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367 | * @param SPI_InitStruct : pointer to a SPI_InitTypeDef structure which will be initialized.
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368 | * @retval None
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369 | */
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370 | void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)
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371 | { |
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372 | /*--------------- Reset SPI init structure parameters values -----------------*/
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373 | /* Initialize the SPI_Direction member */
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374 | SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; |
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375 | /* initialize the SPI_Mode member */
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376 | SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; |
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377 | /* initialize the SPI_DataSize member */
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378 | SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; |
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379 | /* Initialize the SPI_CPOL member */
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380 | SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; |
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381 | /* Initialize the SPI_CPHA member */
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382 | SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; |
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383 | /* Initialize the SPI_NSS member */
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384 | SPI_InitStruct->SPI_NSS = SPI_NSS_Hard; |
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385 | /* Initialize the SPI_BaudRatePrescaler member */
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386 | SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; |
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387 | /* Initialize the SPI_FirstBit member */
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388 | SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; |
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389 | /* Initialize the SPI_CRCPolynomial member */
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390 | SPI_InitStruct->SPI_CRCPolynomial = 7;
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391 | } |
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392 | |||
393 | /**
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394 | * @brief Fills each I2S_InitStruct member with its default value.
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395 | * @param I2S_InitStruct : pointer to a I2S_InitTypeDef structure which will be initialized.
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396 | * @retval None
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397 | */
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398 | void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)
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399 | { |
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400 | /*--------------- Reset I2S init structure parameters values -----------------*/
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401 | /* Initialize the I2S_Mode member */
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402 | I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx; |
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403 | |||
404 | /* Initialize the I2S_Standard member */
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405 | I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips; |
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406 | |||
407 | /* Initialize the I2S_DataFormat member */
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408 | I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b; |
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409 | |||
410 | /* Initialize the I2S_MCLKOutput member */
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411 | I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable; |
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412 | |||
413 | /* Initialize the I2S_AudioFreq member */
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414 | I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default; |
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415 | |||
416 | /* Initialize the I2S_CPOL member */
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417 | I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low; |
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418 | } |
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419 | |||
420 | /**
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421 | * @brief Enables or disables the specified SPI peripheral.
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422 | * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
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423 | * @param NewState: new state of the SPIx peripheral.
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424 | * This parameter can be: ENABLE or DISABLE.
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425 | * @retval None
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426 | */
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427 | void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
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428 | { |
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429 | /* Check the parameters */
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430 | assert_param(IS_SPI_ALL_PERIPH(SPIx)); |
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431 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
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432 | if (NewState != DISABLE)
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433 | { |
||
434 | /* Enable the selected SPI peripheral */
|
||
435 | SPIx->CR1 |= CR1_SPE_Set; |
||
436 | } |
||
437 | else
|
||
438 | { |
||
439 | /* Disable the selected SPI peripheral */
|
||
440 | SPIx->CR1 &= CR1_SPE_Reset; |
||
441 | } |
||
442 | } |
||
443 | |||
444 | /**
|
||
445 | * @brief Enables or disables the specified SPI peripheral (in I2S mode).
|
||
446 | * @param SPIx: where x can be 2 or 3 to select the SPI peripheral.
|
||
447 | * @param NewState: new state of the SPIx peripheral.
|
||
448 | * This parameter can be: ENABLE or DISABLE.
|
||
449 | * @retval None
|
||
450 | */
|
||
451 | void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
|
||
452 | { |
||
453 | /* Check the parameters */
|
||
454 | assert_param(IS_SPI_23_PERIPH(SPIx)); |
||
455 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
||
456 | if (NewState != DISABLE)
|
||
457 | { |
||
458 | /* Enable the selected SPI peripheral (in I2S mode) */
|
||
459 | SPIx->I2SCFGR |= I2SCFGR_I2SE_Set; |
||
460 | } |
||
461 | else
|
||
462 | { |
||
463 | /* Disable the selected SPI peripheral (in I2S mode) */
|
||
464 | SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset; |
||
465 | } |
||
466 | } |
||
467 | |||
468 | /**
|
||
469 | * @brief Enables or disables the specified SPI/I2S interrupts.
|
||
470 | * @param SPIx: where x can be
|
||
471 | * - 1, 2 or 3 in SPI mode
|
||
472 | * - 2 or 3 in I2S mode
|
||
473 | * @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to be enabled or disabled.
|
||
474 | * This parameter can be one of the following values:
|
||
475 | * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask
|
||
476 | * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask
|
||
477 | * @arg SPI_I2S_IT_ERR: Error interrupt mask
|
||
478 | * @param NewState: new state of the specified SPI/I2S interrupt.
|
||
479 | * This parameter can be: ENABLE or DISABLE.
|
||
480 | * @retval None
|
||
481 | */
|
||
482 | void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
|
||
483 | { |
||
484 | uint16_t itpos = 0, itmask = 0 ; |
||
485 | /* Check the parameters */
|
||
486 | assert_param(IS_SPI_ALL_PERIPH(SPIx)); |
||
487 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
||
488 | assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT)); |
||
489 | |||
490 | /* Get the SPI/I2S IT index */
|
||
491 | itpos = SPI_I2S_IT >> 4;
|
||
492 | |||
493 | /* Set the IT mask */
|
||
494 | itmask = (uint16_t)1 << (uint16_t)itpos;
|
||
495 | |||
496 | if (NewState != DISABLE)
|
||
497 | { |
||
498 | /* Enable the selected SPI/I2S interrupt */
|
||
499 | SPIx->CR2 |= itmask; |
||
500 | } |
||
501 | else
|
||
502 | { |
||
503 | /* Disable the selected SPI/I2S interrupt */
|
||
504 | SPIx->CR2 &= (uint16_t)~itmask; |
||
505 | } |
||
506 | } |
||
507 | |||
508 | /**
|
||
509 | * @brief Enables or disables the SPIx/I2Sx DMA interface.
|
||
510 | * @param SPIx: where x can be
|
||
511 | * - 1, 2 or 3 in SPI mode
|
||
512 | * - 2 or 3 in I2S mode
|
||
513 | * @param SPI_I2S_DMAReq: specifies the SPI/I2S DMA transfer request to be enabled or disabled.
|
||
514 | * This parameter can be any combination of the following values:
|
||
515 | * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request
|
||
516 | * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request
|
||
517 | * @param NewState: new state of the selected SPI/I2S DMA transfer request.
|
||
518 | * This parameter can be: ENABLE or DISABLE.
|
||
519 | * @retval None
|
||
520 | */
|
||
521 | void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
|
||
522 | { |
||
523 | /* Check the parameters */
|
||
524 | assert_param(IS_SPI_ALL_PERIPH(SPIx)); |
||
525 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
||
526 | assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq)); |
||
527 | if (NewState != DISABLE)
|
||
528 | { |
||
529 | /* Enable the selected SPI/I2S DMA requests */
|
||
530 | SPIx->CR2 |= SPI_I2S_DMAReq; |
||
531 | } |
||
532 | else
|
||
533 | { |
||
534 | /* Disable the selected SPI/I2S DMA requests */
|
||
535 | SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq; |
||
536 | } |
||
537 | } |
||
538 | |||
539 | /**
|
||
540 | * @brief Transmits a Data through the SPIx/I2Sx peripheral.
|
||
541 | * @param SPIx: where x can be
|
||
542 | * - 1, 2 or 3 in SPI mode
|
||
543 | * - 2 or 3 in I2S mode
|
||
544 | * @param Data : Data to be transmitted.
|
||
545 | * @retval None
|
||
546 | */
|
||
547 | void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data)
|
||
548 | { |
||
549 | /* Check the parameters */
|
||
550 | assert_param(IS_SPI_ALL_PERIPH(SPIx)); |
||
551 | |||
552 | /* Write in the DR register the data to be sent */
|
||
553 | SPIx->DR = Data; |
||
554 | } |
||
555 | |||
556 | /**
|
||
557 | * @brief Returns the most recent received data by the SPIx/I2Sx peripheral.
|
||
558 | * @param SPIx: where x can be
|
||
559 | * - 1, 2 or 3 in SPI mode
|
||
560 | * - 2 or 3 in I2S mode
|
||
561 | * @retval The value of the received data.
|
||
562 | */
|
||
563 | uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx) |
||
564 | { |
||
565 | /* Check the parameters */
|
||
566 | assert_param(IS_SPI_ALL_PERIPH(SPIx)); |
||
567 | |||
568 | /* Return the data in the DR register */
|
||
569 | return SPIx->DR;
|
||
570 | } |
||
571 | |||
572 | /**
|
||
573 | * @brief Configures internally by software the NSS pin for the selected SPI.
|
||
574 | * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
|
||
575 | * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state.
|
||
576 | * This parameter can be one of the following values:
|
||
577 | * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally
|
||
578 | * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally
|
||
579 | * @retval None
|
||
580 | */
|
||
581 | void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)
|
||
582 | { |
||
583 | /* Check the parameters */
|
||
584 | assert_param(IS_SPI_ALL_PERIPH(SPIx)); |
||
585 | assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft)); |
||
586 | if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
|
||
587 | { |
||
588 | /* Set NSS pin internally by software */
|
||
589 | SPIx->CR1 |= SPI_NSSInternalSoft_Set; |
||
590 | } |
||
591 | else
|
||
592 | { |
||
593 | /* Reset NSS pin internally by software */
|
||
594 | SPIx->CR1 &= SPI_NSSInternalSoft_Reset; |
||
595 | } |
||
596 | } |
||
597 | |||
598 | /**
|
||
599 | * @brief Enables or disables the SS output for the selected SPI.
|
||
600 | * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
|
||
601 | * @param NewState: new state of the SPIx SS output.
|
||
602 | * This parameter can be: ENABLE or DISABLE.
|
||
603 | * @retval None
|
||
604 | */
|
||
605 | void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
|
||
606 | { |
||
607 | /* Check the parameters */
|
||
608 | assert_param(IS_SPI_ALL_PERIPH(SPIx)); |
||
609 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
||
610 | if (NewState != DISABLE)
|
||
611 | { |
||
612 | /* Enable the selected SPI SS output */
|
||
613 | SPIx->CR2 |= CR2_SSOE_Set; |
||
614 | } |
||
615 | else
|
||
616 | { |
||
617 | /* Disable the selected SPI SS output */
|
||
618 | SPIx->CR2 &= CR2_SSOE_Reset; |
||
619 | } |
||
620 | } |
||
621 | |||
622 | /**
|
||
623 | * @brief Configures the data size for the selected SPI.
|
||
624 | * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
|
||
625 | * @param SPI_DataSize: specifies the SPI data size.
|
||
626 | * This parameter can be one of the following values:
|
||
627 | * @arg SPI_DataSize_16b: Set data frame format to 16bit
|
||
628 | * @arg SPI_DataSize_8b: Set data frame format to 8bit
|
||
629 | * @retval None
|
||
630 | */
|
||
631 | void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)
|
||
632 | { |
||
633 | /* Check the parameters */
|
||
634 | assert_param(IS_SPI_ALL_PERIPH(SPIx)); |
||
635 | assert_param(IS_SPI_DATASIZE(SPI_DataSize)); |
||
636 | /* Clear DFF bit */
|
||
637 | SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b; |
||
638 | /* Set new DFF bit value */
|
||
639 | SPIx->CR1 |= SPI_DataSize; |
||
640 | } |
||
641 | |||
642 | /**
|
||
643 | * @brief Transmit the SPIx CRC value.
|
||
644 | * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
|
||
645 | * @retval None
|
||
646 | */
|
||
647 | void SPI_TransmitCRC(SPI_TypeDef* SPIx)
|
||
648 | { |
||
649 | /* Check the parameters */
|
||
650 | assert_param(IS_SPI_ALL_PERIPH(SPIx)); |
||
651 | |||
652 | /* Enable the selected SPI CRC transmission */
|
||
653 | SPIx->CR1 |= CR1_CRCNext_Set; |
||
654 | } |
||
655 | |||
656 | /**
|
||
657 | * @brief Enables or disables the CRC value calculation of the transferred bytes.
|
||
658 | * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
|
||
659 | * @param NewState: new state of the SPIx CRC value calculation.
|
||
660 | * This parameter can be: ENABLE or DISABLE.
|
||
661 | * @retval None
|
||
662 | */
|
||
663 | void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)
|
||
664 | { |
||
665 | /* Check the parameters */
|
||
666 | assert_param(IS_SPI_ALL_PERIPH(SPIx)); |
||
667 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
||
668 | if (NewState != DISABLE)
|
||
669 | { |
||
670 | /* Enable the selected SPI CRC calculation */
|
||
671 | SPIx->CR1 |= CR1_CRCEN_Set; |
||
672 | } |
||
673 | else
|
||
674 | { |
||
675 | /* Disable the selected SPI CRC calculation */
|
||
676 | SPIx->CR1 &= CR1_CRCEN_Reset; |
||
677 | } |
||
678 | } |
||
679 | |||
680 | /**
|
||
681 | * @brief Returns the transmit or the receive CRC register value for the specified SPI.
|
||
682 | * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
|
||
683 | * @param SPI_CRC: specifies the CRC register to be read.
|
||
684 | * This parameter can be one of the following values:
|
||
685 | * @arg SPI_CRC_Tx: Selects Tx CRC register
|
||
686 | * @arg SPI_CRC_Rx: Selects Rx CRC register
|
||
687 | * @retval The selected CRC register value..
|
||
688 | */
|
||
689 | uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC) |
||
690 | { |
||
691 | uint16_t crcreg = 0;
|
||
692 | /* Check the parameters */
|
||
693 | assert_param(IS_SPI_ALL_PERIPH(SPIx)); |
||
694 | assert_param(IS_SPI_CRC(SPI_CRC)); |
||
695 | if (SPI_CRC != SPI_CRC_Rx)
|
||
696 | { |
||
697 | /* Get the Tx CRC register */
|
||
698 | crcreg = SPIx->TXCRCR; |
||
699 | } |
||
700 | else
|
||
701 | { |
||
702 | /* Get the Rx CRC register */
|
||
703 | crcreg = SPIx->RXCRCR; |
||
704 | } |
||
705 | /* Return the selected CRC register */
|
||
706 | return crcreg;
|
||
707 | } |
||
708 | |||
709 | /**
|
||
710 | * @brief Returns the CRC Polynomial register value for the specified SPI.
|
||
711 | * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
|
||
712 | * @retval The CRC Polynomial register value.
|
||
713 | */
|
||
714 | uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx) |
||
715 | { |
||
716 | /* Check the parameters */
|
||
717 | assert_param(IS_SPI_ALL_PERIPH(SPIx)); |
||
718 | |||
719 | /* Return the CRC polynomial register */
|
||
720 | return SPIx->CRCPR;
|
||
721 | } |
||
722 | |||
723 | /**
|
||
724 | * @brief Selects the data transfer direction in bi-directional mode for the specified SPI.
|
||
725 | * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
|
||
726 | * @param SPI_Direction: specifies the data transfer direction in bi-directional mode.
|
||
727 | * This parameter can be one of the following values:
|
||
728 | * @arg SPI_Direction_Tx: Selects Tx transmission direction
|
||
729 | * @arg SPI_Direction_Rx: Selects Rx receive direction
|
||
730 | * @retval None
|
||
731 | */
|
||
732 | void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)
|
||
733 | { |
||
734 | /* Check the parameters */
|
||
735 | assert_param(IS_SPI_ALL_PERIPH(SPIx)); |
||
736 | assert_param(IS_SPI_DIRECTION(SPI_Direction)); |
||
737 | if (SPI_Direction == SPI_Direction_Tx)
|
||
738 | { |
||
739 | /* Set the Tx only mode */
|
||
740 | SPIx->CR1 |= SPI_Direction_Tx; |
||
741 | } |
||
742 | else
|
||
743 | { |
||
744 | /* Set the Rx only mode */
|
||
745 | SPIx->CR1 &= SPI_Direction_Rx; |
||
746 | } |
||
747 | } |
||
748 | |||
749 | /**
|
||
750 | * @brief Checks whether the specified SPI/I2S flag is set or not.
|
||
751 | * @param SPIx: where x can be
|
||
752 | * - 1, 2 or 3 in SPI mode
|
||
753 | * - 2 or 3 in I2S mode
|
||
754 | * @param SPI_I2S_FLAG: specifies the SPI/I2S flag to check.
|
||
755 | * This parameter can be one of the following values:
|
||
756 | * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag.
|
||
757 | * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.
|
||
758 | * @arg SPI_I2S_FLAG_BSY: Busy flag.
|
||
759 | * @arg SPI_I2S_FLAG_OVR: Overrun flag.
|
||
760 | * @arg SPI_FLAG_MODF: Mode Fault flag.
|
||
761 | * @arg SPI_FLAG_CRCERR: CRC Error flag.
|
||
762 | * @arg I2S_FLAG_UDR: Underrun Error flag.
|
||
763 | * @arg I2S_FLAG_CHSIDE: Channel Side flag.
|
||
764 | * @retval The new state of SPI_I2S_FLAG (SET or RESET).
|
||
765 | */
|
||
766 | FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) |
||
767 | { |
||
768 | FlagStatus bitstatus = RESET; |
||
769 | /* Check the parameters */
|
||
770 | assert_param(IS_SPI_ALL_PERIPH(SPIx)); |
||
771 | assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG)); |
||
772 | /* Check the status of the specified SPI/I2S flag */
|
||
773 | if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET)
|
||
774 | { |
||
775 | /* SPI_I2S_FLAG is set */
|
||
776 | bitstatus = SET; |
||
777 | } |
||
778 | else
|
||
779 | { |
||
780 | /* SPI_I2S_FLAG is reset */
|
||
781 | bitstatus = RESET; |
||
782 | } |
||
783 | /* Return the SPI_I2S_FLAG status */
|
||
784 | return bitstatus;
|
||
785 | } |
||
786 | |||
787 | /**
|
||
788 | * @brief Clears the SPIx CRC Error (CRCERR) flag.
|
||
789 | * @param SPIx: where x can be
|
||
790 | * - 1, 2 or 3 in SPI mode
|
||
791 | * @param SPI_I2S_FLAG: specifies the SPI flag to clear.
|
||
792 | * This function clears only CRCERR flag.
|
||
793 | * @note
|
||
794 | * - OVR (OverRun error) flag is cleared by software sequence: a read
|
||
795 | * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read
|
||
796 | * operation to SPI_SR register (SPI_I2S_GetFlagStatus()).
|
||
797 | * - UDR (UnderRun error) flag is cleared by a read operation to
|
||
798 | * SPI_SR register (SPI_I2S_GetFlagStatus()).
|
||
799 | * - MODF (Mode Fault) flag is cleared by software sequence: a read/write
|
||
800 | * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a
|
||
801 | * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
|
||
802 | * @retval None
|
||
803 | */
|
||
804 | void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
|
||
805 | { |
||
806 | /* Check the parameters */
|
||
807 | assert_param(IS_SPI_ALL_PERIPH(SPIx)); |
||
808 | assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG)); |
||
809 | |||
810 | /* Clear the selected SPI CRC Error (CRCERR) flag */
|
||
811 | SPIx->SR = (uint16_t)~SPI_I2S_FLAG; |
||
812 | } |
||
813 | |||
814 | /**
|
||
815 | * @brief Checks whether the specified SPI/I2S interrupt has occurred or not.
|
||
816 | * @param SPIx: where x can be
|
||
817 | * - 1, 2 or 3 in SPI mode
|
||
818 | * - 2 or 3 in I2S mode
|
||
819 | * @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to check.
|
||
820 | * This parameter can be one of the following values:
|
||
821 | * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt.
|
||
822 | * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.
|
||
823 | * @arg SPI_I2S_IT_OVR: Overrun interrupt.
|
||
824 | * @arg SPI_IT_MODF: Mode Fault interrupt.
|
||
825 | * @arg SPI_IT_CRCERR: CRC Error interrupt.
|
||
826 | * @arg I2S_IT_UDR: Underrun Error interrupt.
|
||
827 | * @retval The new state of SPI_I2S_IT (SET or RESET).
|
||
828 | */
|
||
829 | ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) |
||
830 | { |
||
831 | ITStatus bitstatus = RESET; |
||
832 | uint16_t itpos = 0, itmask = 0, enablestatus = 0; |
||
833 | |||
834 | /* Check the parameters */
|
||
835 | assert_param(IS_SPI_ALL_PERIPH(SPIx)); |
||
836 | assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT)); |
||
837 | |||
838 | /* Get the SPI/I2S IT index */
|
||
839 | itpos = 0x01 << (SPI_I2S_IT & 0x0F); |
||
840 | |||
841 | /* Get the SPI/I2S IT mask */
|
||
842 | itmask = SPI_I2S_IT >> 4;
|
||
843 | |||
844 | /* Set the IT mask */
|
||
845 | itmask = 0x01 << itmask;
|
||
846 | |||
847 | /* Get the SPI_I2S_IT enable bit status */
|
||
848 | enablestatus = (SPIx->CR2 & itmask) ; |
||
849 | |||
850 | /* Check the status of the specified SPI/I2S interrupt */
|
||
851 | if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus)
|
||
852 | { |
||
853 | /* SPI_I2S_IT is set */
|
||
854 | bitstatus = SET; |
||
855 | } |
||
856 | else
|
||
857 | { |
||
858 | /* SPI_I2S_IT is reset */
|
||
859 | bitstatus = RESET; |
||
860 | } |
||
861 | /* Return the SPI_I2S_IT status */
|
||
862 | return bitstatus;
|
||
863 | } |
||
864 | |||
865 | /**
|
||
866 | * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
|
||
867 | * @param SPIx: where x can be
|
||
868 | * - 1, 2 or 3 in SPI mode
|
||
869 | * @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear.
|
||
870 | * This function clears only CRCERR interrupt pending bit.
|
||
871 | * @note
|
||
872 | * - OVR (OverRun Error) interrupt pending bit is cleared by software
|
||
873 | * sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData())
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874 | * followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()).
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875 | * - UDR (UnderRun Error) interrupt pending bit is cleared by a read
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876 | * operation to SPI_SR register (SPI_I2S_GetITStatus()).
|
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877 | * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence:
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878 | * a read/write operation to SPI_SR register (SPI_I2S_GetITStatus())
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879 | * followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable
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880 | * the SPI).
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881 | * @retval None
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882 | */
|
||
883 | void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
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884 | { |
||
885 | uint16_t itpos = 0;
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886 | /* Check the parameters */
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887 | assert_param(IS_SPI_ALL_PERIPH(SPIx)); |
||
888 | assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT)); |
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889 | |||
890 | /* Get the SPI IT index */
|
||
891 | itpos = 0x01 << (SPI_I2S_IT & 0x0F); |
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892 | |||
893 | /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */
|
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894 | SPIx->SR = (uint16_t)~itpos; |
||
895 | } |
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896 | /**
|
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897 | * @}
|
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898 | */
|
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899 | |||
900 | /**
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901 | * @}
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902 | */
|
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903 | |||
904 | /**
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||
905 | * @}
|
||
906 | */
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907 | |||
908 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
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