amiro-blt / Target / Demo / ARMCM4_STM32F405_Power_Management_GCC / Boot / lib / uip / netdev.c @ 69661903
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1 | 69661903 | Thomas Schöpping | /*
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2 | * Copyright (c) 2001, Swedish Institute of Computer Science.
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3 | * All rights reserved.
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4 | *
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5 | * Redistribution and use in source and binary forms, with or without
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6 | * modification, are permitted provided that the following conditions
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7 | * are met:
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8 | *
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9 | * 1. Redistributions of source code must retain the above copyright
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10 | * notice, this list of conditions and the following disclaimer.
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11 | *
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12 | * 2. Redistributions in binary form must reproduce the above copyright
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13 | * notice, this list of conditions and the following disclaimer in the
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14 | * documentation and/or other materials provided with the distribution.
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15 | *
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16 | * 3. Neither the name of the Institute nor the names of its contributors
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17 | * may be used to endorse or promote products derived from this software
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18 | * without specific prior written permission.
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19 | *
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20 | * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
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21 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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22 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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23 | * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
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24 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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25 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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26 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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27 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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28 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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29 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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30 | * SUCH DAMAGE.
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31 | *
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32 | * Author: Adam Dunkels <adam@sics.se>
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33 | *
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34 | * $Id: netdev.c,v 1.8 2006/06/07 08:39:58 adam Exp $
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35 | */
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36 | |||
37 | |||
38 | /*---------------------------------------------------------------------------*/
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39 | #include "uip.h" |
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40 | #include "uip_arp.h" |
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41 | #include "boot.h" |
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42 | #include "stm32f4xx.h" /* STM32 registers */ |
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43 | #include "stm32f4xx_conf.h" /* STM32 peripheral drivers */ |
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44 | #include "stm32_eth.h" /* STM32 ethernet library */ |
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45 | #include <string.h> /* for memcpy */ |
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46 | |||
47 | |||
48 | /*---------------------------------------------------------------------------*/
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49 | #define NETDEV_DEFAULT_MACADDR0 (0x08) |
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50 | #define NETDEV_DEFAULT_MACADDR1 (0x00) |
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51 | #define NETDEV_DEFAULT_MACADDR2 (0x27) |
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52 | #define NETDEV_DEFAULT_MACADDR3 (0x69) |
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53 | #define NETDEV_DEFAULT_MACADDR4 (0x5B) |
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54 | #define NETDEV_DEFAULT_MACADDR5 (0x45) |
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55 | |||
56 | |||
57 | /*---------------------------------------------------------------------------*/
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58 | static void netdev_TxDscrInit(void); |
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59 | static void netdev_RxDscrInit(void); |
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60 | |||
61 | /*---------------------------------------------------------------------------*/
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62 | typedef union _TranDesc0_t |
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63 | { |
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64 | uint32_t Data; |
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65 | struct {
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66 | uint32_t DB : 1;
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67 | uint32_t UF : 1;
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68 | uint32_t ED : 1;
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69 | uint32_t CC : 4;
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70 | uint32_t VF : 1;
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71 | uint32_t EC : 1;
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72 | uint32_t LC : 1;
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73 | uint32_t NC : 1;
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74 | uint32_t LSC : 1;
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75 | uint32_t IPE : 1;
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76 | uint32_t FF : 1;
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77 | uint32_t JT : 1;
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78 | uint32_t ES : 1;
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79 | uint32_t IHE : 1;
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80 | uint32_t : 3;
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81 | uint32_t TCH : 1;
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82 | uint32_t TER : 1;
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83 | uint32_t CIC : 2;
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84 | uint32_t : 2;
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85 | uint32_t DP : 1;
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86 | uint32_t DC : 1;
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87 | uint32_t FS : 1;
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88 | uint32_t LSEG : 1;
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89 | uint32_t IC : 1;
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90 | uint32_t OWN : 1;
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91 | }; |
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92 | } TranDesc0_t, * pTranDesc0_t; |
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93 | |||
94 | typedef union _TranDesc1_t |
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95 | { |
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96 | uint32_t Data; |
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97 | struct {
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98 | uint32_t TBS1 :13;
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99 | uint32_t : 3;
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100 | uint32_t TBS2 :12;
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101 | uint32_t : 3;
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102 | }; |
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103 | } TranDesc1_t, * pTranDesc1_t; |
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104 | |||
105 | typedef union _RecDesc0_t |
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106 | { |
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107 | uint32_t Data; |
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108 | struct {
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109 | uint32_t RMAM_PCE : 1;
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110 | uint32_t CE : 1;
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111 | uint32_t DE : 1;
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112 | uint32_t RE : 1;
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113 | uint32_t RWT : 1;
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114 | uint32_t FT : 1;
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115 | uint32_t LC : 1;
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116 | uint32_t IPHCE : 1;
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117 | uint32_t LS : 1;
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118 | uint32_t FS : 1;
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119 | uint32_t VLAN : 1;
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120 | uint32_t OE : 1;
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121 | uint32_t LE : 1;
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122 | uint32_t SAF : 1;
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123 | uint32_t DERR : 1;
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124 | uint32_t ES : 1;
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125 | uint32_t FL :14;
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126 | uint32_t AFM : 1;
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127 | uint32_t OWN : 1;
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128 | }; |
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129 | } RecDesc0_t, * pRecDesc0_t; |
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130 | |||
131 | typedef union _recDesc1_t |
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132 | { |
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133 | uint32_t Data; |
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134 | struct {
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135 | uint32_t RBS1 :13;
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136 | uint32_t : 1;
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137 | uint32_t RCH : 1;
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138 | uint32_t RER : 1;
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139 | uint32_t RBS2 :14;
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140 | uint32_t DIC : 1;
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141 | }; |
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142 | } RecDesc1_t, * pRecDesc1_t; |
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143 | |||
144 | typedef union _EnetDmaDesc_t |
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145 | { |
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146 | uint32_t Data[4];
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147 | // Rx DMA descriptor
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148 | struct
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149 | { |
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150 | RecDesc0_t RxDesc0; |
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151 | RecDesc1_t RxDesc1; |
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152 | uint32_t * pBuffer; |
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153 | union
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154 | { |
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155 | uint32_t * pBuffer2; |
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156 | union _EnetDmaDesc_t * pEnetDmaNextDesc;
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157 | }; |
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158 | } Rx; |
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159 | // Tx DMA descriptor
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160 | struct
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161 | { |
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162 | TranDesc0_t TxDesc0; |
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163 | TranDesc1_t TxDesc1; |
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164 | uint32_t * pBuffer1; |
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165 | union
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166 | { |
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167 | uint32_t * pBuffer2; |
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168 | union _EnetDmaDesc_t * pEnetDmaNextDesc;
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169 | }; |
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170 | } Tx; |
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171 | } EnetDmaDesc_t, * pEnetDmaDesc_t; |
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172 | |||
173 | |||
174 | /*---------------------------------------------------------------------------*/
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175 | uint8_t RxBuff[UIP_CONF_BUFFER_SIZE] __attribute__ ((aligned (4)));
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176 | uint8_t TxBuff[UIP_CONF_BUFFER_SIZE] __attribute__ ((aligned (4)));
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177 | |||
178 | EnetDmaDesc_t EnetDmaRx __attribute__((aligned (128)));
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179 | EnetDmaDesc_t EnetDmaTx __attribute__ ((aligned (128)));
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180 | |||
181 | |||
182 | /*---------------------------------------------------------------------------*/
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183 | void netdev_init(void) |
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184 | { |
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185 | GPIO_InitTypeDef GPIO_InitStructure; |
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186 | ETH_InitTypeDef ETH_InitStructure; |
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187 | |||
188 | /* Enable ETHERNET clocks */
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189 | RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_ETH_MAC | RCC_AHB1Periph_ETH_MAC_Tx | |
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190 | RCC_AHB1Periph_ETH_MAC_Rx | RCC_AHB1Periph_ETH_MAC_PTP, ENABLE); |
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191 | |||
192 | |||
193 | /* Enable GPIOs clocks */
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194 | RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB | |
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195 | RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOG, ENABLE); |
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196 | |||
197 | /* Enable SYSCFG clock */
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198 | RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); |
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199 | /*Select RMII Interface*/
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200 | SYSCFG_ETH_MediaInterfaceConfig(SYSCFG_ETH_MediaInterface_RMII); |
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201 | |||
202 | /* ETHERNET pins configuration */
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203 | /* PA
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204 | ETH_RMII_REF_CLK: PA1
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205 | ETH_RMII_MDIO: PA2
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206 | ETH_RMII_MDINT: PA3
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207 | ETH_RMII_CRS_DV: PA7
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208 | */
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209 | |||
210 | /* Configure PA1, PA2, PA3 and PA7*/
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211 | GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_7; |
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212 | GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; |
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213 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; |
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214 | GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; |
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215 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; |
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216 | GPIO_Init(GPIOA, &GPIO_InitStructure); |
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217 | |||
218 | /* Connect PA1, PA2, PA3 and PA7 to ethernet module*/
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219 | GPIO_PinAFConfig(GPIOA, GPIO_PinSource1, GPIO_AF_ETH); |
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220 | GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_ETH); |
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221 | GPIO_PinAFConfig(GPIOA, GPIO_PinSource3, GPIO_AF_ETH); |
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222 | GPIO_PinAFConfig(GPIOA, GPIO_PinSource7, GPIO_AF_ETH); |
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223 | |||
224 | /* PB
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225 | ETH_RMII_TX_EN: PG11
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226 | */
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227 | |||
228 | /* Configure PG11*/
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229 | GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11; |
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230 | GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; |
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231 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; |
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232 | GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; |
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233 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; |
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234 | GPIO_Init(GPIOG, &GPIO_InitStructure); |
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235 | |||
236 | /* Connect PG11 to ethernet module*/
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237 | GPIO_PinAFConfig(GPIOG, GPIO_PinSource11, GPIO_AF_ETH); |
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238 | |||
239 | /* PC
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240 | ETH_RMII_MDC: PC1
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241 | ETH_RMII_RXD0: PC4
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242 | ETH_RMII_RXD1: PC5
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243 | */
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244 | |||
245 | /* Configure PC1, PC4 and PC5*/
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246 | GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5; |
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247 | GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; |
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248 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; |
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249 | GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; |
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250 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; |
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251 | GPIO_Init(GPIOC, &GPIO_InitStructure); |
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252 | |||
253 | /* Connect PC1, PC4 and PC5 to ethernet module*/
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254 | GPIO_PinAFConfig(GPIOC, GPIO_PinSource1, GPIO_AF_ETH); |
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255 | GPIO_PinAFConfig(GPIOC, GPIO_PinSource4, GPIO_AF_ETH); |
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256 | GPIO_PinAFConfig(GPIOC, GPIO_PinSource5, GPIO_AF_ETH); |
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257 | |||
258 | /* PG
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259 | ETH_RMII_TXD0: PG13
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260 | ETH_RMII_TXD1: PG14
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261 | */
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262 | |||
263 | /* Configure PG13 and PG14*/
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264 | GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13 | GPIO_Pin_14; |
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265 | GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; |
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266 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; |
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267 | GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; |
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268 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; |
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269 | GPIO_Init(GPIOG, &GPIO_InitStructure); |
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270 | |||
271 | /* Connect PG13 and PG14 to ethernet module*/
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272 | GPIO_PinAFConfig(GPIOG, GPIO_PinSource13, GPIO_AF_ETH); |
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273 | GPIO_PinAFConfig(GPIOG, GPIO_PinSource14, GPIO_AF_ETH); |
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274 | |||
275 | /* Reset ETHERNET on AHB Bus */
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276 | ETH_DeInit(); |
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277 | |||
278 | /* Software reset */
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279 | ETH_SoftwareReset(); |
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280 | |||
281 | /* Wait for software reset */
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282 | while(ETH_GetSoftwareResetStatus()==SET);
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283 | |||
284 | /* ETHERNET Configuration ------------------------------------------------------*/
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285 | /* Call ETH_StructInit if you don't like to configure all ETH_InitStructure parameter */
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286 | ETH_StructInit(Ð_InitStructure); |
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287 | |||
288 | /* Fill ETH_InitStructure parametrs */
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289 | /*------------------------ MAC -----------------------------------*/
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290 | ETH_InitStructure.ETH_AutoNegotiation = ETH_AutoNegotiation_Disable ; |
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291 | ETH_InitStructure.ETH_LoopbackMode = ETH_LoopbackMode_Disable; |
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292 | ETH_InitStructure.ETH_RetryTransmission = ETH_RetryTransmission_Disable; |
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293 | ETH_InitStructure.ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable; |
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294 | ETH_InitStructure.ETH_ReceiveAll = ETH_ReceiveAll_Enable; |
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295 | ETH_InitStructure.ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable; |
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296 | ETH_InitStructure.ETH_PromiscuousMode = ETH_PromiscuousMode_Disable; |
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297 | ETH_InitStructure.ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect; |
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298 | ETH_InitStructure.ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect; |
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299 | ETH_InitStructure.ETH_Mode = ETH_Mode_FullDuplex; |
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300 | ETH_InitStructure.ETH_Speed = ETH_Speed_100M; |
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301 | |||
302 | unsigned int PhyAddr; |
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303 | union {
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304 | uint32_t HI_LO; |
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305 | struct
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306 | { |
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307 | uint16_t LO; |
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308 | uint16_t HI; |
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309 | }; |
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310 | } PHYID; |
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311 | for(PhyAddr = 0; 32 > PhyAddr; PhyAddr++) |
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312 | { |
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313 | // datasheet for the ks8721bl ethernet controller (http://www.micrel.com/_PDF/Ethernet/datasheets/ks8721bl-sl.pdf)
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314 | // page 20 --> PHY Identifier 1 and 2
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315 | PHYID.HI = ETH_ReadPHYRegister(PhyAddr,2); // 0x0022 |
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316 | PHYID.LO = ETH_ReadPHYRegister(PhyAddr,3); // 0x1619 |
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317 | if ((0x00221619 == PHYID.HI_LO) || (0x0007C0F1 == PHYID.HI_LO)) |
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318 | break;
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319 | } |
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320 | if (32 < PhyAddr) |
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321 | { |
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322 | ASSERT_RT(BLT_FALSE); |
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323 | } |
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324 | /* Configure Ethernet */
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325 | if(0 == ETH_Init(Ð_InitStructure, PhyAddr)) |
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326 | { |
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327 | ASSERT_RT(BLT_FALSE); |
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328 | } |
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329 | |||
330 | netdev_TxDscrInit(); |
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331 | netdev_RxDscrInit(); |
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332 | ETH_Start(); |
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333 | } |
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334 | |||
335 | |||
336 | /*---------------------------------------------------------------------------*/
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337 | void netdev_init_mac(void) |
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338 | { |
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339 | struct uip_eth_addr macAddress;
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340 | |||
341 | /* set the default MAC address */
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342 | macAddress.addr[0] = NETDEV_DEFAULT_MACADDR0;
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343 | macAddress.addr[1] = NETDEV_DEFAULT_MACADDR1;
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344 | macAddress.addr[2] = NETDEV_DEFAULT_MACADDR2;
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345 | macAddress.addr[3] = NETDEV_DEFAULT_MACADDR3;
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346 | macAddress.addr[4] = NETDEV_DEFAULT_MACADDR4;
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347 | macAddress.addr[5] = NETDEV_DEFAULT_MACADDR5;
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348 | uip_setethaddr(macAddress); |
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349 | } |
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350 | |||
351 | |||
352 | /*---------------------------------------------------------------------------*/
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353 | unsigned int netdev_read(void) |
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354 | { |
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355 | uint32_t size; |
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356 | /*check for validity*/
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357 | if(0 == EnetDmaRx.Rx.RxDesc0.OWN) |
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358 | { |
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359 | /*Get the size of the packet*/
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360 | size = EnetDmaRx.Rx.RxDesc0.FL; // CRC
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361 | memcpy(uip_buf, RxBuff, size); //string.h library*/
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362 | } |
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363 | else
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364 | { |
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365 | return 0; |
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366 | } |
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367 | /* Give the buffer back to ENET */
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368 | EnetDmaRx.Rx.RxDesc0.OWN = 1;
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369 | /* Start the receive operation */
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370 | ETH->DMARPDR = 1;
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371 | /* Return no error */
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372 | return size;
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373 | } |
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374 | |||
375 | |||
376 | /*---------------------------------------------------------------------------*/
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377 | void netdev_send(void) |
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378 | { |
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379 | while(EnetDmaTx.Tx.TxDesc0.OWN);
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380 | |||
381 | /* Copy the application buffer to the driver buffer
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382 | Using this MEMCOPY_L2L_BY4 makes the copy routine faster
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383 | than memcpy */
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384 | memcpy(TxBuff, uip_buf, uip_len); |
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385 | |||
386 | /* Assign ENET address to Temp Tx Array */
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387 | EnetDmaTx.Tx.pBuffer1 = (uint32_t *)TxBuff; |
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388 | |||
389 | /* Setting the Frame Length*/
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390 | EnetDmaTx.Tx.TxDesc0.Data = 0;
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391 | EnetDmaTx.Tx.TxDesc0.TCH = 1;
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392 | EnetDmaTx.Tx.TxDesc0.LSEG = 1;
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393 | EnetDmaTx.Tx.TxDesc0.FS = 1;
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394 | EnetDmaTx.Tx.TxDesc0.DC = 0;
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395 | EnetDmaTx.Tx.TxDesc0.DP = 0;
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396 | |||
397 | EnetDmaTx.Tx.TxDesc1.Data = 0;
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398 | EnetDmaTx.Tx.TxDesc1.TBS1 = (uip_len&0xFFF);
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399 | |||
400 | /* Start the ENET by setting the VALID bit in dmaPackStatus of current descr*/
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401 | EnetDmaTx.Tx.TxDesc0.OWN = 1;
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402 | |||
403 | /* Start the transmit operation */
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404 | ETH->DMATPDR = 1;
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405 | } |
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406 | |||
407 | |||
408 | /*---------------------------------------------------------------------------*/
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409 | static void netdev_RxDscrInit(void) |
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410 | { |
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411 | /* Initialization */
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412 | /* Assign temp Rx array to the ENET buffer */
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413 | EnetDmaRx.Rx.pBuffer = (uint32_t *)RxBuff; |
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414 | |||
415 | /* Initialize RX ENET Status and control */
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416 | EnetDmaRx.Rx.RxDesc0.Data = 0;
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417 | |||
418 | /* Initialize the next descriptor- In our case its single descriptor */
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419 | EnetDmaRx.Rx.pEnetDmaNextDesc = &EnetDmaRx; |
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420 | |||
421 | EnetDmaRx.Rx.RxDesc1.Data = 0;
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422 | EnetDmaRx.Rx.RxDesc1.RER = 0; // end of ring |
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423 | EnetDmaRx.Rx.RxDesc1.RCH = 1; // end of ring |
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424 | |||
425 | /* Set the max packet size */
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426 | EnetDmaRx.Rx.RxDesc1.RBS1 = UIP_CONF_BUFFER_SIZE; |
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427 | |||
428 | /* Setting the VALID bit */
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429 | EnetDmaRx.Rx.RxDesc0.OWN = 1;
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430 | /* Setting the RX NEXT Descriptor Register inside the ENET */
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431 | ETH->DMARDLAR = (uint32_t)&EnetDmaRx; |
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432 | } |
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433 | |||
434 | |||
435 | /*---------------------------------------------------------------------------*/
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436 | static void netdev_TxDscrInit(void) |
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437 | { |
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438 | /* ENET Start Address */
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439 | EnetDmaTx.Tx.pBuffer1 = (uint32_t *)TxBuff; |
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440 | |||
441 | /* Next Descriptor Address */
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442 | EnetDmaTx.Tx.pEnetDmaNextDesc = &EnetDmaTx; |
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443 | |||
444 | /* Initialize ENET status and control */
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445 | EnetDmaTx.Tx.TxDesc0.TCH = 1;
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446 | EnetDmaTx.Tx.TxDesc0.Data = 0;
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447 | EnetDmaTx.Tx.TxDesc1.Data = 0;
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448 | /* Tx next set to Tx descriptor base */
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449 | ETH->DMATDLAR = (uint32_t)&EnetDmaTx; |
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450 | |||
451 | } |