amiro-lld / include / PCAL6524 / v1 / alld_PCAL6524_v1.h @ fe058578
History | View | Annotate | Download (16.64 KB)
| 1 | e3287406 | Thomas Schöpping | /*
|
|---|---|---|---|
| 2 | AMiRo-LLD is a compilation of low-level hardware drivers for the Autonomous Mini Robot (AMiRo) platform.
|
||
| 3 | Copyright (C) 2016..2019 Thomas Schöpping et al.
|
||
| 4 | |||
| 5 | This program is free software: you can redistribute it and/or modify
|
||
| 6 | it under the terms of the GNU Lesser General Public License as published by
|
||
| 7 | the Free Software Foundation, either version 3 of the License, or
|
||
| 8 | (at your option) any later version.
|
||
| 9 | |||
| 10 | This program is distributed in the hope that it will be useful,
|
||
| 11 | but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||
| 12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||
| 13 | GNU Lesser General Public License for more details.
|
||
| 14 | |||
| 15 | You should have received a copy of the GNU Lesser General Public License
|
||
| 16 | along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||
| 17 | */
|
||
| 18 | |||
| 19 | /**
|
||
| 20 | 1d5bcc82 | Thomas Schöpping | * @file alld_PCAL6524_v1.h
|
| 21 | e3287406 | Thomas Schöpping | * @brief GPIO extender macros and structures.
|
| 22 | *
|
||
| 23 | * @addtogroup lld_gpioext
|
||
| 24 | * @{
|
||
| 25 | */
|
||
| 26 | |||
| 27 | 1d5bcc82 | Thomas Schöpping | #ifndef AMIROLLD_PCAL6524_V1_H
|
| 28 | #define AMIROLLD_PCAL6524_V1_H
|
||
| 29 | e3287406 | Thomas Schöpping | |
| 30 | #include <amiro-lld.h> |
||
| 31 | |||
| 32 | 1d5bcc82 | Thomas Schöpping | #if (defined(AMIROLLD_CFG_PCAL6524) && (AMIROLLD_CFG_PCAL6524 == 1)) || defined(__DOXYGEN__) |
| 33 | e3287406 | Thomas Schöpping | |
| 34 | ef078306 | Thomas Schöpping | /******************************************************************************/
|
| 35 | /* CONSTANTS */
|
||
| 36 | /******************************************************************************/
|
||
| 37 | |||
| 38 | e3287406 | Thomas Schöpping | /**
|
| 39 | * @brief Maximum I2C frequency.
|
||
| 40 | */
|
||
| 41 | #define PCAL6524_LLD_I2C_MAXFREQUENCY 1000000 |
||
| 42 | |||
| 43 | /**
|
||
| 44 | * @brief A falling edge indicats an interrupt.
|
||
| 45 | */
|
||
| 46 | #define PCAL6524_LLD_INT_EDGE APAL_GPIO_EDGE_FALLING
|
||
| 47 | |||
| 48 | ef078306 | Thomas Schöpping | /******************************************************************************/
|
| 49 | /* SETTINGS */
|
||
| 50 | /******************************************************************************/
|
||
| 51 | |||
| 52 | /******************************************************************************/
|
||
| 53 | /* CHECKS */
|
||
| 54 | /******************************************************************************/
|
||
| 55 | |||
| 56 | /******************************************************************************/
|
||
| 57 | /* DATA STRUCTURES AND TYPES */
|
||
| 58 | /******************************************************************************/
|
||
| 59 | |||
| 60 | e3287406 | Thomas Schöpping | /**
|
| 61 | * @brief The PCAL6524Driver sruct.
|
||
| 62 | */
|
||
| 63 | typedef struct { |
||
| 64 | apalI2CDriver_t* i2cd; |
||
| 65 | apalI2Caddr_t addr; |
||
| 66 | } PCAL6524Driver; |
||
| 67 | |||
| 68 | /**
|
||
| 69 | * @brief Possible I2C address configurations.
|
||
| 70 | */
|
||
| 71 | enum {
|
||
| 72 | PCAL6524_LLD_I2C_ADDR_FIXED = 0x0020u, /**< Fixed part of the I2C address. */ |
||
| 73 | PCAL6524_LLD_I2C_ADDR_SCL = 0x0020u, /**< ADDR pin connected to SCL. */ |
||
| 74 | PCAL6524_LLD_I2C_ADDR_SDA = 0x0021u, /**< ADDR pin connected to SDA. */ |
||
| 75 | PCAL6524_LLD_I2C_ADDR_VSS = 0x0022u, /**< ADDR pin connected to VSS. */ |
||
| 76 | PCAL6524_LLD_I2C_ADDR_VDD = 0x0023u, /**< ADDR pin connected to VDD. */ |
||
| 77 | PCAL6524_LLD_I2C_ADDR_DEVICEID = 0x007Cu, /**< Special address to read device ID information. */ |
||
| 78 | }; |
||
| 79 | |||
| 80 | /**
|
||
| 81 | * @brief Command bit to enable auto-incrementation of command value.
|
||
| 82 | * @details Can be added (ORed) to any command value.
|
||
| 83 | */
|
||
| 84 | #define PCAL6524_LLD_CMD_AUTOINCREMENT 0x80u |
||
| 85 | |||
| 86 | /**
|
||
| 87 | * @brief The total number of registers that can be accessed.
|
||
| 88 | * @note This is the maximum number of bytes that may be read or written continuously.
|
||
| 89 | */
|
||
| 90 | #define PCAL6524_LLD_NUM_REGISTERS 52 |
||
| 91 | |||
| 92 | typedef union { |
||
| 93 | uint8_t raw[3];
|
||
| 94 | struct {
|
||
| 95 | uint16_t name : 12;
|
||
| 96 | uint16_t part : 9;
|
||
| 97 | uint8_t revision : 3;
|
||
| 98 | }; |
||
| 99 | } pcal6524_lld_deviceid_t; |
||
| 100 | |||
| 101 | /**
|
||
| 102 | * @brief Control commands for the PCAL6524.
|
||
| 103 | */
|
||
| 104 | typedef enum { |
||
| 105 | PCAL6524_LLD_CMD_INPUT_P0 = 0x00u, /**< read only */ |
||
| 106 | PCAL6524_LLD_CMD_INPUT_P1 = 0x01u, /**< read only */ |
||
| 107 | PCAL6524_LLD_CMD_INPUT_P2 = 0x02u, /**< read only */ |
||
| 108 | PCAL6524_LLD_CMD_OUTPUT_P0 = 0x04u, /**< read/write */ |
||
| 109 | PCAL6524_LLD_CMD_OUTPUT_P1 = 0x05u, /**< read/write */ |
||
| 110 | PCAL6524_LLD_CMD_OUTPUT_P2 = 0x06u, /**< read/write */ |
||
| 111 | PCAL6524_LLD_CMD_POLARITYINVERSION_P0 = 0x08u, /**< read/write */ |
||
| 112 | PCAL6524_LLD_CMD_POLARITYINVERSION_P1 = 0x09u, /**< read/write */ |
||
| 113 | PCAL6524_LLD_CMD_POLARITYINVERSION_P2 = 0x0Au, /**< read/write */ |
||
| 114 | PCAL6524_LLD_CMD_CONFIGURATION_P0 = 0x0Cu, /**< read/write */ |
||
| 115 | PCAL6524_LLD_CMD_CONFIGURATION_P1 = 0x0Du, /**< read/write */ |
||
| 116 | PCAL6524_LLD_CMD_CONFIGURATION_P2 = 0x0Eu, /**< read/write */ |
||
| 117 | PCAL6524_LLD_CMD_OUTPUTDRIVESTRENGTH_P0A = 0x40u, /**< read/write */ |
||
| 118 | PCAL6524_LLD_CMD_OUTPUTDRIVESTRENGTH_P0B = 0x41u, /**< read/write */ |
||
| 119 | PCAL6524_LLD_CMD_OUTPUTDRIVESTRENGTH_P1A = 0x42u, /**< read/write */ |
||
| 120 | PCAL6524_LLD_CMD_OUTPUTDRIVESTRENGTH_P1B = 0x43u, /**< read/write */ |
||
| 121 | PCAL6524_LLD_CMD_OUTPUTDRIVESTRENGTH_P2A = 0x44u, /**< read/write */ |
||
| 122 | PCAL6524_LLD_CMD_OUTPUTDRIVESTRENGTH_P2B = 0x45u, /**< read/write */ |
||
| 123 | PCAL6524_LLD_CMD_INPUTLATCH_P0 = 0x48u, /**< read/write */ |
||
| 124 | PCAL6524_LLD_CMD_INPUTLATCH_P1 = 0x49u, /**< read/write */ |
||
| 125 | PCAL6524_LLD_CMD_INPUTLATCH_P2 = 0x4Au, /**< read/write */ |
||
| 126 | PCAL6524_LLD_CMD_PUPDENABLE_P0 = 0x4Cu, /**< read/write */ |
||
| 127 | PCAL6524_LLD_CMD_PUPDENABLE_P1 = 0x4Du, /**< read/write */ |
||
| 128 | PCAL6524_LLD_CMD_PUPDENABLE_P2 = 0x4Eu, /**< read/write */ |
||
| 129 | PCAL6524_LLD_CMD_PUPDSELECTION_P0 = 0x50u, /**< read/write */ |
||
| 130 | PCAL6524_LLD_CMD_PUPDSELECTION_P1 = 0x51u, /**< read/write */ |
||
| 131 | PCAL6524_LLD_CMD_PUPDSELECTION_P2 = 0x52u, /**< read/write */ |
||
| 132 | PCAL6524_LLD_CMD_INTERRUPTMASK_P0 = 0x54u, /**< read/write */ |
||
| 133 | PCAL6524_LLD_CMD_INTERRUPTMASK_P1 = 0x55u, /**< read/write */ |
||
| 134 | PCAL6524_LLD_CMD_INTERRUPTMASK_P2 = 0x56u, /**< read/write */ |
||
| 135 | PCAL6524_LLD_CMD_INTERRUPTSTATUS_P0 = 0x58u, /**< read only */ |
||
| 136 | PCAL6524_LLD_CMD_INTERRUPTSTATUS_P1 = 0x59u, /**< read only */ |
||
| 137 | PCAL6524_LLD_CMD_INTERRUPTSTATUS_P2 = 0x5Au, /**< read only */ |
||
| 138 | PCAL6524_LLD_CMD_OUTPUTCONFIGURATION = 0x5Cu, /**< read/write */ |
||
| 139 | PCAL6524_LLD_CMD_INTERRUPTEDGE_P0A = 0x60u, /**< read/write */ |
||
| 140 | PCAL6524_LLD_CMD_INTERRUPTEDGE_P0B = 0x61u, /**< read/write */ |
||
| 141 | PCAL6524_LLD_CMD_INTERRUPTEDGE_P1A = 0x62u, /**< read/write */ |
||
| 142 | PCAL6524_LLD_CMD_INTERRUPTEDGE_P1B = 0x63u, /**< read/write */ |
||
| 143 | PCAL6524_LLD_CMD_INTERRUPTEDGE_P2A = 0x64u, /**< read/write */ |
||
| 144 | PCAL6524_LLD_CMD_INTERRUPTEDGE_P2B = 0x65u, /**< read/write */ |
||
| 145 | PCAL6524_LLD_CMD_INTERRUPTCLEAR_P0 = 0x68u, /**< write only */ |
||
| 146 | PCAL6524_LLD_CMD_INTERRUPTCLEAR_P1 = 0x69u, /**< write only */ |
||
| 147 | PCAL6524_LLD_CMD_INTERRUPTCLEAR_P2 = 0x6Au, /**< write only */ |
||
| 148 | PCAL6524_LLD_CMD_INPUTSTATUS_P0 = 0x6Cu, /**< read only */ |
||
| 149 | PCAL6524_LLD_CMD_INPUTSTATUS_P1 = 0x6Du, /**< read only */ |
||
| 150 | PCAL6524_LLD_CMD_INPUTSTATUS_P2 = 0x6Eu, /**< read only */ |
||
| 151 | PCAL6524_LLD_CMD_INDIVIDUALPINOUTPUTCONFIGURATION_P0 = 0x70u, /**< read/write */ |
||
| 152 | PCAL6524_LLD_CMD_INDIVIDUALPINOUTPUTCONFIGURATION_P1 = 0x71u, /**< read/write */ |
||
| 153 | PCAL6524_LLD_CMD_INDIVIDUALPINOUTPUTCONFIGURATION_P2 = 0x72u, /**< read/write */ |
||
| 154 | PCAL6524_LLD_CMD_SWITCHDEBOUNCEENABLE_P0 = 0x74u, /**< read/write */ |
||
| 155 | PCAL6524_LLD_CMD_SWITCHDEBOUNCEENABLE_P1 = 0x75u, /**< read/write */ |
||
| 156 | PCAL6524_LLD_CMD_SWITCHDEBOUNCECOUNT = 0x76u, /**< read/write */ |
||
| 157 | } pcal6524_lld_cmd_t; |
||
| 158 | |||
| 159 | /**
|
||
| 160 | * @brief Input register bit values.
|
||
| 161 | * @details The bits in the input register reflect the incoming logic levels per pin.
|
||
| 162 | * If a pin is configured as ouput, the bit reflects th set value or is forced to 0 in case the outpus is configured as open-drain.
|
||
| 163 | * If a pin is configured as input with latched interrupts, reading the according port will reset the input value and clear the interrupt.
|
||
| 164 | */
|
||
| 165 | typedef enum { |
||
| 166 | PCAL6524_LLD_INPUT_LOW = 0b0,
|
||
| 167 | PCAL6524_LLD_INPUT_HIGH = 0b1,
|
||
| 168 | } pcal6524_lld_input_t; |
||
| 169 | |||
| 170 | /**
|
||
| 171 | * @brief Output register bit values.
|
||
| 172 | * @details Defines the logic level to be driven by output pins.
|
||
| 173 | * The default value (after reset) is 0b1 (high),
|
||
| 174 | */
|
||
| 175 | typedef enum { |
||
| 176 | PCAL6524_LLD_OUTPUT_LOW = 0b0,
|
||
| 177 | PCAL6524_LLD_OUTPUT_HIGH = 0b1,
|
||
| 178 | } pcal6524_lld_output_t; |
||
| 179 | |||
| 180 | /**
|
||
| 181 | * @brief Polarity inversion register values.
|
||
| 182 | * @details Allows to inverse the logic values written to the input register.
|
||
| 183 | * The default value (after reset) is 0b0 (disabled).
|
||
| 184 | */
|
||
| 185 | typedef enum { |
||
| 186 | PCAL6524_LLD_POLARITYINVERSION_DISABLED = 0b0,
|
||
| 187 | PCAL6524_LLD_POLARITYINVERSION_ENABLED = 0b1,
|
||
| 188 | } pcal6524_lld_polarityinversion_t; |
||
| 189 | |||
| 190 | /**
|
||
| 191 | * @brief Configuration regsiter bit values.
|
||
| 192 | * @details Configures the direction of the I/O pins to either high-impedance input or output.
|
||
| 193 | * The default value (after reset) is 0b1 (input).
|
||
| 194 | */
|
||
| 195 | typedef enum { |
||
| 196 | PCAL6524_LLD_CONFIGURATION_INPUT = 0b1,
|
||
| 197 | PCAL6524_LLD_CONFIGURATION_OUTPUT = 0b0,
|
||
| 198 | } pcal6524_lld_configuration_t; |
||
| 199 | |||
| 200 | /**
|
||
| 201 | * @brief Output drive strength register mask values.
|
||
| 202 | * @details Configures maximum current of output pins can be defined via a 2 bit mask per pin.
|
||
| 203 | * Toggling multiple output pins simultaneously a peak current may induce noise to supply voltage and ground.
|
||
| 204 | * By lowering the maximum current per pin. this effect can be minimized.
|
||
| 205 | * The default value (after reset) is 0b11 (factor 1x)
|
||
| 206 | */
|
||
| 207 | typedef enum { |
||
| 208 | PCAL6524_LL_OUTPUTDRIVESTRENGTH_0_25 = 0b00,
|
||
| 209 | PCAL6524_LL_OUTPUTDRIVESTRENGTH_0_5 = 0b01,
|
||
| 210 | PCAL6524_LL_OUTPUTDRIVESTRENGTH_0_75 = 0b10,
|
||
| 211 | PCAL6524_LL_OUTPUTDRIVESTRENGTH_1 = 0b11,
|
||
| 212 | } pcal6524_lld_outputdrivestrength_t; |
||
| 213 | |||
| 214 | /**
|
||
| 215 | * @brief Input latch register bit values.
|
||
| 216 | * @details Allows to latch interrupt and input states per pin, if an interrupt occurred.
|
||
| 217 | * The default value (after reset) is 0b0 (disabled).
|
||
| 218 | */
|
||
| 219 | typedef enum { |
||
| 220 | PCAL6524_LLD_INPUTLATCH_ENABLED = 0b1,
|
||
| 221 | PCAL6524_LLD_INPUTLATCH_DISABLED = 0b0,
|
||
| 222 | } pcal6524_lld_inputlatch_t; |
||
| 223 | |||
| 224 | /**
|
||
| 225 | * @brief Pull-up/Pull-down enable register bis values.
|
||
| 226 | * @details Configures per pin whether the pull-up/pull-down resistors shall be enabled.
|
||
| 227 | * If a pin is configured as open-drain output, the setting in this register are overridden and the resistors are disconnected.
|
||
| 228 | * The default value (after reset) is 0b0 (disabled).
|
||
| 229 | */
|
||
| 230 | typedef enum { |
||
| 231 | PCAL6524_LLD_PUPD_ENABLED = 0b1,
|
||
| 232 | PCAL6524_LLD_PUPD_DISABLED = 0b0,
|
||
| 233 | } pcal6524_lld_pupdenable_t; |
||
| 234 | |||
| 235 | /**
|
||
| 236 | * @brief Pull-up/Pull-dpwn selection register bit values.
|
||
| 237 | * @details Selects between pull-up and pull-down resistor (100 kΩ) per pin.
|
||
| 238 | * Has no effect if the according bit is the pull-up/pull-down enable register is disabled.
|
||
| 239 | * The default value (after reset) is 0b1 (pull-up).
|
||
| 240 | */
|
||
| 241 | typedef enum { |
||
| 242 | PCAL6524_LLD_PUPDSELECTION_PULLUP = 0b1,
|
||
| 243 | PCAL6524_LLD_PUPDSELECTION_PULLDOWN = 0b0,
|
||
| 244 | } pcal6524_lld_pupdselection_t; |
||
| 245 | |||
| 246 | /**
|
||
| 247 | * @brief Interrupt mask register bit values.
|
||
| 248 | * @details Allows to enable (value 0) or disable (value 1) interrupts per pin.
|
||
| 249 | * The default value (after reset) is 0b1 (interrupt disabled).
|
||
| 250 | */
|
||
| 251 | typedef enum { |
||
| 252 | PCAL6524_LLD_INTERRUPTMASK_ENABLED = 0b0,
|
||
| 253 | PCAL6524_LLD_INTERRUPTMASK_DSIABLED = 0b1,
|
||
| 254 | } pcal6524_lld_interruptmask_t; |
||
| 255 | |||
| 256 | /**
|
||
| 257 | * @brief Interrupt status register bit value.
|
||
| 258 | * @details Indicates whether an interrupt occurred per pin.
|
||
| 259 | * After reset the register is initialized with 0b0 (no interrupt occurred yet).
|
||
| 260 | */
|
||
| 261 | typedef enum { |
||
| 262 | PCAL6524_LLD_INTERRUPTSTATUS_ACTIVE = 0b1,
|
||
| 263 | PCAL6524_LLD_INTERRUPTSTATUS_INACTIVE = 0b0,
|
||
| 264 | } pcal6542_lld_interruptstatus_t; |
||
| 265 | |||
| 266 | /**
|
||
| 267 | * @brief Output port configuration register mask of valid bits.
|
||
| 268 | */
|
||
| 269 | #define PCAL6524_LLD_OUTPUTCONFIGURATION_MASK 0x07u |
||
| 270 | |||
| 271 | /**
|
||
| 272 | * @brief Output port configuration register mask for I/O port 0.
|
||
| 273 | */
|
||
| 274 | #define PCAL6524_LLD_OUTPUTCONFIGURATION_MASK_PORT0 0x01u |
||
| 275 | |||
| 276 | /**
|
||
| 277 | * @brief Output port configuration register mask for I/O port 1.
|
||
| 278 | */
|
||
| 279 | #define PCAL6524_LLD_OUTPUTCONFIGURATION_MASK_PORT1 0x02u |
||
| 280 | |||
| 281 | /**
|
||
| 282 | * @brief Output port configuration register mask for I/O port 2.
|
||
| 283 | */
|
||
| 284 | #define PCAL6524_LLD_OUTPUTCONFIGURATION_MASK_PORT2 0x04u |
||
| 285 | |||
| 286 | /**
|
||
| 287 | * @brief Output port configuration register bit values.
|
||
| 288 | * @details Configures all ouput pins per port to be push-pull or open-drain.
|
||
| 289 | * The default value (after reset) is 0b0 (push-pull).
|
||
| 290 | */
|
||
| 291 | typedef enum { |
||
| 292 | PCAL6524_LLD_OUTPUTCONFIGURATION_PUSHPULL = 0b0,
|
||
| 293 | PCAL6524_LLD_OUTPUTCONFIGURATION_OPENDRAIN = 0b1,
|
||
| 294 | } pcal6524_lld_outputconfiguration_t; |
||
| 295 | |||
| 296 | /**
|
||
| 297 | * @brief Interrupt edge register mask values.
|
||
| 298 | * @details Configures the type of event that would cause an interrupt per pin.
|
||
| 299 | * The default value (after reset) is 0b00 (level triggered).
|
||
| 300 | */
|
||
| 301 | typedef enum { |
||
| 302 | PCAL6524_LLD_INTERRUPTEDGE_LEVELTRIGGERED = 0b00,
|
||
| 303 | PCAL6524_LLD_INTERRUPTEDGE_RISINGEDGE = 0b01,
|
||
| 304 | PCAL6524_LLD_INTERRUPTEDGE_FALLINGEDGE = 0b10,
|
||
| 305 | PCAL6524_LLD_INTERRUPTEDGE_ANYEDGE = 0b11,
|
||
| 306 | } pcal6524_lld_interruptedge_t; |
||
| 307 | |||
| 308 | /**
|
||
| 309 | * @brief Input status register bit values.
|
||
| 310 | * @details Reflects the current logic level per pin similar to the input register.
|
||
| 311 | * However, values are not latched and reading the register will not reset interrupts.
|
||
| 312 | */
|
||
| 313 | typedef enum { |
||
| 314 | PCAL6524_LLD_INPUTSTATUS_LOW = 0b0,
|
||
| 315 | PCAL6524_LLD_INPUTSTATUS_HIGH = 0b1,
|
||
| 316 | } pcal6524_lld_inputstatus_t; |
||
| 317 | |||
| 318 | /**
|
||
| 319 | * @brief Individual pin output configuration register bit values.
|
||
| 320 | * @details Can be used to invert the port-wide push-pull/open-drain configuration via the ouput port configuration register per pin.
|
||
| 321 | * the default value (after reset) is 0b0 (not inverted).
|
||
| 322 | */
|
||
| 323 | typedef enum { |
||
| 324 | PCAL6524_LLD_INDIVIDUALPINOUTPUTCONFIGURATION_PORT = 0b0,
|
||
| 325 | PCAL6524_LLD_INDIVIDUALPINOUTPUTCONFIGURATION_INVERTED = 0b1,
|
||
| 326 | } pcal6524_lld_individualpinoutputconfiguration_t; |
||
| 327 | |||
| 328 | /**
|
||
| 329 | * @brief Switch debounce enable register bit values.
|
||
| 330 | * @details Allows to enable debounce functionality for I/O ports 0 and 1.
|
||
| 331 | * In order to use the debounce feature, an oscillator signal must be applied to pin 0 of port 0.
|
||
| 332 | * The default value (after reset) is 0b0 (disabled).
|
||
| 333 | */
|
||
| 334 | typedef enum { |
||
| 335 | PCAL6524_LLD_SWITCHDEBOUNCE_ENABLED = 0b1,
|
||
| 336 | PCAL6524_LLD_SWITCHDEBOUNCE_DISABLED = 0b0,
|
||
| 337 | } pcal6524_lld_switchdebounceenable_t; |
||
| 338 | |||
| 339 | ef078306 | Thomas Schöpping | /******************************************************************************/
|
| 340 | /* MACROS */
|
||
| 341 | /******************************************************************************/
|
||
| 342 | |||
| 343 | /******************************************************************************/
|
||
| 344 | /* EXTERN DECLARATIONS */
|
||
| 345 | /******************************************************************************/
|
||
| 346 | |||
| 347 | e3287406 | Thomas Schöpping | #ifdef __cplusplus
|
| 348 | extern "C" { |
||
| 349 | #endif
|
||
| 350 | uint8_t pcal6524_lld_cmd_groupsize(const pcal6524_lld_cmd_t cmd);
|
||
| 351 | |||
| 352 | // apalExitStatus_t pcal6524_lld_read_id(const PCAL6524Driver* const pcal6524d, uint8_t* const data, const apalTime_t timeout);
|
||
| 353 | apalExitStatus_t pcal6524_lld_read_reg(const PCAL6524Driver* const pcal6524d, const pcal6524_lld_cmd_t reg, uint8_t* const data, const apalTime_t timeout); |
||
| 354 | apalExitStatus_t pcal6524_lld_write_reg(const PCAL6524Driver* const pcal6524d, const pcal6524_lld_cmd_t reg, const uint8_t data, const apalTime_t timeout); |
||
| 355 | apalExitStatus_t pcal6524_lld_read_group(const PCAL6524Driver* const pcal6524d, const pcal6524_lld_cmd_t reg, uint8_t* const data, const apalTime_t timeout); |
||
| 356 | apalExitStatus_t pcal6524_lld_write_group(const PCAL6524Driver* const pcal6524d, const pcal6524_lld_cmd_t reg, const uint8_t* const data, const apalTime_t timeout); |
||
| 357 | apalExitStatus_t pcal6524_lld_read_continuous(const PCAL6524Driver* const pcal6524d, const pcal6524_lld_cmd_t reg, uint8_t* const data, const uint8_t length, const apalTime_t timeout); |
||
| 358 | apalExitStatus_t pcal6524_lld_write_continuous(const PCAL6524Driver* const pcal6524d, const pcal6524_lld_cmd_t reg, const uint8_t* const data, const uint8_t length, const apalTime_t timeout); |
||
| 359 | #ifdef __cplusplus
|
||
| 360 | } |
||
| 361 | #endif
|
||
| 362 | |||
| 363 | ef078306 | Thomas Schöpping | /******************************************************************************/
|
| 364 | /* INLINE FUNCTIONS */
|
||
| 365 | /******************************************************************************/
|
||
| 366 | |||
| 367 | 1d5bcc82 | Thomas Schöpping | #endif /* defined(AMIROLLD_CFG_PCAL6524) && (AMIROLLD_CFG_PCAL6524 == 1) */ |
| 368 | e3287406 | Thomas Schöpping | |
| 369 | 1d5bcc82 | Thomas Schöpping | #endif /* AMIROLLD_PCAL6524_V1_H */ |
| 370 | e3287406 | Thomas Schöpping | |
| 371 | /** @} */ |