amiro-os / modules / LightRing_1-0 / board.h @ 53710ca3
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/*
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AMiRo-OS is an operating system designed for the Autonomous Mini Robot (AMiRo) platform.
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Copyright (C) 2016..2018 Thomas Schöpping et al.
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file
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* @brief LightRing v1.0 Board specific macros.
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*
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* @addtogroup lightring_board
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* @{
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*/
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#ifndef _BOARD_H_
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#define _BOARD_H_
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/*
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* Setup for AMiRo LightRing v1.0 board.
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*/
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/*
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* Board identifier.
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*/
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#define BOARD_LIGHTRING
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#define BOARD_NAME "AMiRo LightRing" |
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#define BOARD_VERSION "1.0" |
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/*
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* Board oscillators-related settings.
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* NOTE: LSE not fitted.
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*/
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#if !defined(STM32_LSECLK)
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#define STM32_LSECLK 0U |
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#endif
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#if !defined(STM32_HSECLK)
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#define STM32_HSECLK 8000000U |
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#endif
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/*
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* Board voltages.
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* Required for performance limits calculation.
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*/
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#define STM32_VDD 330U |
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/*
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* MCU type as defined in the ST header.
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*/
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#define STM32F103xE
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/*
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* IO pins assignments.
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*/
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#define GPIOA_PIN0 0U |
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#define GPIOA_PIN1 1U |
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#define GPIOA_LASER_RX 2U |
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#define GPIOA_LASER_TX 3U |
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#define GPIOA_LIGHT_BLANK 4U |
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#define GPIOA_LIGHT_SCLK 5U |
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#define GPIOA_PIN6 6U |
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#define GPIOA_LIGHT_MOSI 7U |
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#define GPIOA_PIN8 8U |
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#define GPIOA_PROG_RX 9U |
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#define GPIOA_PROG_TX 10U |
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#define GPIOA_CAN_RX 11U |
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#define GPIOA_CAN_TX 12U |
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#define GPIOA_SWDIO 13U |
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#define GPIOA_SWCLK 14U |
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#define GPIOA_PIN15 15U |
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#define GPIOB_PIN0 0U |
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#define GPIOB_PIN1 1U |
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#define GPIOB_LASER_EN 2U |
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#define GPIOB_PIN3 3U |
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#define GPIOB_PIN4 4U |
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#define GPIOB_LASER_OC_N 5U |
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#define GPIOB_SYS_UART_DN 6U |
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#define GPIOB_PIN7 7U |
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#define GPIOB_WL_GDO2 8U |
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#define GPIOB_WL_GDO0 9U |
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#define GPIOB_MEM_SCL 10U |
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#define GPIOB_MEM_SDA 11U |
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#define GPIOB_WL_SS_N 12U |
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#define GPIOB_WL_SCLK 13U |
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#define GPIOB_WL_MISO 14U |
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#define GPIOB_WL_MOSI 15U |
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#define GPIOC_PIN0 0U |
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#define GPIOC_PIN1 1U |
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#define GPIOC_PIN2 2U |
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#define GPIOC_PIN3 3U |
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#define GPIOC_LIGHT_XLAT 4U |
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#define GPIOC_PIN5 5U |
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#define GPIOC_PIN6 6U |
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#define GPIOC_PIN7 7U |
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#define GPIOC_PIN8 8U |
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#define GPIOC_PIN9 9U |
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#define GPIOC_SYS_UART_RX 10U |
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#define GPIOC_SYS_UART_TX 11U |
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#define GPIOC_PIN12 12U |
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#define GPIOC_PIN13 13U |
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#define GPIOC_SYS_PD_N 14U |
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#define GPIOC_PIN15 15U |
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#define GPIOD_OSC_IN 0U |
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#define GPIOD_OSC_OUT 1U |
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#define GPIOD_SYS_INT_N 2U |
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#define GPIOD_PIN3 3U |
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#define GPIOD_PIN4 4U |
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#define GPIOD_PIN5 5U |
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#define GPIOD_PIN6 6U |
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#define GPIOD_PIN7 7U |
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#define GPIOD_PIN8 8U |
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#define GPIOD_PIN9 9U |
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#define GPIOD_PIN10 10U |
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#define GPIOD_PIN11 11U |
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#define GPIOD_PIN12 12U |
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#define GPIOD_PIN13 13U |
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#define GPIOD_PIN14 14U |
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#define GPIOD_PIN15 15U |
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#define GPIOE_PIN0 0U |
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#define GPIOE_PIN1 1U |
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#define GPIOE_PIN2 2U |
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#define GPIOE_PIN3 3U |
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#define GPIOE_PIN4 4U |
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#define GPIOE_PIN5 5U |
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#define GPIOE_PIN6 6U |
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#define GPIOE_PIN7 7U |
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#define GPIOE_PIN8 8U |
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#define GPIOE_PIN9 9U |
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#define GPIOE_PIN10 10U |
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#define GPIOE_PIN11 11U |
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#define GPIOE_PIN12 12U |
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#define GPIOE_PIN13 13U |
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#define GPIOE_PIN14 14U |
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#define GPIOE_PIN15 15U |
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#define GPIOF_PIN0 0U |
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#define GPIOF_PIN1 1U |
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#define GPIOF_PIN2 2U |
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#define GPIOF_PIN3 3U |
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#define GPIOF_PIN4 4U |
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#define GPIOF_PIN5 5U |
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#define GPIOF_PIN6 6U |
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#define GPIOF_PIN7 7U |
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#define GPIOF_PIN8 8U |
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#define GPIOF_PIN9 9U |
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#define GPIOF_PIN10 10U |
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#define GPIOF_PIN11 11U |
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#define GPIOF_PIN12 12U |
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#define GPIOF_PIN13 13U |
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#define GPIOF_PIN14 14U |
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#define GPIOF_PIN15 15U |
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#define GPIOG_PIN0 0U |
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#define GPIOG_PIN1 1U |
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#define GPIOG_PIN2 2U |
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#define GPIOG_PIN3 3U |
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#define GPIOG_PIN4 4U |
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#define GPIOG_PIN5 5U |
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#define GPIOG_PIN6 6U |
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#define GPIOG_PIN7 7U |
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#define GPIOG_PIN8 8U |
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#define GPIOG_PIN9 9U |
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#define GPIOG_PIN10 10U |
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#define GPIOG_PIN11 11U |
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#define GPIOG_PIN12 12U |
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#define GPIOG_PIN13 13U |
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#define GPIOG_PIN14 14U |
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#define GPIOG_PIN15 15U |
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/*
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* IO lines assignments.
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*/
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#define LINE_LASER_RX PAL_LINE(GPIOA, GPIOA_LASER_RX)
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#define LINE_LASER_TX PAL_LINE(GPIOA, GPIOA_LASER_TX)
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#define LINE_LIGHT_BLANK PAL_LINE(GPIOA, GPIOA_LIGHT_BLANK)
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#define LINE_LIGHT_SCLK PAL_LINE(GPIOA, GPIOA_LIGHT_SCLK)
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#define LINE_LIGHT_MOSI PAL_LINE(GPIOA, GPIOA_LIGHT_MOSI)
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#define LINE_PROG_RX PAL_LINE(GPIOA, GPIOA_PROG_RX)
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#define LINE_PROG_TX PAL_LINE(GPIOA, GPIOA_PROG_TX)
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#define LINE_CAN_RX PAL_LINE(GPIOA, GPIOA_CAN_RX)
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#define LINE_CAN_TX PAL_LINE(GPIOA, GPIOA_CAN_TX)
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#define LINE_SWDIO PAL_LINE(GPIOA, GPIOA_SWDIO)
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#define LINE_SWCLK PAL_LINE(GPIOA, GPIOA_SWCLK)
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#define LINE_LASER_EN PAL_LINE(GPIOB, GPIOB_LASER_EN)
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#define LINE_LASER_OC_N PAL_LINE(GPIOB, GPIOB_LASER_OC_N)
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#define LINE_SYS_UART_DN PAL_LINE(GPIOB, GPIOB_SYS_UART_DN)
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#define LINE_WL_GDO2 PAL_LINE(GPIOB, GPIOB_WL_GDO2)
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#define LINE_WL_GDO0 PAL_LINE(GPIOB, GPIOB_WL_GDO0)
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#define LINE_MEM_SCL PAL_LINE(GPIOB, GPIOB_MEM_SCL)
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#define LINE_MEM_SDA PAL_LINE(GPIOB, GPIOB_MEM_SDA)
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#define LINE_WL_SS_N PAL_LINE(GPIOB, GPIOB_WL_SS_N)
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#define LINE_WL_SCLK PAL_LINE(GPIOB, GPIOB_WL_SCLK)
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#define LINE_WL_MISO PAL_LINE(GPIOB, GPIOB_WL_MISO)
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#define LINE_WL_MOSI PAL_LINE(GPIOB, GPIOB_WL_MOSI)
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#define LINE_LIGHT_XLAT PAL_LINE(GPIOC, GPIOC_LIGHT_XLAT)
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#define LINE_SYS_UART_RX PAL_LINE(GPIOC, GPIOC_SYS_UART_RX)
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#define LINE_SYS_UART_TX PAL_LINE(GPIOC, GPIOC_SYS_UART_TX)
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#define LINE_SYS_PD_N PAL_LINE(GPIOC, GPIOC_SYS_PD_N)
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#define LINE_SYS_INT_N PAL_LINE(GPIOD, GPIOD_SYS_INT_N)
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/*
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* I/O ports initial setup, this configuration is established soon after reset
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* in the initialization code.
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* Please refer to the STM32 Reference Manual for details.
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*/
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#define PIN_MODE_INPUT 0U |
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#define PIN_MODE_OUTPUT_2M 2U |
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#define PIN_MODE_OUTPUT_10M 1U |
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#define PIN_MODE_OUTPUT_50M 3U |
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#define PIN_CNF_INPUT_ANALOG 0U |
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#define PIN_CNF_INPUT_FLOATING 1U |
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#define PIN_CNF_INPUT_PULLX 2U |
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#define PIN_CNF_OUTPUT_PUSHPULL 0U |
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#define PIN_CNF_OUTPUT_OPENDRAIN 1U |
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#define PIN_CNF_ALTERNATE_PUSHPULL 2U |
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#define PIN_CNF_ALTERNATE_OPENDRAIN 3U |
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#define PIN_CR(pin, mode, cnf) (((mode) | ((cnf) << 2U)) << (((pin) % 8U) * 4U)) |
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#define PIN_ODR_LOW(n) (0U << (n)) |
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#define PIN_ODR_HIGH(n) (1U << (n)) |
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/*
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* GPIOA setup:
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*
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* PA0 - PIN0 (input floating)
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* PA1 - PIN1 (input floating)
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* PA2 - LASER_RX (alternate pushpull high 50MHz)
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* PA3 - LASER_TX (input pullup)
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* PA4 - LIGHT_BLANK (output pushpull high 50MHz)
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* PA5 - LIGHT_SCLK (alternate pushpull 50MHz)
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* PA6 - PIN6 (input foating)
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* PA7 - LIGHT_MOSI (alternate pushpull 50MHz)
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* PA8 - PIN8 (input floating)
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* PA9 - PROG_RX (alternate pushpull 50MHz)
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* PA10 - PROG_TX (input pullup)
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* PA11 - CAN_RX (input floating)
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* PA12 - CAN_TX (alternate pushpull 50MHz)
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* PA13 - SWDIO (input pullup)
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* PA14 - SWCLK (input pullup)
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* PA15 - PIN15 (input floating)
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*/
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#define VAL_GPIOACRL (PIN_CR(GPIOA_PIN0, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \
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PIN_CR(GPIOA_PIN1, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
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PIN_CR(GPIOA_LASER_RX, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_PUSHPULL) | \ |
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PIN_CR(GPIOA_LASER_TX, PIN_MODE_INPUT, PIN_CNF_INPUT_PULLX) | \ |
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PIN_CR(GPIOA_LIGHT_BLANK, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_PUSHPULL) | \ |
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PIN_CR(GPIOA_LIGHT_SCLK, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_PUSHPULL) | \ |
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PIN_CR(GPIOA_PIN6, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
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PIN_CR(GPIOA_LIGHT_MOSI, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_PUSHPULL)) |
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#define VAL_GPIOACRH (PIN_CR(GPIOA_PIN8, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \
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PIN_CR(GPIOA_PROG_RX, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_PUSHPULL) | \ |
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PIN_CR(GPIOA_PROG_TX, PIN_MODE_INPUT, PIN_CNF_INPUT_PULLX) | \ |
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PIN_CR(GPIOA_CAN_RX, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
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PIN_CR(GPIOA_CAN_TX, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_PUSHPULL) | \ |
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PIN_CR(GPIOA_SWDIO, PIN_MODE_INPUT, PIN_CNF_INPUT_PULLX) | \ |
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PIN_CR(GPIOA_SWCLK, PIN_MODE_INPUT, PIN_CNF_INPUT_PULLX) | \ |
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PIN_CR(GPIOA_PIN15, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING)) |
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#define VAL_GPIOAODR (PIN_ODR_LOW(GPIOA_PIN0) | \
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PIN_ODR_LOW(GPIOA_PIN1) | \ |
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PIN_ODR_HIGH(GPIOA_LASER_RX) | \ |
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PIN_ODR_HIGH(GPIOA_LASER_TX) | \ |
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PIN_ODR_HIGH(GPIOA_LIGHT_BLANK) | \ |
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PIN_ODR_HIGH(GPIOA_LIGHT_SCLK) | \ |
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PIN_ODR_LOW(GPIOA_PIN6) | \ |
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PIN_ODR_HIGH(GPIOA_LIGHT_MOSI) | \ |
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PIN_ODR_LOW(GPIOA_PIN8) | \ |
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PIN_ODR_HIGH(GPIOA_PROG_RX) | \ |
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PIN_ODR_HIGH(GPIOA_PROG_TX) | \ |
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PIN_ODR_HIGH(GPIOA_CAN_RX) | \ |
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PIN_ODR_HIGH(GPIOA_CAN_TX) | \ |
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PIN_ODR_HIGH(GPIOA_SWDIO) | \ |
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PIN_ODR_HIGH(GPIOA_SWCLK) | \ |
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PIN_ODR_LOW(GPIOA_PIN15)) |
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/*
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* GPIOB setup:
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*
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* PB0 - PIN0 (input floating)
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* PB1 - PIN1 (input floating)
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* PB2 - LASER_EN (output pushpull low 50MHz)
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* PB3 - PIN3 (input floating)
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* PB4 - PIN4 (input floating)
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* PB5 - LASER_OC_N (input floating)
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* PB6 - SYS_UART_DN (output opendrain high 50MHz)
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* PB7 - PIN7 (input foating)
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* PB8 - WL_GDO2 (input pullup)
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* PB9 - WL_GDO0 (input pullup)
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* PB10 - MEM_SCL (alternate opendrain 50MHz)
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* PB11 - MEM_SDA (alternate opendrain 50MHz)
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* PB12 - WL_SS_N (output pushpull high 50MHz)
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* PB13 - WL_SCLK (alternate pushpull 50MHz)
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* PB14 - WL_MISO (input pullup)
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* PB15 - WL_MOSI (alternate pushpull 50MHz)
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*/
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#define VAL_GPIOBCRL (PIN_CR(GPIOB_PIN0, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \
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PIN_CR(GPIOB_PIN1, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
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PIN_CR(GPIOB_LASER_EN, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_PUSHPULL) | \ |
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PIN_CR(GPIOB_PIN3, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
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PIN_CR(GPIOB_PIN4, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
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PIN_CR(GPIOB_LASER_OC_N, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
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PIN_CR(GPIOB_SYS_UART_DN, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_OPENDRAIN) | \ |
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PIN_CR(GPIOB_PIN7, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING)) |
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#define VAL_GPIOBCRH (PIN_CR(GPIOB_WL_GDO2, PIN_MODE_INPUT, PIN_CNF_INPUT_PULLX) | \
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PIN_CR(GPIOB_WL_GDO0, PIN_MODE_INPUT, PIN_CNF_INPUT_PULLX) | \ |
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PIN_CR(GPIOB_MEM_SCL, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_OPENDRAIN) | \ |
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PIN_CR(GPIOB_MEM_SDA, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_OPENDRAIN) | \ |
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PIN_CR(GPIOB_WL_SS_N, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_PUSHPULL) | \ |
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PIN_CR(GPIOB_WL_SCLK, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_PUSHPULL) | \ |
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PIN_CR(GPIOB_WL_MISO, PIN_MODE_INPUT, PIN_CNF_INPUT_PULLX) | \ |
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PIN_CR(GPIOB_WL_MOSI, PIN_MODE_OUTPUT_50M, PIN_CNF_ALTERNATE_PUSHPULL)) |
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#define VAL_GPIOBODR (PIN_ODR_LOW(GPIOB_PIN0) | \
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PIN_ODR_LOW(GPIOB_PIN1) | \ |
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PIN_ODR_LOW(GPIOB_LASER_EN) | \ |
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PIN_ODR_LOW(GPIOB_PIN3) | \ |
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PIN_ODR_LOW(GPIOB_PIN4) | \ |
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PIN_ODR_HIGH(GPIOB_LASER_OC_N) | \ |
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PIN_ODR_HIGH(GPIOB_SYS_UART_DN) | \ |
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PIN_ODR_LOW(GPIOB_PIN7) | \ |
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PIN_ODR_HIGH(GPIOB_WL_GDO2) | \ |
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PIN_ODR_HIGH(GPIOB_WL_GDO0) | \ |
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PIN_ODR_HIGH(GPIOB_MEM_SCL) | \ |
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PIN_ODR_HIGH(GPIOB_MEM_SDA) | \ |
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PIN_ODR_HIGH(GPIOB_WL_SS_N) | \ |
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PIN_ODR_HIGH(GPIOB_WL_SCLK) | \ |
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PIN_ODR_HIGH(GPIOB_WL_MISO) | \ |
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PIN_ODR_HIGH(GPIOB_WL_MOSI)) |
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/*
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* GPIOC setup:
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*
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* PC0 - PIN0 (input floating)
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* PC1 - PIN1 (input floating)
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* PC2 - PIN2 (input floating)
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* PC3 - PIN3 (input floating)
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* PC4 - LIGHT_XLAT (output pushpull high 10MHz)
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* PC5 - PIN5 (input floating)
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* PC6 - PIN6 (input floating)
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* PC7 - PIN7 (input floating)
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* PC8 - PIN8 (input floating)
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* PC9 - PIN9 (input floating)
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* PC10 - SYS_UART_RX (input pullup)
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* PC11 - SYS_UART_TX (input pullup)
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* PC12 - PIN12 (input floating)
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* PC13 - PIN13 (input floating)
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* PC14 - SYS_PD_N (output opendrain high 50MHz)
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* PC15 - PIN15 (input floating)
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*/
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#define VAL_GPIOCCRL (PIN_CR(GPIOC_PIN0, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \
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PIN_CR(GPIOC_PIN1, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
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PIN_CR(GPIOC_PIN2, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
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PIN_CR(GPIOC_PIN3, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
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PIN_CR(GPIOC_LIGHT_XLAT, PIN_MODE_OUTPUT_10M, PIN_CNF_OUTPUT_PUSHPULL) | \ |
| 371 |
PIN_CR(GPIOC_PIN5, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 372 |
PIN_CR(GPIOC_PIN6, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 373 |
PIN_CR(GPIOC_PIN7, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING)) |
| 374 |
#define VAL_GPIOCCRH (PIN_CR(GPIOC_PIN8, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \
|
| 375 |
PIN_CR(GPIOC_PIN9, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 376 |
PIN_CR(GPIOC_SYS_UART_RX, PIN_MODE_INPUT, PIN_CNF_INPUT_PULLX) | \ |
| 377 |
PIN_CR(GPIOC_SYS_UART_TX, PIN_MODE_INPUT, PIN_CNF_INPUT_PULLX) | \ |
| 378 |
PIN_CR(GPIOC_PIN12, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 379 |
PIN_CR(GPIOC_PIN13, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 380 |
PIN_CR(GPIOC_SYS_PD_N, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_OPENDRAIN) | \ |
| 381 |
PIN_CR(GPIOC_PIN15, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING)) |
| 382 |
#define VAL_GPIOCODR (PIN_ODR_LOW(GPIOC_PIN0) | \
|
| 383 |
PIN_ODR_LOW(GPIOC_PIN1) | \ |
| 384 |
PIN_ODR_LOW(GPIOC_PIN2) | \ |
| 385 |
PIN_ODR_LOW(GPIOC_PIN3) | \ |
| 386 |
PIN_ODR_LOW(GPIOC_LIGHT_XLAT) | \ |
| 387 |
PIN_ODR_LOW(GPIOC_PIN5) | \ |
| 388 |
PIN_ODR_LOW(GPIOC_PIN6) | \ |
| 389 |
PIN_ODR_LOW(GPIOC_PIN7) | \ |
| 390 |
PIN_ODR_LOW(GPIOC_PIN8) | \ |
| 391 |
PIN_ODR_LOW(GPIOC_PIN9) | \ |
| 392 |
PIN_ODR_HIGH(GPIOC_SYS_UART_RX) | \ |
| 393 |
PIN_ODR_HIGH(GPIOC_SYS_UART_TX) | \ |
| 394 |
PIN_ODR_LOW(GPIOC_PIN12) | \ |
| 395 |
PIN_ODR_LOW(GPIOC_PIN13) | \ |
| 396 |
PIN_ODR_HIGH(GPIOC_SYS_PD_N) | \ |
| 397 |
PIN_ODR_LOW(GPIOC_PIN15)) |
| 398 |
|
| 399 |
/*
|
| 400 |
* GPIOD setup:
|
| 401 |
*
|
| 402 |
* PD0 - OSC_IN (input floating)
|
| 403 |
* PD1 - OSC_OUT (input floating)
|
| 404 |
* PD2 - SYS_INT_N (output opendrain low 50MHz)
|
| 405 |
* PD3 - PIN3 (input floating)
|
| 406 |
* PD4 - PIN4 (input floating)
|
| 407 |
* PD5 - PIN5 (input floating)
|
| 408 |
* PD6 - PIN6 (input floating)
|
| 409 |
* PD7 - PIN7 (input floating)
|
| 410 |
* PD8 - PIN8 (input floating)
|
| 411 |
* PD9 - PIN9 (input floating)
|
| 412 |
* PD10 - PIN10 (input floating)
|
| 413 |
* PD11 - PIN11 (input floating)
|
| 414 |
* PD12 - PIN12 (input floating)
|
| 415 |
* PD13 - PIN13 (input floating)
|
| 416 |
* PD14 - PIN14 (input floating)
|
| 417 |
* PD15 - PIN15 (input floating)
|
| 418 |
*/
|
| 419 |
#define VAL_GPIODCRL (PIN_CR(GPIOD_OSC_IN, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \
|
| 420 |
PIN_CR(GPIOD_OSC_OUT, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 421 |
PIN_CR(GPIOD_SYS_INT_N, PIN_MODE_OUTPUT_50M, PIN_CNF_OUTPUT_OPENDRAIN) | \ |
| 422 |
PIN_CR(GPIOD_PIN3, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 423 |
PIN_CR(GPIOD_PIN4, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 424 |
PIN_CR(GPIOD_PIN5, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 425 |
PIN_CR(GPIOD_PIN6, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 426 |
PIN_CR(GPIOD_PIN7, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING)) |
| 427 |
#define VAL_GPIODCRH (PIN_CR(GPIOD_PIN8, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \
|
| 428 |
PIN_CR(GPIOD_PIN9, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 429 |
PIN_CR(GPIOD_PIN10, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 430 |
PIN_CR(GPIOD_PIN11, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 431 |
PIN_CR(GPIOD_PIN12, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 432 |
PIN_CR(GPIOD_PIN13, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 433 |
PIN_CR(GPIOD_PIN14, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 434 |
PIN_CR(GPIOD_PIN15, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING)) |
| 435 |
#define VAL_GPIODODR (PIN_ODR_HIGH(GPIOD_OSC_IN) | \
|
| 436 |
PIN_ODR_HIGH(GPIOD_OSC_OUT) | \ |
| 437 |
PIN_ODR_LOW(GPIOD_SYS_INT_N) | \ |
| 438 |
PIN_ODR_LOW(GPIOD_PIN3) | \ |
| 439 |
PIN_ODR_LOW(GPIOD_PIN4) | \ |
| 440 |
PIN_ODR_LOW(GPIOD_PIN5) | \ |
| 441 |
PIN_ODR_LOW(GPIOD_PIN6) | \ |
| 442 |
PIN_ODR_LOW(GPIOD_PIN7) | \ |
| 443 |
PIN_ODR_LOW(GPIOD_PIN8) | \ |
| 444 |
PIN_ODR_LOW(GPIOD_PIN9) | \ |
| 445 |
PIN_ODR_LOW(GPIOD_PIN10) | \ |
| 446 |
PIN_ODR_LOW(GPIOD_PIN11) | \ |
| 447 |
PIN_ODR_LOW(GPIOD_PIN12) | \ |
| 448 |
PIN_ODR_LOW(GPIOD_PIN13) | \ |
| 449 |
PIN_ODR_LOW(GPIOD_PIN14) | \ |
| 450 |
PIN_ODR_LOW(GPIOD_PIN15)) |
| 451 |
|
| 452 |
/*
|
| 453 |
* GPIOE setup:
|
| 454 |
*
|
| 455 |
* PE0 - PIN0 (input floating)
|
| 456 |
* PE1 - PIN1 (input floating)
|
| 457 |
* PE2 - PIN2 (input floating)
|
| 458 |
* PE3 - PIN3 (input floating)
|
| 459 |
* PE4 - PIN4 (input floating)
|
| 460 |
* PE5 - PIN5 (input floating)
|
| 461 |
* PE6 - PIN6 (input floating)
|
| 462 |
* PE7 - PIN7 (input floating)
|
| 463 |
* PE8 - PIN8 (input floating)
|
| 464 |
* PE9 - PIN9 (input floating)
|
| 465 |
* PE10 - PIN10 (input floating)
|
| 466 |
* PE11 - PIN11 (input floating)
|
| 467 |
* PE12 - PIN12 (input floating)
|
| 468 |
* PE13 - PIN13 (input floating)
|
| 469 |
* PE14 - PIN14 (input floating)
|
| 470 |
* PE15 - PIN15 (input floating)
|
| 471 |
*/
|
| 472 |
#define VAL_GPIOECRL (PIN_CR(GPIOE_PIN0, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \
|
| 473 |
PIN_CR(GPIOE_PIN1, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 474 |
PIN_CR(GPIOE_PIN2, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 475 |
PIN_CR(GPIOE_PIN3, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 476 |
PIN_CR(GPIOE_PIN4, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 477 |
PIN_CR(GPIOE_PIN5, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 478 |
PIN_CR(GPIOE_PIN6, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 479 |
PIN_CR(GPIOE_PIN7, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING)) |
| 480 |
#define VAL_GPIOECRH (PIN_CR(GPIOE_PIN8, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \
|
| 481 |
PIN_CR(GPIOE_PIN9, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 482 |
PIN_CR(GPIOE_PIN10, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 483 |
PIN_CR(GPIOE_PIN11, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 484 |
PIN_CR(GPIOE_PIN12, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 485 |
PIN_CR(GPIOE_PIN13, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 486 |
PIN_CR(GPIOE_PIN14, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 487 |
PIN_CR(GPIOE_PIN15, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING)) |
| 488 |
#define VAL_GPIOEODR (PIN_ODR_LOW(GPIOE_PIN0) | \
|
| 489 |
PIN_ODR_LOW(GPIOE_PIN1) | \ |
| 490 |
PIN_ODR_LOW(GPIOE_PIN2) | \ |
| 491 |
PIN_ODR_LOW(GPIOE_PIN3) | \ |
| 492 |
PIN_ODR_LOW(GPIOE_PIN4) | \ |
| 493 |
PIN_ODR_LOW(GPIOE_PIN5) | \ |
| 494 |
PIN_ODR_LOW(GPIOE_PIN6) | \ |
| 495 |
PIN_ODR_LOW(GPIOE_PIN7) | \ |
| 496 |
PIN_ODR_LOW(GPIOE_PIN8) | \ |
| 497 |
PIN_ODR_LOW(GPIOE_PIN9) | \ |
| 498 |
PIN_ODR_LOW(GPIOE_PIN10) | \ |
| 499 |
PIN_ODR_LOW(GPIOE_PIN11) | \ |
| 500 |
PIN_ODR_LOW(GPIOE_PIN12) | \ |
| 501 |
PIN_ODR_LOW(GPIOE_PIN13) | \ |
| 502 |
PIN_ODR_LOW(GPIOE_PIN14) | \ |
| 503 |
PIN_ODR_LOW(GPIOE_PIN15)) |
| 504 |
|
| 505 |
/*
|
| 506 |
* GPIOF setup:
|
| 507 |
*
|
| 508 |
* PF0 - PIN0 (input floating)
|
| 509 |
* PF1 - PIN1 (input floating)
|
| 510 |
* PF2 - PIN2 (input floating)
|
| 511 |
* PF3 - PIN3 (input floating)
|
| 512 |
* PF4 - PIN4 (input floating)
|
| 513 |
* PF5 - PIN5 (input floating)
|
| 514 |
* PF6 - PIN6 (input floating)
|
| 515 |
* PF7 - PIN7 (input floating)
|
| 516 |
* PF8 - PIN8 (input floating)
|
| 517 |
* PF9 - PIN9 (input floating)
|
| 518 |
* PF10 - PIN10 (input floating)
|
| 519 |
* PF11 - PIN11 (input floating)
|
| 520 |
* PF12 - PIN12 (input floating)
|
| 521 |
* PF13 - PIN13 (input floating)
|
| 522 |
* PF14 - PIN14 (input floating)
|
| 523 |
* PF15 - PIN15 (input floating)
|
| 524 |
*/
|
| 525 |
#define VAL_GPIOFCRL (PIN_CR(GPIOF_PIN0, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \
|
| 526 |
PIN_CR(GPIOF_PIN1, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 527 |
PIN_CR(GPIOF_PIN2, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 528 |
PIN_CR(GPIOF_PIN3, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 529 |
PIN_CR(GPIOF_PIN4, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 530 |
PIN_CR(GPIOF_PIN5, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 531 |
PIN_CR(GPIOF_PIN6, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 532 |
PIN_CR(GPIOF_PIN7, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING)) |
| 533 |
#define VAL_GPIOFCRH (PIN_CR(GPIOF_PIN8, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \
|
| 534 |
PIN_CR(GPIOF_PIN9, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 535 |
PIN_CR(GPIOF_PIN10, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 536 |
PIN_CR(GPIOF_PIN11, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 537 |
PIN_CR(GPIOF_PIN12, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 538 |
PIN_CR(GPIOF_PIN13, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 539 |
PIN_CR(GPIOF_PIN14, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 540 |
PIN_CR(GPIOF_PIN15, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING)) |
| 541 |
#define VAL_GPIOFODR (PIN_ODR_LOW(GPIOF_PIN0) | \
|
| 542 |
PIN_ODR_LOW(GPIOF_PIN1) | \ |
| 543 |
PIN_ODR_LOW(GPIOF_PIN2) | \ |
| 544 |
PIN_ODR_LOW(GPIOF_PIN3) | \ |
| 545 |
PIN_ODR_LOW(GPIOF_PIN4) | \ |
| 546 |
PIN_ODR_LOW(GPIOF_PIN5) | \ |
| 547 |
PIN_ODR_LOW(GPIOF_PIN6) | \ |
| 548 |
PIN_ODR_LOW(GPIOF_PIN7) | \ |
| 549 |
PIN_ODR_LOW(GPIOF_PIN8) | \ |
| 550 |
PIN_ODR_LOW(GPIOF_PIN9) | \ |
| 551 |
PIN_ODR_LOW(GPIOF_PIN10) | \ |
| 552 |
PIN_ODR_LOW(GPIOF_PIN11) | \ |
| 553 |
PIN_ODR_LOW(GPIOF_PIN12) | \ |
| 554 |
PIN_ODR_LOW(GPIOF_PIN13) | \ |
| 555 |
PIN_ODR_LOW(GPIOF_PIN14) | \ |
| 556 |
PIN_ODR_LOW(GPIOF_PIN15)) |
| 557 |
|
| 558 |
/*
|
| 559 |
* GPIOG setup:
|
| 560 |
*
|
| 561 |
* PG0 - PIN0 (input floating)
|
| 562 |
* PG1 - PIN1 (input floating)
|
| 563 |
* PG2 - PIN2 (input floating)
|
| 564 |
* PG3 - PIN3 (input floating)
|
| 565 |
* PG4 - PIN4 (input floating)
|
| 566 |
* PG5 - PIN5 (input floating)
|
| 567 |
* PG6 - PIN6 (input floating)
|
| 568 |
* PG7 - PIN7 (input floating)
|
| 569 |
* PG8 - PIN8 (input floating)
|
| 570 |
* PG9 - PIN9 (input floating)
|
| 571 |
* PG10 - PIN10 (input floating)
|
| 572 |
* PG11 - PIN11 (input floating)
|
| 573 |
* PG12 - PIN12 (input floating)
|
| 574 |
* PG13 - PIN13 (input floating)
|
| 575 |
* PG14 - PIN14 (input floating)
|
| 576 |
* PG15 - PIN15 (input floating)
|
| 577 |
*/
|
| 578 |
#define VAL_GPIOGCRL (PIN_CR(GPIOG_PIN0, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \
|
| 579 |
PIN_CR(GPIOG_PIN1, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 580 |
PIN_CR(GPIOG_PIN2, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 581 |
PIN_CR(GPIOG_PIN3, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 582 |
PIN_CR(GPIOG_PIN4, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 583 |
PIN_CR(GPIOG_PIN5, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 584 |
PIN_CR(GPIOG_PIN6, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 585 |
PIN_CR(GPIOG_PIN7, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING)) |
| 586 |
#define VAL_GPIOGCRH (PIN_CR(GPIOG_PIN8, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \
|
| 587 |
PIN_CR(GPIOG_PIN9, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 588 |
PIN_CR(GPIOG_PIN10, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 589 |
PIN_CR(GPIOG_PIN11, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 590 |
PIN_CR(GPIOG_PIN12, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 591 |
PIN_CR(GPIOG_PIN13, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 592 |
PIN_CR(GPIOG_PIN14, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING) | \ |
| 593 |
PIN_CR(GPIOG_PIN15, PIN_MODE_INPUT, PIN_CNF_INPUT_FLOATING)) |
| 594 |
#define VAL_GPIOGODR (PIN_ODR_LOW(GPIOG_PIN0) | \
|
| 595 |
PIN_ODR_LOW(GPIOG_PIN1) | \ |
| 596 |
PIN_ODR_LOW(GPIOG_PIN2) | \ |
| 597 |
PIN_ODR_LOW(GPIOG_PIN3) | \ |
| 598 |
PIN_ODR_LOW(GPIOG_PIN4) | \ |
| 599 |
PIN_ODR_LOW(GPIOG_PIN5) | \ |
| 600 |
PIN_ODR_LOW(GPIOG_PIN6) | \ |
| 601 |
PIN_ODR_LOW(GPIOG_PIN7) | \ |
| 602 |
PIN_ODR_LOW(GPIOG_PIN8) | \ |
| 603 |
PIN_ODR_LOW(GPIOG_PIN9) | \ |
| 604 |
PIN_ODR_LOW(GPIOG_PIN10) | \ |
| 605 |
PIN_ODR_LOW(GPIOG_PIN11) | \ |
| 606 |
PIN_ODR_LOW(GPIOG_PIN12) | \ |
| 607 |
PIN_ODR_LOW(GPIOG_PIN13) | \ |
| 608 |
PIN_ODR_LOW(GPIOG_PIN14) | \ |
| 609 |
PIN_ODR_LOW(GPIOG_PIN15)) |
| 610 |
|
| 611 |
#if !defined(_FROM_ASM_)
|
| 612 |
#ifdef __cplusplus
|
| 613 |
extern "C" { |
| 614 |
#endif
|
| 615 |
void boardInit(void); |
| 616 |
#ifdef __cplusplus
|
| 617 |
} |
| 618 |
#endif
|
| 619 |
#endif /* _FROM_ASM_ */ |
| 620 |
|
| 621 |
#endif /* _BOARD_H_ */ |
| 622 |
|
| 623 |
/** @} */
|