amiro-os / hal / platforms / STM32 / qei_lld.c @ 58fe0e0b
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1 | 58fe0e0b | Thomas Schöpping | #include "ch.h" |
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2 | #include "hal.h" |
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3 | |||
4 | #include "qei.h" |
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5 | |||
6 | #if HAL_USE_QEI || defined(__DOXYGEN__)
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7 | |||
8 | /*===========================================================================*/
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9 | /* Driver exported variables. */
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10 | /*===========================================================================*/
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11 | |||
12 | /**
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13 | * @brief QEID1 driver identifier.
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14 | * @note The driver QEID1 allocates the complex timer TIM1 when enabled.
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15 | */
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16 | #if STM32_QEI_USE_TIM1 || defined(__DOXYGEN__)
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17 | QEIDriver QEID1; |
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18 | #endif
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19 | |||
20 | /**
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21 | * @brief QEID2 driver identifier.
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22 | * @note The driver QEID1 allocates the timer TIM2 when enabled.
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23 | */
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24 | #if STM32_QEI_USE_TIM2 || defined(__DOXYGEN__)
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25 | QEIDriver QEID2; |
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26 | #endif
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27 | |||
28 | /**
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29 | * @brief QEID3 driver identifier.
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30 | * @note The driver QEID1 allocates the timer TIM3 when enabled.
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31 | */
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32 | #if STM32_QEI_USE_TIM3 || defined(__DOXYGEN__)
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33 | QEIDriver QEID3; |
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34 | #endif
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35 | |||
36 | /**
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37 | * @brief QEID4 driver identifier.
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38 | * @note The driver QEID4 allocates the timer TIM4 when enabled.
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39 | */
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40 | #if STM32_QEI_USE_TIM4 || defined(__DOXYGEN__)
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41 | QEIDriver QEID4; |
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42 | #endif
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43 | |||
44 | /**
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45 | * @brief QEID5 driver identifier.
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46 | * @note The driver QEID5 allocates the timer TIM5 when enabled.
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47 | */
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48 | #if STM32_QEI_USE_TIM5 || defined(__DOXYGEN__)
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49 | QEIDriver QEID5; |
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50 | #endif
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51 | |||
52 | /**
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53 | * @brief QEID8 driver identifier.
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54 | * @note The driver QEID8 allocates the timer TIM8 when enabled.
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55 | */
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56 | #if STM32_QEI_USE_TIM8 || defined(__DOXYGEN__)
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57 | QEIDriver QEID8; |
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58 | #endif
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59 | |||
60 | /*===========================================================================*/
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61 | /* Driver local variables. */
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62 | /*===========================================================================*/
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63 | |||
64 | /*===========================================================================*/
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65 | /* Driver local functions. */
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66 | /*===========================================================================*/
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67 | |||
68 | /*===========================================================================*/
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69 | /* Driver interrupt handlers. */
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70 | /*===========================================================================*/
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71 | |||
72 | /*===========================================================================*/
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73 | /* Driver exported functions. */
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74 | /*===========================================================================*/
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75 | |||
76 | /**
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77 | * @brief Low level QEI driver initialization.
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78 | *
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79 | * @notapi
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80 | */
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81 | void qei_lld_init(void) { |
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82 | |||
83 | #if STM32_QEI_USE_TIM1
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84 | /* Driver initialization.*/
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85 | qeiObjectInit(&QEID1); |
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86 | QEID1.tim = STM32_TIM1; |
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87 | #endif
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88 | |||
89 | #if STM32_QEI_USE_TIM2
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90 | /* Driver initialization.*/
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91 | qeiObjectInit(&QEID2); |
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92 | QEID2.tim = STM32_TIM2; |
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93 | #endif
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94 | |||
95 | #if STM32_QEI_USE_TIM3
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96 | /* Driver initialization.*/
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97 | qeiObjectInit(&QEID3); |
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98 | QEID3.tim = STM32_TIM3; |
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99 | #endif
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100 | |||
101 | #if STM32_QEI_USE_TIM4
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102 | /* Driver initialization.*/
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103 | qeiObjectInit(&QEID4); |
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104 | QEID4.tim = STM32_TIM4; |
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105 | #endif
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106 | |||
107 | #if STM32_QEI_USE_TIM5
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108 | /* Driver initialization.*/
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109 | qeiObjectInit(&QEID5); |
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110 | QEID5.tim = STM32_TIM5; |
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111 | #endif
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112 | |||
113 | #if STM32_QEI_USE_TIM8
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114 | /* Driver initialization.*/
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115 | qeiObjectInit(&QEID8); |
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116 | QEID8.tim = STM32_TIM8; |
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117 | #endif
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118 | } |
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119 | |||
120 | /**
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121 | * @brief Configures and activates the QEI peripheral.
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122 | *
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123 | * @param[in] qeip pointer to the @p QEIDriver object
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124 | *
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125 | * @notapi
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126 | */
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127 | void qei_lld_start(QEIDriver *qeip) {
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128 | uint32_t arr, ccer; |
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129 | |||
130 | if (qeip->state == QEI_STOP) {
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131 | /* Clock activation and timer reset.*/
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132 | #if STM32_QEI_USE_TIM1
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133 | if (&QEID1 == qeip) {
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134 | rccEnableTIM1(FALSE); |
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135 | rccResetTIM1(); |
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136 | } |
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137 | #endif
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138 | #if STM32_QEI_USE_TIM2
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139 | if (&QEID2 == qeip) {
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140 | rccEnableTIM2(FALSE); |
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141 | rccResetTIM2(); |
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142 | } |
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143 | #endif
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144 | #if STM32_QEI_USE_TIM3
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145 | if (&QEID3 == qeip) {
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146 | rccEnableTIM3(FALSE); |
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147 | rccResetTIM3(); |
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148 | } |
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149 | #endif
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150 | #if STM32_QEI_USE_TIM4
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151 | if (&QEID4 == qeip) {
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152 | rccEnableTIM4(FALSE); |
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153 | rccResetTIM4(); |
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154 | } |
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155 | #endif
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156 | |||
157 | #if STM32_QEI_USE_TIM5
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158 | if (&QEID5 == qeip) {
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159 | rccEnableTIM5(FALSE); |
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160 | rccResetTIM5(); |
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161 | } |
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162 | #endif
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163 | #if STM32_QEI_USE_TIM8
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164 | if (&QEID8 == qeip) {
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165 | rccEnableTIM8(FALSE); |
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166 | rccResetTIM8(); |
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167 | } |
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168 | #endif
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169 | } |
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170 | else {
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171 | /* Driver re-configuration scenario, it must be stopped first.*/
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172 | qeip->tim->CR1 = 0; /* Timer disabled. */ |
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173 | qeip->tim->DIER = 0; /* All IRQs disabled. */ |
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174 | qeip->tim->SR = 0; /* Clear eventual pending IRQs. */ |
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175 | qeip->tim->CCR[0] = 0; /* Comparator 1 disabled. */ |
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176 | qeip->tim->CCR[1] = 0; /* Comparator 2 disabled. */ |
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177 | qeip->tim->CNT = 0; /* Counter reset to zero. */ |
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178 | } |
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179 | |||
180 | /* Timer configuration.*/
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181 | qeip->tim->PSC = 0;
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182 | arr = qeip->config->range - 1;
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183 | chDbgAssert((arr <= 0xFFFF), "qei_lld_start(), #1", "invalid range"); |
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184 | qeip->tim->ARR = arr & 0xFFFF;
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185 | |||
186 | /* CCMR1_CC1S = 01 - CH1 Input on TI1.
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187 | CCMR1_CC2S = 01 - CH2 Input on TI2.*/
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188 | qeip->tim->CCMR1 = TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0; |
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189 | |||
190 | ccer = 0;
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191 | if (qeip->config->channels[0].mode == QEI_INPUT_INVERTED) |
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192 | ccer |= TIM_CCER_CC1P; |
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193 | if (qeip->config->channels[1].mode == QEI_INPUT_INVERTED) |
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194 | ccer |= TIM_CCER_CC2P; |
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195 | qeip->tim->CCER = ccer; |
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196 | |||
197 | if (qeip->config->mode == QEI_COUNT_CH1)
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198 | qeip->tim->SMCR = TIM_SMCR_SMS_1; |
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199 | else if (qeip->config->mode == QEI_COUNT_CH2) |
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200 | qeip->tim->SMCR = TIM_SMCR_SMS_0; |
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201 | else
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202 | qeip->tim->SMCR = TIM_SMCR_SMS_0 | TIM_SMCR_SMS_1; |
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203 | } |
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204 | |||
205 | /**
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206 | * @brief Deactivates the QEI peripheral.
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207 | *
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208 | * @param[in] qeip pointer to the @p QEIDriver object
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209 | *
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210 | * @notapi
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211 | */
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212 | void qei_lld_stop(QEIDriver *qeip) {
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213 | |||
214 | if (qeip->state == QEI_READY) {
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215 | /* Clock deactivation.*/
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216 | qeip->tim->CR1 = 0; /* Timer disabled. */ |
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217 | |||
218 | #if STM32_QEI_USE_TIM1
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219 | if (&QEID1 == qeip) {
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220 | rccDisableTIM1(FALSE); |
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221 | } |
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222 | #endif
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223 | #if STM32_QEI_USE_TIM2
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224 | if (&QEID2 == qeip) {
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225 | rccDisableTIM2(FALSE); |
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226 | } |
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227 | #endif
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228 | #if STM32_QEI_USE_TIM3
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229 | if (&QEID3 == qeip) {
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230 | rccDisableTIM3(FALSE); |
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231 | } |
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232 | #endif
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233 | #if STM32_QEI_USE_TIM4
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234 | if (&QEID4 == qeip) {
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235 | rccDisableTIM4(FALSE); |
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236 | } |
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237 | #endif
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238 | #if STM32_QEI_USE_TIM5
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239 | if (&QEID5 == qeip) {
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240 | rccDisableTIM5(FALSE); |
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241 | } |
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242 | #endif
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243 | } |
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244 | #if STM32_QEI_USE_TIM8
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245 | if (&QEID8 == qeip) {
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246 | rccDisableTIM8(FALSE); |
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247 | } |
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248 | #endif
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249 | } |
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250 | |||
251 | /**
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252 | * @brief Enables the quadrature encoder.
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253 | *
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254 | * @param[in] qeip pointer to the @p QEIDriver object
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255 | *
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256 | * @notapi
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257 | */
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258 | void qei_lld_enable(QEIDriver *qeip) {
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259 | |||
260 | qeip->tim->CR1 = TIM_CR1_CEN; |
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261 | } |
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262 | |||
263 | /**
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264 | * @brief Disables the quadrature encoder.
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265 | *
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266 | * @param[in] qeip pointer to the @p QEIDriver object
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267 | *
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268 | * @notapi
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269 | */
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270 | void qei_lld_disable(QEIDriver *qeip) {
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271 | |||
272 | qeip->tim->CR1 = 0;
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273 | } |
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274 | |||
275 | #endif /* HAL_USE_QEI */ |