amiro-os / unittests / periphery-lld / src / ut_alld_l3g4200d.c @ 84f0ce9e
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/*
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AMiRo-OS is an operating system designed for the Autonomous Mini Robot (AMiRo) platform.
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Copyright (C) 2016..2019 Thomas Schöpping et al.
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <ut_alld_l3g4200d.h> |
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#if ((AMIROOS_CFG_TESTS_ENABLE == true) && defined(AMIROLLD_CFG_USE_L3G4200D)) || defined(__DOXYGEN__) |
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#include <aos_debug.h> |
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#include <chprintf.h> |
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#include <aos_thread.h> |
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#include <alld_l3g4200d.h> |
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/**
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* @brief L3G4200D unit test function.
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*
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* @param[in] stream Stream for input/output.
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* @param[in] ut Unit test object.
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*
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* @return Unit test result value.
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*/
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aos_utresult_t utAlldL3g4200dFunc(BaseSequentialStream* stream, aos_unittest_t* ut) |
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{
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aosDbgCheck(ut->data != NULL && ((ut_l3g4200ddata_t*)(ut->data)) != NULL); |
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// local variables
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aos_utresult_t result = {0, 0};
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uint32_t status; |
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uint8_t data = 0;
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uint8_t write_data[5];
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uint8_t read_data[5];
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int16_t sdata[3];
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uint8_t status_reg; |
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eventmask_t event_mask; |
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bool success = false; |
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uint8_t fifo = 0x5F;
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event_listener_t el; |
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for (uint8_t dataIdx = 0; dataIdx < 4; dataIdx++) { |
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write_data[dataIdx] = (dataIdx+1)*11; |
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} |
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write_data[4] = 0; |
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chprintf(stream, "check identity...\n");
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status = l3g4200d_lld_read_register(((ut_l3g4200ddata_t*)(ut->data))->l3gd, L3G4200D_LLD_REGISTER_WHO_AM_I, &data, 1);
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if(status == APAL_STATUS_SUCCESS && data == L3G4200D_LLD_WHO_AM_I){
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aosUtPassed(stream, &result); |
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} else {
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aosUtFailedMsg(stream, &result, "0x%08X, data: %d\n", status, data);
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} |
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chprintf(stream, "write register...\n");
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status = l3g4200d_lld_write_register(((ut_l3g4200ddata_t*)(ut->data))->l3gd, L3G4200D_LLD_REGISTER_CTRL_REG1, write_data, 1);
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if (status == APAL_STATUS_SUCCESS) {
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aosUtPassed(stream, &result); |
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} else {
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aosUtFailed(stream, &result); |
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} |
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chprintf(stream, "read register...\n");
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status = l3g4200d_lld_read_register(((ut_l3g4200ddata_t*)(ut->data))->l3gd, L3G4200D_LLD_REGISTER_CTRL_REG1, &data, 1);
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if (status == APAL_STATUS_SUCCESS && data == write_data[0]) { |
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aosUtPassed(stream, &result); |
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} else {
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aosUtFailedMsg(stream, &result, "0x%08X, data: %d\n", status, data);
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} |
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chprintf(stream, "write multiple registers...\n");
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status = l3g4200d_lld_write_register(((ut_l3g4200ddata_t*)(ut->data))->l3gd, L3G4200D_LLD_REGISTER_CTRL_REG1, write_data, 5);
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if (status == APAL_STATUS_SUCCESS) {
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aosUtPassed(stream, &result); |
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} else {
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aosUtFailed(stream, &result); |
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} |
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chprintf(stream, "read multiple registers...\n");
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status = l3g4200d_lld_read_register(((ut_l3g4200ddata_t*)(ut->data))->l3gd, L3G4200D_LLD_REGISTER_CTRL_REG1, read_data, 5);
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uint8_t errors = 0;
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for (uint8_t dataIdx = 0; dataIdx < 5; dataIdx++) { |
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if (read_data[dataIdx] != write_data[dataIdx]) {
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++errors; |
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} |
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} |
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if (status == APAL_STATUS_SUCCESS && errors == 0) { |
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aosUtPassed(stream, &result); |
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} else {
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for (uint8_t dataIdx = 0; dataIdx < 5; dataIdx++) { |
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chprintf(stream, "\t\tStatus: %d, CTRL_REG%d: %d, write_data: %d\n", status, dataIdx+1, read_data[dataIdx], write_data[dataIdx]); |
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} |
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aosUtFailedMsg(stream, &result, "0x%08X, errors: %d\n", status, errors);
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} |
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chprintf(stream, "read config...\n");
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l3g4200d_lld_cfg_t cfg; |
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status = l3g4200d_lld_read_config(((ut_l3g4200ddata_t*)(ut->data))->l3gd, &cfg); |
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if (status == APAL_STATUS_SUCCESS) {
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aosUtPassed(stream, &result); |
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} else {
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aosUtFailed(stream, &result); |
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} |
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chprintf(stream, "write config...\n");
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cfg.registers.ctrl_reg1 = L3G4200D_LLD_PD | L3G4200D_LLD_DR_100_HZ | L3G4200D_LLD_BW_12_5 | L3G4200D_LLD_ZEN | L3G4200D_LLD_YEN | L3G4200D_LLD_XEN; |
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//cfg.registers.ctrl_reg1 = L3G4200D_LLD_PD | L3G4200D_LLD_DR_800_HZ | L3G4200D_LLD_BW_20 | L3G4200D_LLD_ZEN | L3G4200D_LLD_YEN | L3G4200D_LLD_XEN;
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cfg.registers.ctrl_reg3 = 0x07;
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cfg.registers.ctrl_reg5 |= L3G4200D_LLD_FIFO_EN; |
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status = l3g4200d_lld_write_config(((ut_l3g4200ddata_t*)(ut->data))->l3gd, cfg); |
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uint8_t reg1 = cfg.data[0];
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status |= l3g4200d_lld_read_config(((ut_l3g4200ddata_t*)(ut->data))->l3gd, &cfg); |
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if (status == APAL_STATUS_SUCCESS && cfg.data[0] == reg1) { |
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aosUtPassed(stream, &result); |
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} else {
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aosUtFailed(stream, &result); |
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} |
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chprintf(stream, "read gyro data for five seconds...\n");
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status = APAL_STATUS_OK; |
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for (uint8_t i = 0; i < 5; ++i) { |
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status |= l3g4200d_lld_read_all_data(((ut_l3g4200ddata_t*)(ut->data))->l3gd, sdata, &cfg); |
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chprintf(stream, "\t\tX = %6d\tY = %6d\tZ = %6d\n", sdata[0], sdata[1], sdata[2]); |
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aosThdSSleep(1);
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} |
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if (status == APAL_STATUS_SUCCESS) {
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aosUtPassed(stream, &result); |
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} else {
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aosUtFailed(stream, &result); |
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} |
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chprintf(stream, "read X axis for five seconds...\n");
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status = APAL_STATUS_SUCCESS; |
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for (uint32_t i = 0; i <= 5; i++) { |
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status |= l3g4200d_lld_read_data(((ut_l3g4200ddata_t*)(ut->data))->l3gd, &(sdata[0]), L3G4200D_LLD_X_AXIS, &cfg);
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chprintf(stream, "\t\tX = %6d\n", sdata[0]); |
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aosThdSSleep(1);
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} |
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if (status == APAL_STATUS_SUCCESS) {
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aosUtPassed(stream, &result); |
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} else {
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aosUtFailed(stream, &result); |
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} |
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chprintf(stream, "read Y axis for five seconds...\n");
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status = APAL_STATUS_SUCCESS; |
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for (uint32_t i = 0; i <= 5; i++) { |
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status |= l3g4200d_lld_read_data(((ut_l3g4200ddata_t*)(ut->data))->l3gd, &(sdata[0]), L3G4200D_LLD_Y_AXIS, &cfg);
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chprintf(stream, "\t\tY = %6d\n", sdata[0]); |
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aosThdSSleep(1);
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} |
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if (status == APAL_STATUS_SUCCESS) {
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aosUtPassed(stream, &result); |
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} else {
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aosUtFailed(stream, &result); |
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} |
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chprintf(stream, "read Z axis for five seconds...\n");
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status = APAL_STATUS_SUCCESS; |
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for (uint32_t i = 0; i <= 5; i++) { |
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status |= l3g4200d_lld_read_data(((ut_l3g4200ddata_t*)(ut->data))->l3gd, &(sdata[0]), L3G4200D_LLD_Z_AXIS, &cfg);
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chprintf(stream, "\t\tZ = %6d\n", sdata[0]); |
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aosThdSSleep(1);
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} |
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if (status == APAL_STATUS_SUCCESS) {
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aosUtPassed(stream, &result); |
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} else {
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aosUtFailed(stream, &result); |
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} |
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aosThdMSleep(10);
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chprintf(stream, "read status register...\n");
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status = l3g4200d_lld_read_status_register(((ut_l3g4200ddata_t*)(ut->data))->l3gd, &status_reg); |
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if (status == APAL_STATUS_SUCCESS) {
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aosUtPassed(stream, &result); |
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} else {
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aosUtFailed(stream, &result); |
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} |
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chprintf(stream, "read interrupt config...\n");
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l3g4200d_lld_int_cfg_t int_cfg; |
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status = l3g4200d_lld_read_int_config(((ut_l3g4200ddata_t*)(ut->data))->l3gd, &int_cfg); |
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if (status == APAL_STATUS_SUCCESS) {
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aosUtPassed(stream, &result); |
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} else {
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aosUtFailed(stream, &result); |
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} |
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chprintf(stream, "write interrupt config...\n");
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int_cfg.registers.int1_tsh_xh = 10;
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status = l3g4200d_lld_write_int_config(((ut_l3g4200ddata_t*)(ut->data))->l3gd, int_cfg); |
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l3g4200d_lld_int_cfg_t int_cfg2; |
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status |= l3g4200d_lld_read_int_config(((ut_l3g4200ddata_t*)(ut->data))->l3gd, &int_cfg2); |
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if (status == APAL_STATUS_SUCCESS && int_cfg.registers.int1_tsh_xh == 10) { |
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aosUtPassed(stream, &result); |
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} else {
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aosUtFailed(stream, &result); |
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} |
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chprintf(stream, "interrupt test: read fifo until empty...\n");
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chEvtRegister(((ut_l3g4200ddata_t*)(ut->data))->src, &el, 0);
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status = l3g4200d_lld_write_fifo_ctrl_register(((ut_l3g4200ddata_t*)(ut->data))->l3gd,fifo); |
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fifo = 0;
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status |= l3g4200d_lld_read_fifo_ctrl_register(((ut_l3g4200ddata_t*)(ut->data))->l3gd,&fifo); |
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status |= l3g4200d_lld_read_all_data(((ut_l3g4200ddata_t*)(ut->data))->l3gd, sdata, &cfg); |
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chEvtGetAndClearFlags(&el); |
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aosThdSSleep(1);
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chEvtGetAndClearFlags(&el); |
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success = false;
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for (uint8_t i = 0; i < 200; i++) { |
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status |= l3g4200d_lld_read_all_data(((ut_l3g4200ddata_t*)(ut->data))->l3gd, sdata, &cfg); |
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event_mask = chEvtWaitAnyTimeout(~0, TIME_IMMEDIATE);
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status |= l3g4200d_lld_read_fifo_src_register(((ut_l3g4200ddata_t*)(ut->data))->l3gd,&fifo); |
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if (event_mask != 0 && ((fifo & L3G4200D_LLD_EMPTY) || fifo == 0)) { |
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success = true;
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break;
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} |
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aosThdMSleep(1);
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} |
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if (status == APAL_STATUS_SUCCESS && success) {
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aosUtPassed(stream, &result); |
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} else {
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aosUtFailed(stream, &result); |
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} |
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fifo = 0x4A;
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status |= l3g4200d_lld_write_fifo_ctrl_register(((ut_l3g4200ddata_t*)(ut->data))->l3gd,fifo); |
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cfg.registers.ctrl_reg1 = L3G4200D_LLD_PD | L3G4200D_LLD_DR_800_HZ | L3G4200D_LLD_BW_20 | L3G4200D_LLD_ZEN | L3G4200D_LLD_YEN | L3G4200D_LLD_XEN; |
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cfg.registers.ctrl_reg3 = 0x04;
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status |= l3g4200d_lld_write_config(((ut_l3g4200ddata_t*)(ut->data))->l3gd, cfg); |
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chprintf(stream, "interrupt test: wait until wtm reached...\n");
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for (uint8_t i = 0; i < 200; i++) { |
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status |= l3g4200d_lld_read_all_data(((ut_l3g4200ddata_t*)(ut->data))->l3gd, sdata, &cfg); |
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event_mask = chEvtWaitAnyTimeout(~0, TIME_IMMEDIATE);
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status |= l3g4200d_lld_read_fifo_src_register(((ut_l3g4200ddata_t*)(ut->data))->l3gd,&fifo); |
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if (event_mask != 0 && (fifo & L3G4200D_LLD_WTM)) { |
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success = true;
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break;
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} |
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aosThdMSleep(10);
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} |
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if (status == APAL_STATUS_SUCCESS && success) {
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aosUtPassed(stream, &result); |
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} else {
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aosUtFailed(stream, &result); |
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} |
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chEvtUnregister(((ut_l3g4200ddata_t*)(ut->data))->src, &el); |
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aosThdMSleep(10);
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aosUtInfoMsg(stream, "driver object memory footprint: %u bytes\n", sizeof(L3G4200DDriver)); |
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return result;
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} |
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#endif /* (AMIROOS_CFG_TESTS_ENABLE == true) && defined(AMIROLLD_CFG_USE_L3G4200D) */ |
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