amiro-os / hal / platforms / STM32 / qei_lld.h @ e404e6c0
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/**
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* @file STM32/qei_lld.h
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* @brief STM32 QEI subsystem low level driver header.
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*
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* @addtogroup QEI
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* @{
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*/
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#ifndef _QEI_LLD_H_
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#define _QEI_LLD_H_
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#include "stm32_tim.h" |
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#if HAL_USE_QEI || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/**
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* @brief Number of input channels per QEI driver.
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*/
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#define QEI_CHANNELS 2 |
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @name Configuration options
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* @{
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*/
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/**
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* @brief QEID1 driver enable switch.
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* @details If set to @p TRUE the support for QEID1 is included.
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* @note The default is @p TRUE.
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*/
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#if !defined(STM32_QEI_USE_TIM1) || defined(__DOXYGEN__)
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#define STM32_QEI_USE_TIM1 TRUE
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#endif
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/**
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* @brief QEID2 driver enable switch.
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* @details If set to @p TRUE the support for QEID2 is included.
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* @note The default is @p TRUE.
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*/
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#if !defined(STM32_QEI_USE_TIM2) || defined(__DOXYGEN__)
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#define STM32_QEI_USE_TIM2 TRUE
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#endif
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/**
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* @brief QEID3 driver enable switch.
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* @details If set to @p TRUE the support for QEID3 is included.
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* @note The default is @p TRUE.
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*/
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#if !defined(STM32_QEI_USE_TIM3) || defined(__DOXYGEN__)
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#define STM32_QEI_USE_TIM3 TRUE
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#endif
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/**
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* @brief QEID4 driver enable switch.
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* @details If set to @p TRUE the support for QEID4 is included.
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* @note The default is @p TRUE.
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*/
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#if !defined(STM32_QEI_USE_TIM4) || defined(__DOXYGEN__)
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#define STM32_QEI_USE_TIM4 TRUE
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#endif
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/**
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* @brief QEID5 driver enable switch.
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* @details If set to @p TRUE the support for QEID5 is included.
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* @note The default is @p TRUE.
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*/
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#if !defined(STM32_QEI_USE_TIM5) || defined(__DOXYGEN__)
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#define STM32_QEI_USE_TIM5 TRUE
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#endif
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/**
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* @brief QEID8 driver enable switch.
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* @details If set to @p TRUE the support for QEID8 is included.
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* @note The default is @p TRUE.
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*/
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#if !defined(STM32_QEI_USE_TIM8) || defined(__DOXYGEN__)
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#define STM32_QEI_USE_TIM8 TRUE
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#endif
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/** @} */
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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#if STM32_QEI_USE_TIM1 && !STM32_HAS_TIM1
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#error "TIM1 not present in the selected device" |
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#endif
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#if STM32_QEI_USE_TIM2 && !STM32_HAS_TIM2
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#error "TIM2 not present in the selected device" |
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#endif
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#if STM32_QEI_USE_TIM3 && !STM32_HAS_TIM3
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#error "TIM3 not present in the selected device" |
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#endif
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#if STM32_QEI_USE_TIM4 && !STM32_HAS_TIM4
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#error "TIM4 not present in the selected device" |
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#endif
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#if STM32_QEI_USE_TIM5 && !STM32_HAS_TIM5
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#error "TIM5 not present in the selected device" |
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#endif
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#if STM32_QEI_USE_TIM8 && !STM32_HAS_TIM8
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#error "TIM8 not present in the selected device" |
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#endif
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#if !STM32_QEI_USE_TIM1 && !STM32_QEI_USE_TIM2 && \
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!STM32_QEI_USE_TIM3 && !STM32_QEI_USE_TIM4 && \ |
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!STM32_QEI_USE_TIM5 && !STM32_QEI_USE_TIM8 |
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#error "QEI driver activated but no TIM peripheral assigned" |
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#endif
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/**
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* @brief QEI driver mode.
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*/
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typedef enum { |
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QEI_COUNT_BOTH = 0,
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QEI_COUNT_CH1 = 1,
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QEI_COUNT_CH2 = 2,
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} qeimode_t; |
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/**
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* @brief QEI input mode.
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*/
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typedef enum { |
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QEI_INPUT_NONINVERTED = 0, /**< Input channel noninverted.*/ |
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QEI_INPUT_INVERTED = 1, /**< Input channel inverted.*/ |
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} qeiinputmode_t; |
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/**
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* @brief QEI count type.
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*/
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typedef uint32_t qeicnt_t;
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/**
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* @brief Driver channel configuration structure.
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*/
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typedef struct { |
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/**
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* @brief Channel input logic.
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*/
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qeiinputmode_t mode; |
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/* End of the mandatory fields.*/
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} QEIChannelConfig; |
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/**
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* @brief Driver configuration structure.
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*/
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typedef struct { |
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/**
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* @brief Driver mode.
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*/
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qeimode_t mode; |
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/**
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* @brief Channels configurations.
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*/
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QEIChannelConfig channels[QEI_CHANNELS]; |
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/**
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* @brief Range in pulses.
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*/
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qeicnt_t range; |
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/* End of the mandatory fields.*/
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} QEIConfig; |
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/**
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* @brief Structure representing an QEI driver.
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*/
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struct QEIDriver {
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/**
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* @brief Driver state.
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*/
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qeistate_t state; |
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/**
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* @brief Current configuration data.
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*/
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const QEIConfig *config;
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#if defined(QEI_DRIVER_EXT_FIELDS)
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QEI_DRIVER_EXT_FIELDS |
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#endif
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/* End of the mandatory fields.*/
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/**
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* @brief Pointer to the TIMx registers block.
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*/
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stm32_tim_t *tim; |
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}; |
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/*===========================================================================*/
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/* Driver macros. */
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/*===========================================================================*/
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/**
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* @brief Returns the direction of the last transition.
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* @details The direction is defined as boolean and is
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* calculated at each transition on any input.
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*
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* @param[in] qeip pointer to the @p QEIDriver object
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* @return The request direction.
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* @retval FALSE Position counted up.
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* @retval TRUE Position counted down.
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*
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* @iclass
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*/
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#define qei_lld_get_direction(qeip) !!((qeip)->tim->CR1 & TIM_CR1_DIR)
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/**
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* @brief Returns the position of the encoder.
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* @details The position is defined as number of pulses since last reset.
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*
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* @param[in] qeip pointer to the @p QEIDriver object
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* @return The number of pulses.
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*
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* @iclass
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*/
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#define qei_lld_get_position(qeip) ((qeip)->tim->CNT)
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/**
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* @brief Returns the range of the encoder.
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* @details The range is defined as number of maximum pulse count.
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*
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* @param[in] qeip pointer to the @p QEIDriver object
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* @return The number of pulses.
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*
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* @iclass
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*/
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#define qei_lld_get_range(qeip) ((qeip)->tim->ARR + 1) |
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/*===========================================================================*/
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/* External declarations. */
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/*===========================================================================*/
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#if STM32_QEI_USE_TIM1 && !defined(__DOXYGEN__)
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extern QEIDriver QEID1;
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#endif
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#if STM32_QEI_USE_TIM2 && !defined(__DOXYGEN__)
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extern QEIDriver QEID2;
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#endif
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#if STM32_QEI_USE_TIM3 && !defined(__DOXYGEN__)
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extern QEIDriver QEID3;
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#endif
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#if STM32_QEI_USE_TIM4 && !defined(__DOXYGEN__)
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extern QEIDriver QEID4;
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#endif
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#if STM32_QEI_USE_TIM5 && !defined(__DOXYGEN__)
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extern QEIDriver QEID5;
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#endif
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#if STM32_QEI_USE_TIM8 && !defined(__DOXYGEN__)
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extern QEIDriver QEID8;
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#endif
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#ifdef __cplusplus
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extern "C" { |
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#endif
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void qei_lld_init(void); |
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void qei_lld_start(QEIDriver *qeip);
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void qei_lld_stop(QEIDriver *qeip);
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void qei_lld_enable(QEIDriver *qeip);
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void qei_lld_disable(QEIDriver *qeip);
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#ifdef __cplusplus
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} |
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#endif
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#endif /* HAL_USE_QEI */ |
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#endif /* _QEI_LLD_H_ */ |
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/** @} */
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