AMiRo-OS

doc

AMiRo-OS is the operating system for the base version of the Autonomous Mini

system kernel and extends it with platform specific functionalities.

Copyright (C) 2016..2017  Thomas Schöpping et al.

 - Thomas Schöpping        <tschoepp[at]cit-ec.uni-bielefeld.de>

 - Timo Korthals           <tkorthals[at]cit-ec.uni-bielefeld.de>

 - Stefan Herbrechtsmeier  <sherbrec[at]cit-ec.uni-bielefeld.de>

 - Teerapat Chinapirom     <tchinapirom[at]cit-ec.uni-bielefeld.de>

 - Robert Abel

 - Marvin Barther

 - Claas Braun

 - Tristan Kenneweg

 1  Required software

   1.1  Git

   1.2  GCC ARM Embedded Toolchain

   1.3  ChibiOS

   1.4  AMiRo-BLT

 2  Recommended software

   2.1  gtkterm and hterm

   2.2  QtCreator

 3  Building and flashing

In order to compile the source code, you need to install the GCC for ARM

embedded devices. Since AMiRo-OS requires ChibiOS as system kernel, you need a

copy of that project as well. Furthermore, AMiRo-OS requires a compatible

bootloader, such as provided by the AMiRo-BLT project.

1.2 GCC ARM Embedded Toolchain

------------------------------

Various versions of the GCC for ARM embedded devices can be found at

<https://launchpad.net/gcc-arm-embedded>. It is highly recommended to use the

version 4.8 with update 2014-q1 since some others will cause issues. For

installation of the compiler toolchain, please follow the instructions that can

be found on the web page.

If you are running a 64-bit operating system, you will have to install several

32-bit libraries in order to make the compiler work. The required packages are

libc6, libstdc++6, and libncurses5. You can run the following shell commands to

install the according 32-bit versions of the packages:

  >$ sudo dpkg --add-architecture i386 && sudo apt-get update

  >$ sudo apt-get install libc6:i386 libstdc++6:i386 libncurses5:i386

1.3 ChibiOS

-----------

copy of it as well. First, go to the directory which contains the AMiRo-OS

folder (but do not go into the AMiRo-OS directory itself!). Now clone the GIT

repository of ChibiOS and checkout version 2.6.x:

  >$ git clone https://github.com/ChibiOS/ChibiOS.git ChibiOS

  >$ cd ChibiOS

  >$ git checkout 2e6dfc7364e7551483922ea6afbaea8f3501ab0e

It is highly recommended to use exactly this commit. Although newer commits in

the 2.6.x branch might work fine, AMiRo-OS is not compatible with ChibiOS

version 3 or newer.

AMiRo-OS comes with some patches to ChibiOS, which must be applied as well

before compiling the project. Therefore you need to copy all files from the

./patches directory of AMiRo-OS to the root directory of ChibiOS. You can then

apply the patches via the following command:

  >$ for i in `ls | grep patch`; do git am --ignore-space-change --ignore-whitespace < ${i}; done

If the files could not be patched successfully, you are probably using an

incompatible version of ChibiOS (try to checkout the correct commit as denoted

above).

1.4 AMiRo-BLT

-------------

AMiRo-BLT is an additional software project, which is developed in parallel with

AMiRo-OS. If you did not receive a copy of AMiRo-BLT with AMiRo-OS, you can find

all code and documentation at <https://opensource.cit-ec.de/projects/amiro-os>.

Instructions for installation and how to use the software provided by AMiRo-BLT

can be found on the web page or in the project's readme file. It is highly

recommended to install AMiRo-BLT in the same directory as AMiRo-OS and ChibiOS

and name its root directory 'amiro-blt'.

In order to fully use all features of AMiRo-OS it is recommended to install the

'hterm' or 'gtkterm' application for accessing the robot. To ease further

development, this project offers support for the QtCreator IDE.

Depending on your operating system, it is recommended to install 'gtkterm' for

gtkterm you need to modify the configuration file ~/.gtktermrc (it is generated

For hterm you must need to configure the tool analogously.

2.2 - QtCreator

---------------

In order to setup QtCreator projects for the three AMiRo base modules, a script

is provided in the directory ./ide/qtcreator/. It is accompanied by an

additional README.txt file, which contains further information.

project for the according AMiRo module. Therefore you have to use the makefiles

provided in ./devices/<DeviceToRecompile>/ by simply executing 'make' in the

according directory. If you want to compile all modules at once, you can also

use the makefile in the ./devices/ folder.

After compilation, you always have to flash the generated program to the robot.

Therefore you need to install the SerialBoot tool provided by the AMiRo-BLT

project. By default AMiRo-OS assumes AMiRo-BLT to be installed in the same

folder and its root directory to be named 'amiro-blt'. If this is the case, it

will automatically detect the SerialBoot tool. Otherwise the tool must be

accessible globally under the environment variable 'SERIALBOOT'. You can make

it so by appending the following line to your ~/.bashrc file:

  export SERIALBOOT=</absolute/path/to/the/SerialBoot/binary>

You can test the tool by calling it via the variable:

  >$ ${SERIALBOOT}

This should print some information about the tool.

Similar to the compilation procedure as described above, you can flash either

each module separately, or all modules at once by executing 'make flash' from

the according directory. Note that you must connect the programming cable either

to the DiWheelDrive or the PowerManagement module for flashing the operating

system. All other modules are powered off after reset so that only these two

offer a bootloader that is required for flashing.

#include "ch.h"

#include "hal.h"

/**

 * @brief   PAL setup.

 * @details Digital I/O ports static configuration as defined in @p board.h.

 *          This variable is used by the HAL when initializing the PAL driver.

 */

#if HAL_USE_PAL || defined(__DOXYGEN__)

const PALConfig pal_default_config =

{

  {VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH},

  {VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH},

  {VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH},

  {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH},

  {VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH},

  {VAL_GPIOFODR, VAL_GPIOFCRL, VAL_GPIOFCRH},

  {VAL_GPIOGODR, VAL_GPIOGCRL, VAL_GPIOGCRH},

};

#endif

/*

 * Early initialization code.

 * This initialization must be performed just after stack setup and before

 * any other initialization.

 */

void __early_init(void) {

  stm32_clock_init();

}

/*

 * Board-specific initialization code.

 */

void boardInit(void) {

  /*

   * Several I/O pins are re-mapped:

   *   JTAG disabled and SWJ enabled

   *   TIM2 to the PA15/PB3/PA2/PA3 pins.

   *   TIM3 to PC6/PC7 pins.

   *   USART3 to the PC10/PC11 pins.

   *   I2C1 to the PB8/PB9 pins.

   */

  AFIO->MAPR = AFIO_MAPR_SWJ_CFG_DISABLE |

               AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 |

               AFIO_MAPR_TIM3_REMAP_FULLREMAP |

               AFIO_MAPR_USART3_REMAP_PARTIALREMAP |

               AFIO_MAPR_I2C1_REMAP;

}

inline void boardWriteIoPower(const uint8_t value)

{

    if (value) {

        // drive pins

        palSetPadMode(GPIOA, GPIOA_CAN_TX, PAL_MODE_STM32_ALTERNATE_PUSHPULL);

    } else {

        // float pins

        palSetPadMode(GPIOA, GPIOA_CAN_TX, PAL_MODE_INPUT);

    }

}

inline void boardWriteLed(int value)

{

    palWritePad(GPIOA, GPIOA_LED, !value);

}

inline void boardRequestShutdown(void)

{

  palClearPad(GPIOC, GPIOC_SYS_PD_N);

}

inline void boardStandby(void)

{

  palSetPad(GPIOC, GPIOC_SYS_PD_N);

  chSysLock();

  // Standby

  // set deepsleep bit

  SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;

  // enable wakeup pin

  //PWR->CSR |= PWR_CSR_EWUP;

  // set PDDS, clear WUF, clear SBF

  PWR->CR |= (PWR_CR_CWUF | PWR_CR_PDDS | PWR_CR_CSBF);

  // clear RTC wakeup source flags

  RTC->CRL &= ~(RTC_CRL_ALRF);

  // Wait for Interrupt

  __WFI();

}

inline void boardWakeup(void) {

  palClearPad(GPIOC, GPIOC_SYS_PD_N);

  chThdSleepMicroseconds(10);

  palSetPad(GPIOC, GPIOC_SYS_PD_N);

}

inline void boardClearI2CBus(const uint8_t scl_pad, const uint8_t sda_pad) {

  uint8_t i;

  // configure I²C SCL and SDA open drain

  palSetPadMode(GPIOB, scl_pad, PAL_MODE_OUTPUT_OPENDRAIN);

  palSetPadMode(GPIOB, sda_pad, PAL_MODE_OUTPUT_OPENDRAIN);

  // perform a 2-wire software reset for the eeprom (see AT24C01BN-SH-B datasheet, chapter 3)

  // note: clock is ~50kHz (20us per cycle)

  palSetPad(GPIOB, sda_pad);

  palClearPad(GPIOB, scl_pad);

  chThdSleepMicroseconds(10);

  palSetPad(GPIOB, scl_pad);

  chThdSleepMicroseconds(5);

  palClearPad(GPIOB, sda_pad);

  chThdSleepMicroseconds(5);

  palClearPad(GPIOB, scl_pad);

  chThdSleepMicroseconds(5);

  palSetPad(GPIOB, sda_pad);

  chThdSleepMicroseconds(5);

  for (i = 0; i < 9; ++i) {

    palSetPad(GPIOB, scl_pad);

    chThdSleepMicroseconds(10);

    palClearPad(GPIOB, scl_pad);

    chThdSleepMicroseconds(10);

  }

  palSetPad(GPIOB, scl_pad);

  chThdSleepMicroseconds(5);

  palClearPad(GPIOB, sda_pad);

  chThdSleepMicroseconds(5);

  palClearPad(GPIOB, scl_pad);

  chThdSleepMicroseconds(10);

  palSetPad(GPIOB, scl_pad);

  chThdSleepMicroseconds(5);

  palSetPad(GPIOB, sda_pad);

  chThdSleepMicroseconds(5);

  palClearPad(GPIOB, scl_pad);

  chThdSleepMicroseconds(10);

  // perform bus clear as per I²C Specification v6 3.1.16

  // note: clock is 100kHz (10us per cycle)

  for (i = 0; i < 10; i++) {

    palClearPad(GPIOB, scl_pad);

    chThdSleepMicroseconds(5);

    palSetPad(GPIOB, scl_pad);

    chThdSleepMicroseconds(5);

  }

  // reconfigure I²C SCL

  palSetPadMode(GPIOB, scl_pad, PAL_MODE_STM32_ALTERNATE_OPENDRAIN);

  palSetPadMode(GPIOB, sda_pad, PAL_MODE_STM32_ALTERNATE_OPENDRAIN);

  return;

}

#ifndef _BOARD_H_

#define _BOARD_H_

/*

 * Setup for AMiRo DiWheelDrive board.

 */

/*

 * Board identifier.

 */

#define BOARD_DI_WHEEL_DRIVE

#define BOARD_NAME              "AMiRo DiWheelDrive"

#define BOARD_VERSION           "1.1"

/*

 * Board frequencies.

 */

#define STM32_LSECLK            0

#define STM32_HSECLK            8000000

/*

 * MCU type as defined in the ST header file stm32f1xx.h.

 */

#define STM32F10X_HD

/*

 * IO pins assignments.

 */

#define GPIOA_WKUP              0

#define GPIOA_LED               1

#define GPIOA_DRIVE_PWM1A       2

#define GPIOA_DRIVE_PWM1B       3

#define GPIOA_MOTION_SCLK       5

#define GPIOA_MOTION_MISO       6

#define GPIOA_MOTION_MOSI       7

#define GPIOA_PROG_RX           9

#define GPIOA_PROG_TX           10

#define GPIOA_CAN_RX            11

#define GPIOA_CAN_TX            12

#define GPIOA_SWDIO             13

#define GPIOA_SWCLK             14

#define GPIOA_DRIVE_PWM2B       15

#define GPIOB_DRIVE_SENSE2      1

#define GPIOB_POWER_EN          2

#define GPIOB_DRIVE_PWM2A       3

#define GPIOB_COMPASS_DRDY      5

#define GPIOB_DRIVE_ENC1A       6

#define GPIOB_DRIVE_ENC1B       7

#define GPIOB_COMPASS_SCL       8

#define GPIOB_COMPASS_SDA       9

#define GPIOB_IR_SCL            10

#define GPIOB_IR_SDA            11

#define GPIOB_IR_INT            12

#define GPIOB_GYRO_DRDY         13

#define GPIOB_SYS_UART_UP       14

#define GPIOB_ACCEL_INT_N       15

#define GPIOC_DRIVE_SENSE1      0

#define GPIOC_SYS_INT_N         1

#define GPIOC_PATH_DCSTAT       3

#define GPIOC_PATH_DCEN         5

#define GPIOC_DRIVE_ENC2B       6

#define GPIOC_DRIVE_ENC2A       7

#define GPIOC_SYS_PD_N          8

#define GPIOC_SYS_REG_EN        9

#define GPIOC_SYS_UART_RX       10

#define GPIOC_SYS_UART_TX       11

#define GPIOC_ACCEL_SS_N        13

#define GPIOC_GYRO_SS_N         14

#define GPIOD_OSC_IN            0

#define GPIOD_OSC_OUT           1

#define GPIOD_SYS_WARMRST_N     2

/*

 * I/O ports initial setup, this configuration is established soon after reset

 * in the initialization code.

 */

#define PIN_MODE_INPUT(n)               (0x4U << (((n) % 8) * 4))

#define PIN_MODE_INPUT_PULLX(n)         (0x8U << (((n) % 8) * 4))

#define PIN_MODE_INPUT_ANALOG(n)        (0x0U << (((n) % 8) * 4))

/* Push Pull output 50MHz */

#define PIN_MODE_OUTPUT_PUSHPULL(n)     (0x3U << (((n) % 8) * 4))

/* Open Drain output 50MHz */

#define PIN_MODE_OUTPUT_OPENDRAIN(n)    (0x7U << (((n) % 8) * 4))

/* Alternate Push Pull output 50MHz */

#define PIN_MODE_ALTERNATE_PUSHPULL(n)  (0xbU << (((n) % 8) * 4))

/* Alternate Open Drain output 50MHz */

#define PIN_MODE_ALTERNATE_OPENDRAIN(n) (0xfU << (((n) % 8) * 4))

/*

 * Port A setup.

 */

#define VAL_GPIOACRL            (PIN_MODE_INPUT(GPIOA_WKUP) | \

                                 PIN_MODE_OUTPUT_OPENDRAIN(GPIOA_LED) | \

                                 PIN_MODE_ALTERNATE_PUSHPULL(GPIOA_DRIVE_PWM1A) | \

                                 PIN_MODE_ALTERNATE_PUSHPULL(GPIOA_DRIVE_PWM1B) | \

                                 PIN_MODE_INPUT_PULLX(4) | \

                                 PIN_MODE_ALTERNATE_PUSHPULL(GPIOA_MOTION_SCLK) | \

                                 PIN_MODE_INPUT_PULLX(GPIOA_MOTION_MISO) | \

                                 PIN_MODE_ALTERNATE_PUSHPULL(GPIOA_MOTION_MOSI))

#define VAL_GPIOACRH            (PIN_MODE_INPUT_PULLX(8) | \

                                 PIN_MODE_ALTERNATE_PUSHPULL(GPIOA_PROG_RX) | \

                                 PIN_MODE_INPUT_PULLX(GPIOA_PROG_TX) | \

                                 PIN_MODE_INPUT_PULLX(GPIOA_CAN_RX) | \

                                 PIN_MODE_ALTERNATE_PUSHPULL(GPIOA_CAN_TX) | \

                                 PIN_MODE_INPUT_PULLX(GPIOA_SWDIO) | \

                                 PIN_MODE_INPUT_PULLX(GPIOA_SWCLK) | \

                                 PIN_MODE_ALTERNATE_PUSHPULL(GPIOA_DRIVE_PWM2B))

#define VAL_GPIOAODR            0xF7FF /* prevent power over CAN bug */

/*

 * Port B setup.

 */

#define VAL_GPIOBCRL            (PIN_MODE_INPUT_PULLX(0) | \

                                 PIN_MODE_INPUT_ANALOG(GPIOB_DRIVE_SENSE2) | \

                                 PIN_MODE_OUTPUT_PUSHPULL(GPIOB_POWER_EN) | \

                                 PIN_MODE_ALTERNATE_PUSHPULL(GPIOB_DRIVE_PWM2A) | \

                                 PIN_MODE_INPUT_PULLX(4) | \

                                 PIN_MODE_INPUT_PULLX(GPIOB_COMPASS_DRDY) | \

                                 PIN_MODE_INPUT(GPIOB_DRIVE_ENC1A) | \

                                 PIN_MODE_INPUT(GPIOB_DRIVE_ENC1B))

#define VAL_GPIOBCRH            (PIN_MODE_ALTERNATE_OPENDRAIN(GPIOB_COMPASS_SCL) | \

                                 PIN_MODE_ALTERNATE_OPENDRAIN(GPIOB_COMPASS_SDA) | \

                                 PIN_MODE_ALTERNATE_OPENDRAIN(GPIOB_IR_SCL) | \

                                 PIN_MODE_ALTERNATE_OPENDRAIN(GPIOB_IR_SDA) | \

                                 PIN_MODE_INPUT(GPIOB_IR_INT) | \

                                 PIN_MODE_INPUT_PULLX(GPIOB_GYRO_DRDY) | \

                                 PIN_MODE_OUTPUT_OPENDRAIN(GPIOB_SYS_UART_UP) | \

                                 PIN_MODE_INPUT_PULLX(GPIOB_ACCEL_INT_N))

#define VAL_GPIOBODR            0xFFFB /* initially the motors are not powered */

/*

 * Port C setup.

 */

#define VAL_GPIOCCRL            (PIN_MODE_INPUT_ANALOG(GPIOC_DRIVE_SENSE1) | \

                                 PIN_MODE_OUTPUT_OPENDRAIN(GPIOC_SYS_INT_N) | \

                                 PIN_MODE_INPUT_PULLX(2) | \

                                 PIN_MODE_INPUT(GPIOC_PATH_DCSTAT) | \

                                 PIN_MODE_INPUT_PULLX(4) | \

                                 PIN_MODE_OUTPUT_PUSHPULL(GPIOC_PATH_DCEN) | \

                                 PIN_MODE_INPUT(GPIOC_DRIVE_ENC2B) | \

                                 PIN_MODE_INPUT(GPIOC_DRIVE_ENC2A))

#define VAL_GPIOCCRH            (PIN_MODE_OUTPUT_OPENDRAIN(GPIOC_SYS_PD_N) | \

                                 PIN_MODE_INPUT(GPIOC_SYS_REG_EN) | \

                                 PIN_MODE_INPUT(GPIOC_SYS_UART_RX) | \

                                 PIN_MODE_INPUT(GPIOC_SYS_UART_TX) | \

                                 PIN_MODE_INPUT_PULLX(12) | \

                                 PIN_MODE_OUTPUT_PUSHPULL(GPIOC_ACCEL_SS_N) | \

                                 PIN_MODE_OUTPUT_PUSHPULL(GPIOC_GYRO_SS_N) | \

                                 PIN_MODE_INPUT_PULLX(15))

#define VAL_GPIOCODR            0xFFDD /* initially charging via the pins is disabled and SYSNIN_N indicates that the OS is busy */

/*

 * Port D setup.

 */

#define VAL_GPIODCRL            (PIN_MODE_INPUT(GPIOD_OSC_IN) | \

                                 PIN_MODE_INPUT(GPIOD_OSC_OUT) | \

                                 PIN_MODE_OUTPUT_OPENDRAIN(GPIOD_SYS_WARMRST_N) | \

                                 PIN_MODE_INPUT_PULLX(3) | \

                                 PIN_MODE_INPUT_PULLX(4) | \

                                 PIN_MODE_INPUT_PULLX(5) | \

                                 PIN_MODE_INPUT_PULLX(6) | \

                                 PIN_MODE_INPUT_PULLX(7))

#define VAL_GPIODCRH            0x88888888

#define VAL_GPIODODR            0xFFFF

/*

 * Port E setup.

 */

#define VAL_GPIOECRL            0x88888888 /*  PE7...PE0 */

#define VAL_GPIOECRH            0x88888888 /* PE15...PE8 */

#define VAL_GPIOEODR            0xFFFF

/*

 * Port F setup.

 */

#define VAL_GPIOFCRL            0x88888888 /*  PF7...PF0 */

#define VAL_GPIOFCRH            0x88888888 /* PF15...PF8 */

#define VAL_GPIOFODR            0xFFFF

/*

 * Port G setup.

 */

#define VAL_GPIOGCRL            0x88888888 /*  PG7...PG0 */

#define VAL_GPIOGCRH            0x88888888 /* PG15...PG8 */

#define VAL_GPIOGODR            0xFFFF

#if !defined(_FROM_ASM_)

#ifdef __cplusplus

extern "C" {

#endif

  void boardInit(void);

  void boardWriteIoPower(const uint8_t value);

  void boardWriteLed(int value);

  void boardRequestShutdown(void);

  void boardStandby(void);

  void boardWakeup(void);

  void boardClearI2CBus(const uint8_t scl_pad, const uint8_t sda_pad);

#ifdef __cplusplus

}

#endif

#endif /* _FROM_ASM_ */

#endif /* _BOARD_H_ */

# List of all the board related files.

BOARDSRC = ${AMIRO}/boards/DiWheelDrive/board.c

# Required include directories

BOARDINC = ${AMIRO}/boards/DiWheelDrive

# Required linker directory

BOARDLD = ${AMIRO}/ports

#include "ch.h"

#include "hal.h"

/**

 * @brief   PAL setup.

 * @details Digital I/O ports static configuration as defined in @p board.h.

 *          This variable is used by the HAL when initializing the PAL driver.

 */

#if HAL_USE_PAL || defined(__DOXYGEN__)

const PALConfig pal_default_config =

{

  {VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH},

  {VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH},

  {VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH},

  {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH},

  {VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH},

  {VAL_GPIOFODR, VAL_GPIOFCRL, VAL_GPIOFCRH},

  {VAL_GPIOGODR, VAL_GPIOGCRL, VAL_GPIOGCRH},

};

#endif

/*

 * Early initialization code.

 * This initialization must be performed just after stack setup and before

 * any other initialization.

 */

void __early_init(void) {

  stm32_clock_init();

}

/*

 * Board-specific initialization code.

 */

void boardInit(void) {

  /*

   * Several I/O pins are re-mapped:

   *   JTAG disabled and SWD enabled

   */

  AFIO->MAPR = AFIO_MAPR_SWJ_CFG_JTAGDISABLE |

               AFIO_MAPR_USART3_REMAP_PARTIALREMAP;

}

inline void boardRequestShutdown(void)

{

  palClearPad(GPIOC, GPIOC_SYS_PD_N);

}

inline void boardStandby(void)

{

  palSetPad(GPIOC, GPIOC_SYS_PD_N);

  chSysLock();

  // Standby

  // set deepsleep bit

  SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;

  // set PDDS, clear WUF, clear SBF

  PWR->CR |= (PWR_CR_CWUF | PWR_CR_PDDS | PWR_CR_CSBF);

  // clear RTC wakeup source flags

  RTC->CRL &= ~(RTC_CRL_ALRF);

  // Wait for Interrupt

  __WFI();

}

inline void boardClearI2CBus(const uint8_t scl_pad, const uint8_t sda_pad) {

  uint8_t i;

  // configure I²C SCL and SDA open drain

  palSetPadMode(GPIOB, scl_pad, PAL_MODE_OUTPUT_OPENDRAIN);

  palSetPadMode(GPIOB, sda_pad, PAL_MODE_OUTPUT_OPENDRAIN);

  // perform a 2-wire software reset for the eeprom (see AT24C01BN-SH-B datasheet, chapter 3)

  // note: clock is ~50kHz (20us per cycle)

  palSetPad(GPIOB, sda_pad);

  palClearPad(GPIOB, scl_pad);

  chThdSleepMicroseconds(10);

  palSetPad(GPIOB, scl_pad);

  chThdSleepMicroseconds(5);

  palClearPad(GPIOB, sda_pad);

  chThdSleepMicroseconds(5);

  palClearPad(GPIOB, scl_pad);

  chThdSleepMicroseconds(5);

  palSetPad(GPIOB, sda_pad);

  chThdSleepMicroseconds(5);

  for (i = 0; i < 9; ++i) {

    palSetPad(GPIOB, scl_pad);

    chThdSleepMicroseconds(10);

    palClearPad(GPIOB, scl_pad);

    chThdSleepMicroseconds(10);

  }

  palSetPad(GPIOB, scl_pad);

  chThdSleepMicroseconds(5);

  palClearPad(GPIOB, sda_pad);

  chThdSleepMicroseconds(5);

  palClearPad(GPIOB, scl_pad);

  chThdSleepMicroseconds(10);

  palSetPad(GPIOB, scl_pad);

  chThdSleepMicroseconds(5);

  palSetPad(GPIOB, sda_pad);

  chThdSleepMicroseconds(5);

  palClearPad(GPIOB, scl_pad);

  chThdSleepMicroseconds(10);

  // perform bus clear as per I²C Specification v6 3.1.16

  // note: clock is 100kHz (10us per cycle)

  for (i = 0; i < 10; i++) {

    palClearPad(GPIOB, scl_pad);

    chThdSleepMicroseconds(5);

    palSetPad(GPIOB, scl_pad);

    chThdSleepMicroseconds(5);

  }

  // reconfigure I²C SCL

  palSetPadMode(GPIOB, scl_pad, PAL_MODE_STM32_ALTERNATE_OPENDRAIN);

  palSetPadMode(GPIOB, sda_pad, PAL_MODE_STM32_ALTERNATE_OPENDRAIN);

  return;

}

#ifndef _BOARD_H_

#define _BOARD_H_

/*

 * Setup for AMiRo LightRing board.

 */

/*

 * Board identifier.

 */

#define BOARD_LIGHT_RING

#define BOARD_NAME              "AMiRo LightRing"

#define BOARD_VERSION           "1.0"

/*

 * Board frequencies.

 */

#define STM32_LSECLK            0

#define STM32_HSECLK            8000000

/*

 * MCU type as defined in the ST header file stm32f1xx.h.

 */

#define STM32F10X_HD

/*

 * IO pins assignments.

 */

#define GPIOA_LASER_RX          2

#define GPIOA_LASER_TX          3

#define GPIOA_LIGHT_BLANK       4

#define GPIOA_LIGHT_SCLK        5

#define GPIOA_LIGHT_MOSI        7

#define GPIOA_PROG_RX           9

#define GPIOA_PROG_TX           10

#define GPIOA_CAN_RX            11

#define GPIOA_CAN_TX            12

#define GPIOB_LASER_EN          2

#define GPIOB_LASER_OC_N        5

#define GPIOB_SYS_UART_DN       6

#define GPIOB_WL_GDO2           8

#define GPIOB_WL_GDO0           9

#define GPIOB_MEM_SCL           10

#define GPIOB_MEM_SDA           11

#define GPIOB_WL_SS_N           12

#define GPIOB_WL_SCLK           13

#define GPIOB_WL_MISO           14

#define GPIOB_WL_MOSI           15

#define GPIOC_LIGHT_XLAT        4

#define GPIOC_SYS_UART_RX       10

#define GPIOC_SYS_UART_TX       11

#define GPIOC_SYS_PD_N          14

#define GPIOD_OSC_IN            0

#define GPIOD_OSC_OUT           1

#define GPIOD_SYS_INT_N         2

/*

 * I/O ports initial setup, this configuration is established soon after reset

 * in the initialization code.

 */

#define PIN_MODE_INPUT(n)               (0x4U << (((n) % 8) * 4))

#define PIN_MODE_INPUT_PULLX(n)         (0x8U << (((n) % 8) * 4))

#define PIN_MODE_INPUT_ANALOG(n)        (0x0U << (((n) % 8) * 4))

/* Push Pull output 50MHz */

#define PIN_MODE_OUTPUT_PUSHPULL(n)     (0x3U << (((n) % 8) * 4))

/* Open Drain output 50MHz */

#define PIN_MODE_OUTPUT_OPENDRAIN(n)    (0x7U << (((n) % 8) * 4))

/* Alternate Push Pull output 50MHz */

#define PIN_MODE_ALTERNATE_PUSHPULL(n)  (0xbU << (((n) % 8) * 4))

/* Alternate Open Drain output 50MHz */

#define PIN_MODE_ALTERNATE_OPENDRAIN(n) (0xfU << (((n) % 8) * 4))

/*

 * Port A setup.

 */

#define VAL_GPIOACRL            (PIN_MODE_INPUT_PULLX(0) | \

                                 PIN_MODE_INPUT_PULLX(1) | \

                                 PIN_MODE_ALTERNATE_PUSHPULL(GPIOA_LASER_RX) | \

                                 PIN_MODE_INPUT_PULLX(GPIOA_LASER_TX) | \

                                 PIN_MODE_OUTPUT_PUSHPULL(GPIOA_LIGHT_BLANK) | \

                                 PIN_MODE_ALTERNATE_PUSHPULL(GPIOA_LIGHT_SCLK) | \

                                 PIN_MODE_INPUT_PULLX(6) | \

                                 PIN_MODE_ALTERNATE_PUSHPULL(GPIOA_LIGHT_MOSI))

#define VAL_GPIOACRH            (PIN_MODE_INPUT_PULLX(8) | \

                                 PIN_MODE_ALTERNATE_PUSHPULL(GPIOA_PROG_RX) | \

                                 PIN_MODE_INPUT_PULLX(GPIOA_PROG_TX) | \

                                 PIN_MODE_INPUT(GPIOA_CAN_RX) | \

                                 PIN_MODE_ALTERNATE_PUSHPULL(GPIOA_CAN_TX) | \

                                 PIN_MODE_INPUT_PULLX(13) | \

                                 PIN_MODE_INPUT_PULLX(14) | \

                                 PIN_MODE_INPUT_PULLX(15))

#define VAL_GPIOAODR            0xFFFF

/*

 * Port B setup.

 */

#define VAL_GPIOBCRL            (PIN_MODE_INPUT_PULLX(0) | \

                                 PIN_MODE_INPUT_PULLX(1) | \

                                 PIN_MODE_OUTPUT_PUSHPULL(GPIOB_LASER_EN) | \

                                 PIN_MODE_INPUT_PULLX(3) | \

                                 PIN_MODE_INPUT_PULLX(4) | \

                                 PIN_MODE_INPUT(GPIOB_LASER_OC_N) | \

                                 PIN_MODE_OUTPUT_OPENDRAIN(GPIOB_SYS_UART_DN) | \

                                 PIN_MODE_INPUT_PULLX(7))

#define VAL_GPIOBCRH            (PIN_MODE_INPUT_PULLX(GPIOB_WL_GDO2) | \

                                 PIN_MODE_INPUT_PULLX(GPIOB_WL_GDO0) | \

                                 PIN_MODE_ALTERNATE_OPENDRAIN(GPIOB_MEM_SCL) | \

                                 PIN_MODE_ALTERNATE_OPENDRAIN(GPIOB_MEM_SDA) | \

                                 PIN_MODE_OUTPUT_PUSHPULL(GPIOB_WL_SS_N) | \

                                 PIN_MODE_ALTERNATE_PUSHPULL(GPIOB_WL_SCLK) | \

                                 PIN_MODE_INPUT(GPIOB_WL_MISO) | \

                                 PIN_MODE_ALTERNATE_PUSHPULL(GPIOB_WL_MOSI))

#define VAL_GPIOBODR            0xFFFB /* initially LASER_EN is deactivated */

/*

 * Port C setup.

 */

#define VAL_GPIOCCRL            (PIN_MODE_INPUT_PULLX(0) | \

                                 PIN_MODE_INPUT_PULLX(1) | \

                                 PIN_MODE_INPUT_PULLX(2) | \

                                 PIN_MODE_INPUT_PULLX(3) | \

                                 PIN_MODE_OUTPUT_PUSHPULL(GPIOC_LIGHT_XLAT) | \

                                 PIN_MODE_INPUT_PULLX(5) | \

                                 PIN_MODE_INPUT_PULLX(6) | \

                                 PIN_MODE_INPUT_PULLX(7))

#define VAL_GPIOCCRH            (PIN_MODE_INPUT_PULLX(8) | \

                                 PIN_MODE_INPUT_PULLX(9) | \

                                 PIN_MODE_INPUT(GPIOC_SYS_UART_RX) | \

                                 PIN_MODE_INPUT(GPIOC_SYS_UART_TX) | \

                                 PIN_MODE_INPUT_PULLX(12) | \

                                 PIN_MODE_INPUT_PULLX(13) | \

                                 PIN_MODE_OUTPUT_OPENDRAIN(GPIOC_SYS_PD_N) | \

                                 PIN_MODE_INPUT_PULLX(15))

#define VAL_GPIOCODR            0xFFFF

/*

 * Port D setup.

 */

#define VAL_GPIODCRL            (PIN_MODE_INPUT(GPIOD_OSC_IN) | \

                                 PIN_MODE_INPUT(GPIOD_OSC_OUT) | \

                                 PIN_MODE_OUTPUT_OPENDRAIN(GPIOD_SYS_INT_N) | \

                                 PIN_MODE_INPUT_PULLX(3) | \

                                 PIN_MODE_INPUT_PULLX(4) | \

                                 PIN_MODE_INPUT_PULLX(5) | \

                                 PIN_MODE_INPUT_PULLX(6) | \

                                 PIN_MODE_INPUT_PULLX(7))

#define VAL_GPIODCRH            0x88888888

#define VAL_GPIODODR            0xFFFB /* initially SYS_INT_N indicates that the OS is busy */

/*

 * Port E setup.

 */

#define VAL_GPIOECRL            0x88888888 /*  PE7...PE0 */

#define VAL_GPIOECRH            0x88888888 /* PE15...PE8 */

#define VAL_GPIOEODR            0xFFFF

/*

 * Port F setup.

 */

#define VAL_GPIOFCRL            0x88888888 /*  PF7...PF0 */

#define VAL_GPIOFCRH            0x88888888 /* PF15...PF8 */

#define VAL_GPIOFODR            0xFFFF

/*

 * Port G setup.

 */

#define VAL_GPIOGCRL            0x88888888 /*  PG7...PG0 */

#define VAL_GPIOGCRH            0x88888888 /* PG15...PG8 */

#define VAL_GPIOGODR            0xFFFF

#if !defined(_FROM_ASM_)

#ifdef __cplusplus

extern "C" {

#endif

  void boardInit(void);

  void boardRequestShutdown(void);

  void boardStandby(void);

  void boardClearI2CBus(const uint8_t scl_pad, const uint8_t sda_pad);

#ifdef __cplusplus

}

#endif

#endif /* _FROM_ASM_ */

#endif /* _BOARD_H_ */

# List of all the board related files.

BOARDSRC = ${AMIRO}/boards/LightRing/board.c

# Required include directories

BOARDINC = ${AMIRO}/boards/LightRing

# Required linker directory

BOARDLD = ${AMIRO}/ports

#include "ch.h"

#include "hal.h"

#include "board.h"

/**

 * @brief   PAL setup.

 * @details Digital I/O ports static configuration as defined in @p board.h.

 *          This variable is used by the HAL when initializing the PAL driver.

 */

#if HAL_USE_PAL || defined(__DOXYGEN__)

const PALConfig pal_default_config =

{

  {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},

  {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},

  {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},

  {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},

  {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},

  {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},

  {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},

  {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},

  {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}

};

#endif

/*

 * Early initialization code.

 * This initialization must be performed just after stack setup and before

 * any other initialization.

 */

void __early_init(void) {

  stm32_clock_init();

}

/*

 * Board-specific initialization code.

 */

void boardInit(void) {

}

inline void boardWriteIoPower(int value)

{

    palWritePad(GPIOA, GPIOA_SYS_REG_EN, value);

    if (value) {

        // drive pins

        palSetPadMode(GPIOA, GPIOA_CAN_TX, PAL_MODE_ALTERNATE(9));

        palSetPadMode(GPIOA, GPIOA_SYS_UART_TX, PAL_MODE_ALTERNATE(7));

        palSetPadMode(GPIOB, GPIOB_BT_CTS, PAL_MODE_ALTERNATE(7));

    } else {

        // float pins

        palSetPadMode(GPIOA, GPIOA_CAN_TX, PAL_MODE_INPUT);

        palSetPadMode(GPIOA, GPIOA_SYS_UART_TX, PAL_MODE_INPUT);

        palSetPadMode(GPIOB, GPIOB_BT_CTS, PAL_MODE_INPUT);

    }

    chThdSleepMilliseconds(50);

}

inline void boardWriteLed(int value)

{

    palWritePad(GPIOB, GPIOB_LED, !value);

}

inline void boardWriteSystemPower(int value)

{

    palWritePad(GPIOB, GPIOB_POWER_EN, value);

    chThdSleepMilliseconds(50);

}

inline void boardWriteWarmRestart(const uint8_t value)

{

    palWritePad(GPIOC, GPIOC_SYS_WARMRST_N, ~value);

    chThdSleepMilliseconds(50);

}

inline void boardChargerSetState(uint8_t chrg_mask, uint8_t state)

{

  if (chrg_mask & (1u << 0))

    palWritePad(GPIOC, GPIOC_CHARGE_EN1_N, ~state);

  if (chrg_mask & (1u << 1))

    palWritePad(GPIOD, GPIOD_CHARGE_EN2_N, ~state);

}

inline void boardBluetoothSetState(uint8_t state)

{

    palWritePad(GPIOC, GPIOC_BT_RST, ~state);

}

inline void boardRequestShutdown(void)

{

  palClearPad(GPIOC, GPIOC_SYS_PD_N);

}

#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)

inline void boardStandby(void)

{

  chSysLock();

  // set deepsleep bit

  SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;

  // enable wakeup pin

  PWR->CSR |= PWR_CSR_EWUP;

  // set PDDS, clear WUF, clear SBF

  PWR->CR |= (PWR_CR_CWUF | PWR_CR_PDDS | PWR_CR_CSBF);

  // clear RTC wakeup source flags

  RTC->ISR &= ~(RTC_ISR_ALRBF | RTC_ISR_ALRAF | RTC_ISR_WUTF | RTC_ISR_TAMP1F | RTC_ISR_TAMP2F |

                RTC_ISR_TSOVF | RTC_ISR_TSF);

  // Wait for Interrupt

  __WFI();

}

inline void boardStop(const uint8_t lpds, const uint8_t fpds)

{

  chSysLock();

  // set deepsleep bit

  SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;

  // enable wakeup pin

  //PWR->CSR |= PWR_CSR_EWUP;

  // clear PDDS, clear LPDS, clear FPDS

  PWR->CR &= ~(PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS);

  // clear WUF, clear SBF

  PWR->CR |= (PWR_CR_CWUF | PWR_CR_CSBF);

  if (lpds)

    PWR->CR |= (PWR_CR_LPDS);

  if (fpds)

    PWR->CR |= (PWR_CR_FPDS);

  // clear RTC wakeup source flags

  RTC->ISR &= ~(RTC_ISR_ALRBF | RTC_ISR_ALRAF | RTC_ISR_WUTF | RTC_ISR_TAMP1F | RTC_ISR_TAMP2F |

                RTC_ISR_TSOVF | RTC_ISR_TSF);

  // clear pending interrupts

  EXTI->PR = ~0;

  // Wait for Interrupt

  __WFI();

}

#undef RTC_ISR_TAMP2F

inline void boardWakeup(void) {

  palClearPad(GPIOC, GPIOC_SYS_PD_N);

  chThdSleepMicroseconds(10);

  palSetPad(GPIOC, GPIOC_SYS_PD_N);

}

inline void boardClearI2CBus(const uint8_t scl_pad, const uint8_t sda_pad) {

  uint8_t i;

  // configure I²C SCL and SDA open drain

  palSetPadMode(GPIOB, scl_pad, PAL_MODE_OUTPUT_OPENDRAIN);

  palSetPadMode(GPIOB, sda_pad, PAL_MODE_OUTPUT_OPENDRAIN);

  // perform a 2-wire software reset for the eeprom (see AT24C01BN-SH-B datasheet, chapter 3)

  // note: clock is ~50kHz (20us per cycle)

  palSetPad(GPIOB, sda_pad);

  palClearPad(GPIOB, scl_pad);

  chThdSleepMicroseconds(10);

  palSetPad(GPIOB, scl_pad);

  chThdSleepMicroseconds(5);

  palClearPad(GPIOB, sda_pad);

  chThdSleepMicroseconds(5);

  palClearPad(GPIOB, scl_pad);

  chThdSleepMicroseconds(5);

  palSetPad(GPIOB, sda_pad);

  chThdSleepMicroseconds(5);

  for (i = 0; i < 9; ++i) {

    palSetPad(GPIOB, scl_pad);

    chThdSleepMicroseconds(10);

    palClearPad(GPIOB, scl_pad);

    chThdSleepMicroseconds(10);

  }

  palSetPad(GPIOB, scl_pad);

  chThdSleepMicroseconds(5);

  palClearPad(GPIOB, sda_pad);

  chThdSleepMicroseconds(5);

  palClearPad(GPIOB, scl_pad);

  chThdSleepMicroseconds(10);

  palSetPad(GPIOB, scl_pad);

  chThdSleepMicroseconds(5);

  palSetPad(GPIOB, sda_pad);

  chThdSleepMicroseconds(5);

  palClearPad(GPIOB, scl_pad);

  chThdSleepMicroseconds(10);

  // perform bus clear as per I²C Specification v6 3.1.16

  // note: clock is 100kHz (10us per cycle)

  for (i = 0; i < 10; i++) {

    palClearPad(GPIOB, scl_pad);

    chThdSleepMicroseconds(5);

    palSetPad(GPIOB, scl_pad);

    chThdSleepMicroseconds(5);

  }

  // reconfigure I²C SCL

  palSetPadMode(GPIOB, scl_pad, PAL_MODE_ALTERNATE(4) | PAL_STM32_OTYPE_OPENDRAIN);

  palSetPadMode(GPIOB, sda_pad, PAL_MODE_ALTERNATE(4) | PAL_STM32_OTYPE_OPENDRAIN);

  return;

}

inline void boardResetBQ27500I2C(const uint8_t scl_pad, const uint8_t sda_pad) {

  // configure I²C SCL and SDA open drain

  palSetPadMode(GPIOB, scl_pad, PAL_MODE_OUTPUT_OPENDRAIN);

  palSetPadMode(GPIOB, sda_pad, PAL_MODE_OUTPUT_OPENDRAIN);

  // BQ27500: reset by holding bus low for t_BUSERR (17.3 - 21.2 seconds)

  palClearPad(GPIOB, scl_pad);

  palClearPad(GPIOB, sda_pad);

  chThdSleepSeconds(20);

  boardClearI2CBus(scl_pad, sda_pad);

  return;

}

#ifndef _BOARD_H_

#define _BOARD_H_

/*

 * Setup for AMiRo PowerManagement board.

 */

/*

 * Board identifier.

 */

#define BOARD_POWER_MANAGEMENT

#define BOARD_NAME              "AMiRo PowerManagement"

#define BOARD_VERSION           "1.1"

/*

 * Board frequencies.

 */

#define STM32_LSECLK            0

#define STM32_HSECLK            8000000

/*

 * Board voltages.

 * Required for performance limits calculation.

 */

#define STM32_VDD               330

/*

 * MCU type as defined in the ST header file stm32f4xx.h.

 */

#define STM32F40_41xxx

/*

 * IO pins assignments.

 */

#define GPIOA_WKUP              0

#define GPIOA_SYS_UART_TX       2

#define GPIOA_SYS_UART_RX       3

#define GPIOA_SYS_SPI_SS0_N     4

#define GPIOA_SYS_SPI_SCLK      5

#define GPIOA_SYS_SPI_MISO      6

#define GPIOA_SYS_SPI_MOSI      7

#define GPIOA_SYS_REG_EN        8

#define GPIOA_PROG_RX           9

#define GPIOA_PROG_TX           10

#define GPIOA_CAN_RX            11

#define GPIOA_CAN_TX            12

#define GPIOA_SYS_SPI_SS1_N     15

#define GPIOB_IR_INT1_N         0

#define GPIOB_VSYS_SENSE        1

#define GPIOB_POWER_EN          2

#define GPIOB_SYS_UART_DN       3

#define GPIOB_CHARGE_STAT2A     4

#define GPIOB_BUZZER            5

#define GPIOB_GAUGE_BATLOW2     6

#define GPIOB_GAUGE_BATGD2_N    7

#define GPIOB_GAUGE_SCL2        8

#define GPIOB_GAUGE_SDA2        9

#define GPIOB_GAUGE_SCL1        10

#define GPIOB_GAUGE_SDA1        11

#define GPIOB_LED               12

#define GPIOB_BT_RTS            13

#define GPIOB_BT_CTS            14

#define GPIOB_SYS_UART_UP       15

#define GPIOC_CHARGE_STAT1A     0

#define GPIOC_GAUGE_BATLOW1     1

#define GPIOC_GAUGE_BATGD1_N    2

#define GPIOC_CHARGE_EN1_N      3

#define GPIOC_IR_INT2_N         4

#define GPIOC_TOUCH_INT_N       5

#define GPIOC_SYS_DONE          6

#define GPIOC_SYS_PROG_N        7

#define GPIOC_PATH_DC           8

#define GPIOC_SYS_SPI_DIR       9

#define GPIOC_BT_RX             10

#define GPIOC_BT_TX             11

#define GPIOC_SYS_INT_N         12

#define GPIOC_SYS_PD_N          13

#define GPIOC_SYS_WARMRST_N     14

#define GPIOC_BT_RST            15

#define GPIOD_CHARGE_EN2_N      2

#define GPIOH_OSC_IN            0

#define GPIOH_OSC_OUT           1

/*

 * I/O ports initial setup, this configuration is established soon after reset

 * in the initialization code.

 */

#define PIN_MODE_INPUT(n)       (0U << ((n) * 2))

#define PIN_MODE_OUTPUT(n)      (1U << ((n) * 2))

#define PIN_MODE_ALTERNATE(n)   (2U << ((n) * 2))

#define PIN_MODE_ANALOG(n)      (3U << ((n) * 2))

#define PIN_OTYPE_PUSHPULL(n)   (0U << (n))

#define PIN_OTYPE_OPENDRAIN(n)  (1U << (n))

#define PIN_OSPEED_2M(n)        (0U << ((n) * 2))

#define PIN_OSPEED_25M(n)       (1U << ((n) * 2))

#define PIN_OSPEED_50M(n)       (2U << ((n) * 2))

#define PIN_OSPEED_100M(n)      (3U << ((n) * 2))

#define PIN_PUDR_FLOATING(n)    (0U << ((n) * 2))

#define PIN_PUDR_PULLUP(n)      (1U << ((n) * 2))

#define PIN_PUDR_PULLDOWN(n)    (2U << ((n) * 2))

#define PIN_AFIO_AF(n, v)       ((v##U) << ((n % 8) * 4))

/*

 * Port A setup.

 */

#define VAL_GPIOA_MODER         (PIN_MODE_INPUT(GPIOA_WKUP) | \

                                 PIN_MODE_INPUT(1) | \

                                 PIN_MODE_ALTERNATE(GPIOA_SYS_UART_TX) | \

                                 PIN_MODE_ALTERNATE(GPIOA_SYS_UART_RX) | \

                                 PIN_MODE_INPUT(GPIOA_SYS_SPI_SS0_N) | \

                                 PIN_MODE_ALTERNATE(GPIOA_SYS_SPI_SCLK) | \

                                 PIN_MODE_ALTERNATE(GPIOA_SYS_SPI_MOSI) | \

                                 PIN_MODE_ALTERNATE(GPIOA_SYS_SPI_MISO) | \

                                 PIN_MODE_INPUT(GPIOA_SYS_SPI_SS1_N) | \

                                 PIN_MODE_ALTERNATE(GPIOA_PROG_RX) | \

                                 PIN_MODE_ALTERNATE(GPIOA_PROG_TX) | \

                                 PIN_MODE_ALTERNATE(GPIOA_CAN_RX) | \

                                 PIN_MODE_ALTERNATE(GPIOA_CAN_TX) | \

                                 PIN_MODE_INPUT(13) | \

                                 PIN_MODE_INPUT(14) | \

                                 PIN_MODE_OUTPUT(GPIOA_SYS_REG_EN))

#define VAL_GPIOA_OTYPER        (PIN_OTYPE_PUSHPULL(GPIOA_SYS_UART_TX) | \

                                 PIN_OTYPE_PUSHPULL(GPIOA_SYS_SPI_SS0_N) | \

                                 PIN_OTYPE_PUSHPULL(GPIOA_PROG_RX) | \

                                 PIN_OTYPE_PUSHPULL(GPIOA_CAN_TX) | \

                                 PIN_OTYPE_PUSHPULL(GPIOA_SYS_REG_EN))

#define VAL_GPIOA_OSPEEDR       0xFFFFFFFF

#define VAL_GPIOA_PUPDR         (PIN_PUDR_FLOATING(GPIOA_WKUP) | \

                                 PIN_PUDR_PULLUP(1) | \

                                 PIN_PUDR_FLOATING(GPIOA_SYS_UART_TX) | \

                                 PIN_PUDR_FLOATING(GPIOA_SYS_UART_RX) | \

                                 PIN_PUDR_FLOATING(GPIOA_SYS_SPI_SS0_N) | \

                                 PIN_PUDR_FLOATING(GPIOA_SYS_SPI_SCLK) | \

                                 PIN_PUDR_FLOATING(GPIOA_SYS_SPI_MOSI) | \

                                 PIN_PUDR_FLOATING(GPIOA_SYS_SPI_MISO) | \

                                 PIN_PUDR_FLOATING(GPIOA_SYS_SPI_SS1_N) | \

                                 PIN_PUDR_FLOATING(GPIOA_PROG_RX) | \

                                 PIN_PUDR_PULLUP(GPIOA_PROG_TX) | \

                                 PIN_PUDR_FLOATING(GPIOA_CAN_RX) | \

                                 PIN_PUDR_FLOATING(GPIOA_CAN_TX) | \

                                 PIN_PUDR_PULLUP(13) | \

                                 PIN_PUDR_PULLUP(14) | \