amiro-blt / Target / Source / ARMCM4_STM32 / can.c @ 1da30dfc
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/************************************************************************************//** |
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* \file Source\ARMCM4_STM32\can.c
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* \brief Bootloader CAN communication interface source file.
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* \ingroup Target_ARMCM4_STM32
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* \internal
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*----------------------------------------------------------------------------------------
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* C O P Y R I G H T
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*----------------------------------------------------------------------------------------
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* Copyright (c) 2013 by Feaser http://www.feaser.com All rights reserved
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*
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*----------------------------------------------------------------------------------------
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* L I C E N S E
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*----------------------------------------------------------------------------------------
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* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as published by the Free
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* Software Foundation, either version 3 of the License, or (at your option) any later
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* version.
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*
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* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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* PURPOSE. See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along with OpenBLT.
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* If not, see <http://www.gnu.org/licenses/>.
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*
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* A special exception to the GPL is included to allow you to distribute a combined work
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* that includes OpenBLT without being obliged to provide the source code for any
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* proprietary components. The exception text is included at the bottom of the license
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* file <license.html>.
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*
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* \endinternal
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****************************************************************************************/
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/****************************************************************************************
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* Include files
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****************************************************************************************/
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#include "boot.h" /* bootloader generic header */ |
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#if (BOOT_COM_CAN_ENABLE > 0 || BOOT_GATE_CAN_ENABLE > 0) |
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/****************************************************************************************
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* Type definitions
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****************************************************************************************/
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/** \brief CAN transmission mailbox layout. */
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typedef struct |
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{
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volatile blt_int32u TIR;
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volatile blt_int32u TDTR;
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volatile blt_int32u TDLR;
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volatile blt_int32u TDHR;
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} tCanTxMailBox; |
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/** \brief CAN reception FIFO mailbox layout. */
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typedef struct |
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{
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volatile blt_int32u RIR;
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volatile blt_int32u RDTR;
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volatile blt_int32u RDLR;
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volatile blt_int32u RDHR;
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} tCanRxFIFOMailBox; |
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/** \brief CAN filter register layout. */
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typedef struct |
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{
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volatile blt_int32u FR1;
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volatile blt_int32u FR2;
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} tCanFilter; |
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/** \brief CAN controller register layout. */
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typedef struct |
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{
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volatile blt_int32u MCR;
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volatile blt_int32u MSR;
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volatile blt_int32u TSR;
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volatile blt_int32u RF0R;
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volatile blt_int32u RF1R;
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volatile blt_int32u IER;
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volatile blt_int32u ESR;
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volatile blt_int32u BTR;
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blt_int32u RESERVED0[88];
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tCanTxMailBox sTxMailBox[3];
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tCanRxFIFOMailBox sFIFOMailBox[2];
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blt_int32u RESERVED1[12];
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volatile blt_int32u FMR;
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volatile blt_int32u FM1R;
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blt_int32u RESERVED2; |
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volatile blt_int32u FS1R;
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blt_int32u RESERVED3; |
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volatile blt_int32u FFA1R;
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blt_int32u RESERVED4; |
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volatile blt_int32u FA1R;
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blt_int32u RESERVED5[8];
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tCanFilter sFilterRegister[28];
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} tCanRegs; |
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/****************************************************************************************
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* Macro definitions
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****************************************************************************************/
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/** \brief Reset request bit. */
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#define CAN_BIT_RESET ((blt_int32u)0x00008000) |
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/** \brief Initialization request bit. */
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#define CAN_BIT_INRQ ((blt_int32u)0x00000001) |
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/** \brief Initialization acknowledge bit. */
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#define CAN_BIT_INAK ((blt_int32u)0x00000001) |
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/** \brief Sleep mode request bit. */
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#define CAN_BIT_SLEEP ((blt_int32u)0x00000002) |
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/** \brief Filter 0 selection bit. */
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#define CAN_BIT_FILTER0 ((blt_int32u)0x00000001) |
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/** \brief Filter 14 selection bit. */
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#define CAN_BIT_FILTER14 ((blt_int32u)0x00004000) |
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/** \brief Filter init mode bit. */
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#define CAN_BIT_FINIT ((blt_int32u)0x00000001) |
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/** \brief Transmit mailbox 0 empty bit. */
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#define CAN_BIT_TME0 ((blt_int32u)0x04000000) |
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/** \brief Transmit mailbox request bit. */
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#define CAN_BIT_TXRQ ((blt_int32u)0x00000001) |
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/** \brief Release FIFO 0 mailbox bit. */
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#define CAN_BIT_RFOM0 ((blt_int32u)0x00000020) |
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#if (BOOT_GATE_CAN_ENABLE > 0) |
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blt_bool commandSend; |
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#endif /* BOOT_GATE_CAN_ENABLE > 0 */ |
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/****************************************************************************************
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* Register definitions
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****************************************************************************************/
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#if (BOOT_COM_CAN_CHANNEL_INDEX == 0) |
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/** \brief Macro for accessing CAN1 controller registers. */
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#define CANx ((tCanRegs *) (blt_int32u)0x40006400) |
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#else
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/** \brief Macro for accessing CAN2 controller registers. */
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#define CANx ((tCanRegs *) (blt_int32u)0x40006800) |
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#endif
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/** \brief Macro for accessing CAN1 controller registers. */
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#define CAN1 ((tCanRegs *) (blt_int32u)0x40006400) |
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/****************************************************************************************
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* Type definitions
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****************************************************************************************/
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/** \brief Structure type for grouping CAN bus timing related information. */
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typedef struct t_can_bus_timing |
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{
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blt_int8u tseg1; /**< CAN time segment 1 */
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blt_int8u tseg2; /**< CAN time segment 2 */
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} tCanBusTiming; |
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/****************************************************************************************
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* Local constant declarations
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****************************************************************************************/
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/** \brief CAN bittiming table for dynamically calculating the bittiming settings.
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* \details According to the CAN protocol 1 bit-time can be made up of between 8..25
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* time quanta (TQ). The total TQ in a bit is SYNC + TSEG1 + TSEG2 with SYNC
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* always being 1. The sample point is (SYNC + TSEG1) / (SYNC + TSEG1 + SEG2) *
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* 100%. This array contains possible and valid time quanta configurations with
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* a sample point between 68..78%.
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*/
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static const tCanBusTiming canTiming[] = |
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{ /* TQ | TSEG1 | TSEG2 | SP */
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/* ------------------------- */
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{ 5, 2 }, /* 8 | 5 | 2 | 75% */
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{ 6, 2 }, /* 9 | 6 | 2 | 78% */
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{ 6, 3 }, /* 10 | 6 | 3 | 70% */
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{ 7, 3 }, /* 11 | 7 | 3 | 73% */
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{ 8, 3 }, /* 12 | 8 | 3 | 75% */
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{ 9, 3 }, /* 13 | 9 | 3 | 77% */
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{ 9, 4 }, /* 14 | 9 | 4 | 71% */
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{ 10, 4 }, /* 15 | 10 | 4 | 73% */
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{ 11, 4 }, /* 16 | 11 | 4 | 75% */
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{ 12, 4 }, /* 17 | 12 | 4 | 76% */
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{ 12, 5 }, /* 18 | 12 | 5 | 72% */
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{ 13, 5 }, /* 19 | 13 | 5 | 74% */
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{ 14, 5 }, /* 20 | 14 | 5 | 75% */
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{ 15, 5 }, /* 21 | 15 | 5 | 76% */
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{ 15, 6 }, /* 22 | 15 | 6 | 73% */
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{ 16, 6 }, /* 23 | 16 | 6 | 74% */
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{ 16, 7 }, /* 24 | 16 | 7 | 71% */
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{ 16, 8 } /* 25 | 16 | 8 | 68% */
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}; |
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int counter = 0; |
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/************************************************************************************//** |
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** \brief Search algorithm to match the desired baudrate to a possible bus
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** timing configuration.
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** \param baud The desired baudrate in kbps. Valid values are 10..1000.
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** \param prescaler Pointer to where the value for the prescaler will be stored.
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** \param tseg1 Pointer to where the value for TSEG2 will be stored.
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** \param tseg2 Pointer to where the value for TSEG2 will be stored.
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** \return BLT_TRUE if the CAN bustiming register values were found, BLT_FALSE
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** otherwise.
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**
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****************************************************************************************/
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static blt_bool CanGetSpeedConfig(blt_int16u baud, blt_int16u *prescaler,
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blt_int8u *tseg1, blt_int8u *tseg2) |
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{
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blt_int8u cnt; |
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/* loop through all possible time quanta configurations to find a match */
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for (cnt=0; cnt < sizeof(canTiming)/sizeof(canTiming[0]); cnt++) |
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{
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if (((BOOT_CPU_SYSTEM_SPEED_KHZ/4) % (baud*(canTiming[cnt].tseg1+canTiming[cnt].tseg2+1))) == 0) |
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{
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/* compute the prescaler that goes with this TQ configuration */
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*prescaler = (BOOT_CPU_SYSTEM_SPEED_KHZ/4)/(baud*(canTiming[cnt].tseg1+canTiming[cnt].tseg2+1)); |
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/* make sure the prescaler is valid */
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if ( (*prescaler > 0) && (*prescaler <= 1024) ) |
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{
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/* store the bustiming configuration */
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*tseg1 = canTiming[cnt].tseg1; |
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*tseg2 = canTiming[cnt].tseg2; |
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/* found a good bus timing configuration */
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return BLT_TRUE;
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} |
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} |
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} |
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/* could not find a good bus timing configuration */
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return BLT_FALSE;
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} /*** end of CanGetSpeedConfig ***/
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/************************************************************************************//** |
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** \brief Initializes the CAN controller and synchronizes it to the CAN bus.
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** \return none.
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**
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****************************************************************************************/
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void CanInit(void) |
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{
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blt_int16u prescaler; |
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blt_int8u tseg1, tseg2; |
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blt_bool result; |
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#if (BOOT_GATE_CAN_ENABLE > 0) |
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commandSend = BLT_FALSE; |
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#endif /* BOOT_GATE_CAN_ENABLE > 0 */ |
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/* the current implementation supports CAN1 and 2. throw an assertion error in case a
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* different CAN channel is configured.
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*/
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ASSERT_CT((BOOT_COM_CAN_CHANNEL_INDEX == 0 || BOOT_COM_CAN_CHANNEL_INDEX == 1)); |
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/* obtain bittiming configuration information */
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result = CanGetSpeedConfig(BOOT_COM_CAN_BAUDRATE/1000, &prescaler, &tseg1, &tseg2);
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ASSERT_RT(result == BLT_TRUE); |
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/* disable all can interrupt. this driver works in polling mode */
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CANx->IER = (blt_int32u)0;
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/* set request to reset the can controller */
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CANx->MCR |= CAN_BIT_RESET ; |
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/* wait for acknowledge that the can controller was reset */
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while ((CANx->MCR & CAN_BIT_RESET) != 0) |
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{
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/* keep the watchdog happy */
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CopService(); |
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} |
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/* exit from sleep mode, which is the default mode after reset */
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CANx->MCR &= ~CAN_BIT_SLEEP; |
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/* set request to enter initialisation mode */
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CANx->MCR |= CAN_BIT_INRQ ; |
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/* wait for acknowledge that initialization mode was entered */
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while ((CANx->MSR & CAN_BIT_INAK) == 0) |
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{
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/* keep the watchdog happy */
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CopService(); |
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} |
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/* configure the bittming */
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CANx->BTR = (blt_int32u)((blt_int32u)(3) << 24) | \ |
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(blt_int32u)((blt_int32u)(tseg1 - 1) << 16) | \ |
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(blt_int32u)((blt_int32u)(tseg2 - 1) << 20) | \ |
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(blt_int32u)(prescaler - 1);
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// CANx->BTR = (blt_int32u)((blt_int32u)(tseg1 - 1) << 16) | \
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(blt_int32u)((blt_int32u)(tseg2 - 1) << 20) | \
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(blt_int32u)(prescaler - 1) | \
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(blt_int32u)(0x3 << 30);
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// CANx->BTR = (blt_int32u)((blt_int32u)(15) << 16) | \
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(blt_int32u)((blt_int32u)(3) << 20) | \
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(blt_int32u)((blt_int32u)(1) << 24) | \
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(blt_int32u)(1) | \
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(blt_int32u)(0x3 << 30);
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/* set request to leave initialisation mode */
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CANx->MCR &= ~CAN_BIT_INRQ; |
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/* wait for acknowledge that initialization mode was exited */
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while ((CANx->MSR & CAN_BIT_INAK) != 0) |
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{
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/* keep the watchdog happy */
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CopService(); |
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} |
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#if (BOOT_COM_CAN_CHANNEL_INDEX == 0) |
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/* enter initialisation mode for the acceptance filter */
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CAN1->FMR |= CAN_BIT_FINIT; |
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/* deactivate filter 0 */
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CAN1->FA1R &= ~CAN_BIT_FILTER0; |
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/* 32-bit scale for the filter */
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CAN1->FS1R |= CAN_BIT_FILTER0; |
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/* open up the acceptance filter to receive all messages */
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CAN1->sFilterRegister[0].FR1 = 0; |
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CAN1->sFilterRegister[0].FR2 = 0; |
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/* select id/mask mode for the filter */
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CAN1->FM1R &= ~CAN_BIT_FILTER0; |
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/* FIFO 0 assignation for the filter */
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CAN1->FFA1R &= ~CAN_BIT_FILTER0; |
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/* filter activation */
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CAN1->FA1R |= CAN_BIT_FILTER0; |
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/* leave initialisation mode for the acceptance filter */
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CAN1->FMR &= ~CAN_BIT_FINIT; |
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#else
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/* enter initialisation mode for the acceptance filter */
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CAN1->FMR |= CAN_BIT_FINIT; |
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/* deactivate filter 14 */
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CAN1->FA1R &= ~CAN_BIT_FILTER14; |
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/* 32-bit scale for the filter */
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CAN1->FS1R |= CAN_BIT_FILTER14; |
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/* open up the acceptance filter to receive all messages */
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CAN1->sFilterRegister[14].FR1 = 0; |
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CAN1->sFilterRegister[14].FR2 = 0; |
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/* select id/mask mode for the filter */
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CAN1->FM1R &= ~CAN_BIT_FILTER14; |
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/* FIFO 0 assignation for the filter */
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CAN1->FFA1R &= ~CAN_BIT_FILTER14; |
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/* filter activation */
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CAN1->FA1R |= CAN_BIT_FILTER14; |
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/* leave initialisation mode for the acceptance filter */
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CAN1->FMR &= ~CAN_BIT_FINIT; |
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#endif
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} /*** end of CanInit ***/
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/************************************************************************************//** |
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** \brief Transmits a packet formatted for the communication interface.
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** \param data Pointer to byte array with data that it to be transmitted.
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** \param len Number of bytes that are to be transmitted.
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** \return none.
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**
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****************************************************************************************/
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void CanTransmitPacket(blt_int8u *data, blt_int8u len, blt_int8u deviceID)
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{
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/* make sure that transmit mailbox 0 is available */
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ASSERT_RT((CANx->TSR&CAN_BIT_TME0) == CAN_BIT_TME0); |
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/* store the 11-bit message identifier */
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CANx->sTxMailBox[0].TIR &= CAN_BIT_TXRQ;
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blt_int32u address; |
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#if (BOOT_GATE_CAN_ENABLE > 0) |
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if (deviceID == 0) { |
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#endif /* BOOT_GATE_CAN_ENABLE > 0 */ |
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address = (blt_int32u)BOOT_COM_CAN_TX_MSG_ID; |
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#if (BOOT_GATE_CAN_ENABLE > 0) |
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commandSend = BLT_FALSE; |
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} else {
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address = ((blt_int32u)BOOT_COM_CAN_RX_MSG_ID | (blt_int32u)deviceID); |
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commandSend = BLT_TRUE; |
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} |
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#endif /* BOOT_GATE_CAN_ENABLE > 0 */ |
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/* init variables */
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blt_int8u canData[8];
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blt_int8u restLen = len; |
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blt_int8u canIdx = 0;
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/* send the given package in 8 byte packages */
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while (restLen > 0) { |
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CANx->sTxMailBox[0].TIR |= (address << 21); |
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/* store the message date length code (DLC) */
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if (restLen > 7) { |
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CANx->sTxMailBox[0].TDTR = 8; |
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} else {
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CANx->sTxMailBox[0].TDTR = restLen+1; |
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} |
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/* Load max 8 bytes into message data bytes */
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canData[0] = restLen;
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canIdx = 1;
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while (restLen > 0 && canIdx < 8) { |
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canData[canIdx] = data[len-restLen]; |
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canIdx++; |
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restLen--; |
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} |
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/* fill rest with nulls */
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while (canIdx < 8) { |
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canData[canIdx] = 0;
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canIdx++; |
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} |
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/* store the message data bytes */
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CANx->sTxMailBox[0].TDLR = (((blt_int32u)canData[3] << 24) | \ |
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((blt_int32u)canData[2] << 16) | \ |
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((blt_int32u)canData[1] << 8) | \ |
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((blt_int32u)canData[0]));
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CANx->sTxMailBox[0].TDHR = (((blt_int32u)canData[7] << 24) | \ |
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((blt_int32u)canData[6] << 16) | \ |
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((blt_int32u)canData[5] << 8) | \ |
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((blt_int32u)canData[4]));
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/* request the start of message transmission */
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CANx->sTxMailBox[0].TIR |= CAN_BIT_TXRQ;
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/* wait for transmit completion */
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while ((CANx->TSR&CAN_BIT_TME0) == 0) |
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{
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/* keep the watchdog happy */
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CopService(); |
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} |
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} |
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} /*** end of CanTransmitSinglePacket ***/
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/************************************************************************************//** |
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** \brief Transmits many packets formatted for the communication interface.
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** \param data Pointer to byte array with data that it to be transmitted.
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** \param len Number of bytes that are to be transmitted.
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** \return none.
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**
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****************************************************************************************/
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| 417 |
/*void CanTransmitPacket(blt_int8u *data, blt_int8u len, blt_int8u deviceID)
|
| 418 |
{
|
| 419 |
static blt_int8u canPacketData[8];
|
| 420 |
|
| 421 |
canPacketData[0] = len;
|
| 422 |
blt_int8u restLength = len;
|
| 423 |
while (restLength > 0) {
|
| 424 |
blt_int8u canIdx = 0;
|
| 425 |
if (restLength == len) {
|
| 426 |
canIdx = 1;
|
| 427 |
}
|
| 428 |
|
| 429 |
/* while (restLength > 0 && canIdx < 8) {
|
| 430 |
canPacketData[canIdx] = data[len-restLength];
|
| 431 |
canIdx++;
|
| 432 |
restLength--;
|
| 433 |
}*/
|
| 434 |
/* blt_int8u dataLength = 8;
|
| 435 |
if (dataLength > restLength) {
|
| 436 |
dataLength = restLength;
|
| 437 |
}
|
| 438 |
CpuMemCopy((blt_int32u)&canPacketData[1], (blt_int32u)&data[], toReceive);
|
| 439 |
|
| 440 |
CanTransmitSinglePacket(canPacketData, canIdx, deviceID);
|
| 441 |
}
|
| 442 |
} /*** end of CanTransmitPacket ***/
|
| 443 |
|
| 444 |
|
| 445 |
/************************************************************************************//** |
| 446 |
** \brief Receives a communication interface packet if one is present.
|
| 447 |
** \param data Pointer to byte array where the data is to be stored.
|
| 448 |
** \return Length of message (if the message is invalid, the length will be 0).
|
| 449 |
**
|
| 450 |
****************************************************************************************/
|
| 451 |
blt_int8u CanReceivePacket(blt_int8u *data) |
| 452 |
{
|
| 453 |
blt_int32u rxMsgId; |
| 454 |
blt_bool result = BLT_FALSE; |
| 455 |
blt_int8u length = 0;
|
| 456 |
|
| 457 |
static blt_int8u readData[BOOT_COM_RX_MAX_DATA];
|
| 458 |
static blt_int8u receivedLen = 0; |
| 459 |
static blt_int8u lastLen = 0; |
| 460 |
static blt_int8u toReceive = 0; |
| 461 |
blt_int8u canData[8];
|
| 462 |
blt_int8u restLen; |
| 463 |
blt_int8u canLength; |
| 464 |
|
| 465 |
/* check if a new message was received */
|
| 466 |
if ((CANx->RF0R&(blt_int32u)0x00000003) > 0) |
| 467 |
{
|
| 468 |
/* read out the message identifier */
|
| 469 |
rxMsgId = (blt_int32u)0x000007FF & (CANx->sFIFOMailBox[0].RIR >> 21); |
| 470 |
/* is this the packet identifier */
|
| 471 |
|
| 472 |
blt_int32u compID; |
| 473 |
#if (BOOT_GATE_CAN_ENABLE > 0) |
| 474 |
if (commandSend == BLT_TRUE) {
|
| 475 |
compID = (blt_int32u)BOOT_COM_CAN_TX_MSG_ID; |
| 476 |
} else {
|
| 477 |
#endif /* BOOT_GATE_CAN_ENABLE > 0 */ |
| 478 |
compID = (blt_int32u)BOOT_COM_CAN_RX_MSG_ID | (blt_int32u)BOOT_COM_DEVICE_ID; |
| 479 |
#if (BOOT_GATE_CAN_ENABLE > 0) |
| 480 |
} |
| 481 |
#endif /* BOOT_GATE_CAN_ENABLE > 0 */ |
| 482 |
|
| 483 |
if (rxMsgId == compID)
|
| 484 |
{
|
| 485 |
#if (BOOT_GATE_CAN_ENABLE > 0) |
| 486 |
commandSend = BLT_FALSE; |
| 487 |
#endif /* BOOT_GATE_CAN_ENABLE > 0 */ |
| 488 |
result = BLT_TRUE; |
| 489 |
|
| 490 |
/* save length */
|
| 491 |
canLength = (blt_int8u)0x0F & CANx->sFIFOMailBox[0].RDTR; |
| 492 |
/* store the received packet data */
|
| 493 |
canData[0] = (blt_int8u)0xFF & CANx->sFIFOMailBox[0].RDLR; |
| 494 |
canData[1] = (blt_int8u)0xFF & (CANx->sFIFOMailBox[0].RDLR >> 8); |
| 495 |
canData[2] = (blt_int8u)0xFF & (CANx->sFIFOMailBox[0].RDLR >> 16); |
| 496 |
canData[3] = (blt_int8u)0xFF & (CANx->sFIFOMailBox[0].RDLR >> 24); |
| 497 |
canData[4] = (blt_int8u)0xFF & CANx->sFIFOMailBox[0].RDHR; |
| 498 |
canData[5] = (blt_int8u)0xFF & (CANx->sFIFOMailBox[0].RDHR >> 8); |
| 499 |
canData[6] = (blt_int8u)0xFF & (CANx->sFIFOMailBox[0].RDHR >> 16); |
| 500 |
canData[7] = (blt_int8u)0xFF & (CANx->sFIFOMailBox[0].RDHR >> 24); |
| 501 |
|
| 502 |
/* Store rest length of package and check if possible */
|
| 503 |
if (receivedLen == 0) { |
| 504 |
toReceive = canData[0];
|
| 505 |
lastLen = canData[0];
|
| 506 |
} else {
|
| 507 |
restLen = canData[0];
|
| 508 |
if (lastLen-restLen != 7) { |
| 509 |
// package has been lost - but nothing happens
|
| 510 |
} |
| 511 |
lastLen = restLen; |
| 512 |
} |
| 513 |
|
| 514 |
/* store data in data package */
|
| 515 |
blt_int8u idx; |
| 516 |
for (idx=1; idx < canLength; idx++) { |
| 517 |
readData[receivedLen] = canData[idx]; |
| 518 |
receivedLen++; |
| 519 |
} |
| 520 |
|
| 521 |
/* check if full package has been received */
|
| 522 |
if (receivedLen >= toReceive) {
|
| 523 |
receivedLen = 0;
|
| 524 |
for (idx = 0; idx < toReceive; idx++) { |
| 525 |
data[idx] = readData[idx]; |
| 526 |
} |
| 527 |
length = toReceive; |
| 528 |
} else {
|
| 529 |
length = 0;
|
| 530 |
} |
| 531 |
} |
| 532 |
/* release FIFO0 */
|
| 533 |
CANx->RF0R |= CAN_BIT_RFOM0; |
| 534 |
} |
| 535 |
return length;
|
| 536 |
} /*** end of CanReceiveSinglePacket ***/
|
| 537 |
|
| 538 |
|
| 539 |
/************************************************************************************//** |
| 540 |
** \brief Receives some communication interface packets if they are present.
|
| 541 |
** \param data Pointer to byte array where the data is to be stored.
|
| 542 |
** \return Length of message (if the message is invalid, the length will be 0).
|
| 543 |
**
|
| 544 |
****************************************************************************************/
|
| 545 |
#if (0) |
| 546 |
blt_int8u CanReceivePacket(blt_int8u *data) |
| 547 |
{
|
| 548 |
static blt_int8u canPacketData[8]; |
| 549 |
static blt_int8u canData[BOOT_COM_RX_MAX_DATA];
|
| 550 |
static blt_int8u receivedLength = 0; |
| 551 |
static blt_int8u toReceive = 0; |
| 552 |
|
| 553 |
// get CAN packet
|
| 554 |
blt_int8u len = CanReceiveSinglePacket(canPacketData); |
| 555 |
|
| 556 |
// check, if packet has been received
|
| 557 |
if (len == 0) { |
| 558 |
return 0; |
| 559 |
} |
| 560 |
|
| 561 |
// if it's the first packet of a flow, save data length
|
| 562 |
blt_int8u startRead = 0;
|
| 563 |
if (receivedLength == 0) { |
| 564 |
toReceive = canPacketData[0];
|
| 565 |
startRead = 1;
|
| 566 |
} |
| 567 |
|
| 568 |
// copy CAN packet data into complete data packet
|
| 569 |
blt_int8u canIdx = 0;
|
| 570 |
while (receivedLength < toReceive && canIdx < 8) { |
| 571 |
canData[receivedLength] = canPacketData[canIdx]; |
| 572 |
receivedLength++; |
| 573 |
canIdx++; |
| 574 |
} |
| 575 |
|
| 576 |
// check, if data packet is finished
|
| 577 |
if (receivedLength == toReceive) {
|
| 578 |
receivedLength = 0;
|
| 579 |
CpuMemCopy((blt_int32u)data, (blt_int32u)&canData[0], toReceive);
|
| 580 |
return toReceive;
|
| 581 |
} else {
|
| 582 |
return 0; |
| 583 |
} |
| 584 |
|
| 585 |
|
| 586 |
} /*** end of CanReceivePacket ***/
|
| 587 |
#endif
|
| 588 |
#endif /* BOOT_COM_CAN_ENABLE > 0 || BOOT_GATE_CAN_ENABLE > 0 */ |
| 589 |
|
| 590 |
|
| 591 |
/*********************************** end of can.c **************************************/
|