Statistics
| Branch: | Tag: | Revision:

amiro-blt / Target / Modules / DiWheelDrive_1-1 / Boot / lib / CMSIS / CM3 / DeviceSupport / ST / STM32F10x / startup / TrueSTUDIO / startup_stm32f10x_hd_vl.s @ 367c0652

History | View | Annotate | Download (12 KB)

1 69661903 Thomas Schöpping
/**
2
  ******************************************************************************
3
  * @file      startup_stm32f10x_hd_vl.s
4
  * @author    MCD Application Team
5
  * @version   V3.5.0
6
  * @date      11-March-2011
7
  * @brief     STM32F10x High Density Value Line Devices vector table for Atollic 
8
  *            toolchain.
9
  *            This module performs:
10
  *                - Set the initial SP
11
  *                - Set the initial PC == Reset_Handler,
12
  *                - Set the vector table entries with the exceptions ISR address
13
  *                - Configure the clock system  
14
  *                - Configure external SRAM mounted on STM32100E-EVAL board
15
  *                  to be used as data memory (optional, to be enabled by user)   
16
  *                - Branches to main in the C library (which eventually
17
  *                  calls main()).
18
  *            After Reset the Cortex-M3 processor is in Thread mode,
19
  *            priority is Privileged, and the Stack is set to Main.
20
  ******************************************************************************
21
  * @attention
22
  *
23
  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
24
  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
25
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
26
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
27
  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
28
  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
29
  *
30
  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
31
  ******************************************************************************
32
  */
33
34
  .syntax unified
35
	.cpu cortex-m3
36
	.fpu softvfp
37
	.thumb
38
39
.global	g_pfnVectors
40
.global	Default_Handler
41
42
/* start address for the initialization values of the .data section.
43
defined in linker script */
44
.word	_sidata
45
/* start address for the .data section. defined in linker script */
46
.word	_sdata
47
/* end address for the .data section. defined in linker script */
48
.word	_edata
49
/* start address for the .bss section. defined in linker script */
50
.word	_sbss
51
/* end address for the .bss section. defined in linker script */
52
.word	_ebss
53
54
.equ  BootRAM, 0xF108F85F
55
/**
56
 * @brief  This is the code that gets called when the processor first
57
 *          starts execution following a reset event. Only the absolutely
58
 *          necessary set is performed, after which the application
59
 *          supplied main() routine is called.
60
 * @param  None
61
 * @retval : None
62
*/
63
64
    .section	.text.Reset_Handler
65
	.weak	Reset_Handler
66
	.type	Reset_Handler, %function
67
Reset_Handler:
68
69
/* Copy the data segment initializers from flash to SRAM */
70
  movs	r1, #0
71
  b	LoopCopyDataInit
72
73
CopyDataInit:
74
	ldr	r3, =_sidata
75
	ldr	r3, [r3, r1]
76
	str	r3, [r0, r1]
77
	adds	r1, r1, #4
78
79
LoopCopyDataInit:
80
	ldr	r0, =_sdata
81
	ldr	r3, =_edata
82
	adds	r2, r0, r1
83
	cmp	r2, r3
84
	bcc	CopyDataInit
85
	ldr	r2, =_sbss
86
	b	LoopFillZerobss
87
/* Zero fill the bss segment. */
88
FillZerobss:
89
	movs	r3, #0
90
	str	r3, [r2], #4
91
92
LoopFillZerobss:
93
	ldr	r3, = _ebss
94
	cmp	r2, r3
95
	bcc	FillZerobss
96
	
97
/* Call the clock system intitialization function.*/
98
  bl  SystemInit 
99
/* Call static constructors */
100
  bl __libc_init_array  
101
/* Call the application's entry point.*/
102
	bl	main
103
	bx	lr
104
.size	Reset_Handler, .-Reset_Handler
105
106
/**
107
 * @brief  This is the code that gets called when the processor receives an
108
 *         unexpected interrupt.  This simply enters an infinite loop, preserving
109
 *         the system state for examination by a debugger.
110
 *
111
 * @param  None
112
 * @retval : None
113
*/
114
    .section	.text.Default_Handler,"ax",%progbits
115
Default_Handler:
116
Infinite_Loop:
117
	b	Infinite_Loop
118
	.size	Default_Handler, .-Default_Handler
119
/******************************************************************************
120
*
121
* The minimal vector table for a Cortex M3.  Note that the proper constructs
122
* must be placed on this to ensure that it ends up at physical address
123
* 0x0000.0000.
124
*
125
******************************************************************************/
126
 	.section	.isr_vector,"a",%progbits
127
	.type	g_pfnVectors, %object
128
	.size	g_pfnVectors, .-g_pfnVectors
129
130
131
g_pfnVectors:
132
	.word	_estack
133
	.word	Reset_Handler
134
	.word	NMI_Handler
135
	.word	HardFault_Handler
136
	.word	MemManage_Handler
137
	.word	BusFault_Handler
138
	.word	UsageFault_Handler
139
	.word	0
140
	.word	0
141
	.word	0
142
	.word	0
143
	.word	SVC_Handler
144
	.word	DebugMon_Handler
145
	.word	0
146
	.word	PendSV_Handler
147
	.word	SysTick_Handler
148
	.word	WWDG_IRQHandler
149
	.word	PVD_IRQHandler
150
	.word	TAMPER_IRQHandler
151
	.word	RTC_IRQHandler
152
	.word	FLASH_IRQHandler
153
	.word	RCC_IRQHandler
154
	.word	EXTI0_IRQHandler
155
	.word	EXTI1_IRQHandler
156
	.word	EXTI2_IRQHandler
157
	.word	EXTI3_IRQHandler
158
	.word	EXTI4_IRQHandler
159
	.word	DMA1_Channel1_IRQHandler
160
	.word	DMA1_Channel2_IRQHandler
161
	.word	DMA1_Channel3_IRQHandler
162
	.word	DMA1_Channel4_IRQHandler
163
	.word	DMA1_Channel5_IRQHandler
164
	.word	DMA1_Channel6_IRQHandler
165
	.word	DMA1_Channel7_IRQHandler
166
	.word	ADC1_IRQHandler
167
	.word	0
168
	.word	0
169
	.word	0
170
	.word	0
171
	.word	EXTI9_5_IRQHandler
172
	.word	TIM1_BRK_TIM15_IRQHandler
173
	.word	TIM1_UP_TIM16_IRQHandler
174
	.word	TIM1_TRG_COM_TIM17_IRQHandler
175
	.word	TIM1_CC_IRQHandler
176
	.word	TIM2_IRQHandler
177
	.word	TIM3_IRQHandler
178
	.word	TIM4_IRQHandler
179
	.word	I2C1_EV_IRQHandler
180
	.word	I2C1_ER_IRQHandler
181
	.word	I2C2_EV_IRQHandler
182
	.word	I2C2_ER_IRQHandler
183
	.word	SPI1_IRQHandler
184
	.word	SPI2_IRQHandler
185
	.word	USART1_IRQHandler
186
	.word	USART2_IRQHandler
187
	.word	USART3_IRQHandler
188
	.word	EXTI15_10_IRQHandler
189
	.word	RTCAlarm_IRQHandler
190
	.word	CEC_IRQHandler
191
  .word TIM12_IRQHandler
192
  .word TIM13_IRQHandler
193
  .word TIM14_IRQHandler
194
  .word 0
195
  .word 0
196
  .word 0
197
  .word 0
198
  .word TIM5_IRQHandler
199
  .word SPI3_IRQHandler
200
  .word UART4_IRQHandler
201
  .word UART5_IRQHandler
202
  .word TIM6_DAC_IRQHandler
203
  .word TIM7_IRQHandler  
204
  .word DMA2_Channel1_IRQHandler
205
  .word DMA2_Channel2_IRQHandler
206
  .word DMA2_Channel3_IRQHandler
207
  .word DMA2_Channel4_5_IRQHandler
208
  .word DMA2_Channel5_IRQHandler
209
  .word 0
210
  .word 0
211
  .word 0
212
  .word 0
213
  .word 0
214
  .word 0
215
  .word 0
216
  .word 0
217
  .word 0
218
  .word 0
219
  .word 0
220
  .word 0
221
  .word 0
222
  .word 0
223
  .word 0
224
  .word 0
225
  .word 0
226
  .word 0
227
  .word 0
228
  .word 0
229
  .word 0
230
  .word 0
231
  .word 0
232
  .word 0
233
  .word 0
234
  .word 0
235
  .word 0
236
  .word 0
237
  .word 0
238
  .word 0
239
  .word 0
240
  .word 0
241
  .word 0
242
  .word 0
243
  .word 0
244
  .word 0
245
  .word 0
246
  .word 0
247
  .word 0
248
  .word 0
249
  .word 0
250
  .word 0
251
  .word 0
252
  .word  BootRAM       /* @0x1E0. This is for boot in RAM mode for 
253
                         STM32F10x High Density Value line devices. */
254
255
/*******************************************************************************
256
*
257
* Provide weak aliases for each Exception handler to the Default_Handler.
258
* As they are weak aliases, any function with the same name will override
259
* this definition.
260
*
261
*******************************************************************************/
262
263
    
264
  .weak  NMI_Handler
265
  .thumb_set NMI_Handler,Default_Handler
266
  
267
  .weak  HardFault_Handler
268
  .thumb_set HardFault_Handler,Default_Handler
269
  
270
  .weak  MemManage_Handler
271
  .thumb_set MemManage_Handler,Default_Handler
272
  
273
  .weak  BusFault_Handler
274
  .thumb_set BusFault_Handler,Default_Handler
275
276
  .weak  UsageFault_Handler
277
  .thumb_set UsageFault_Handler,Default_Handler
278
279
  .weak  SVC_Handler
280
  .thumb_set SVC_Handler,Default_Handler
281
282
  .weak  DebugMon_Handler
283
  .thumb_set DebugMon_Handler,Default_Handler
284
285
  .weak  PendSV_Handler
286
  .thumb_set PendSV_Handler,Default_Handler
287
288
  .weak  SysTick_Handler
289
  .thumb_set SysTick_Handler,Default_Handler
290
291
  .weak  WWDG_IRQHandler
292
  .thumb_set WWDG_IRQHandler,Default_Handler
293
294
  .weak  PVD_IRQHandler
295
  .thumb_set PVD_IRQHandler,Default_Handler
296
297
  .weak  TAMPER_IRQHandler
298
  .thumb_set TAMPER_IRQHandler,Default_Handler
299
300
  .weak  RTC_IRQHandler
301
  .thumb_set RTC_IRQHandler,Default_Handler
302
303
  .weak  FLASH_IRQHandler
304
  .thumb_set FLASH_IRQHandler,Default_Handler
305
306
  .weak  RCC_IRQHandler
307
  .thumb_set RCC_IRQHandler,Default_Handler
308
309
  .weak  EXTI0_IRQHandler
310
  .thumb_set EXTI0_IRQHandler,Default_Handler
311
312
  .weak  EXTI1_IRQHandler
313
  .thumb_set EXTI1_IRQHandler,Default_Handler
314
315
  .weak  EXTI2_IRQHandler
316
  .thumb_set EXTI2_IRQHandler,Default_Handler
317
318
  .weak  EXTI3_IRQHandler
319
  .thumb_set EXTI3_IRQHandler,Default_Handler
320
321
  .weak  EXTI4_IRQHandler
322
  .thumb_set EXTI4_IRQHandler,Default_Handler
323
324
  .weak  DMA1_Channel1_IRQHandler
325
  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
326
327
  .weak  DMA1_Channel2_IRQHandler
328
  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
329
330
  .weak  DMA1_Channel3_IRQHandler
331
  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
332
333
  .weak  DMA1_Channel4_IRQHandler
334
  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
335
336
  .weak  DMA1_Channel5_IRQHandler
337
  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
338
339
  .weak  DMA1_Channel6_IRQHandler
340
  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
341
342
  .weak  DMA1_Channel7_IRQHandler
343
  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
344
345
  .weak  ADC1_IRQHandler
346
  .thumb_set ADC1_IRQHandler,Default_Handler
347
348
  .weak  EXTI9_5_IRQHandler
349
  .thumb_set EXTI9_5_IRQHandler,Default_Handler
350
351
  .weak  TIM1_BRK_TIM15_IRQHandler
352
  .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
353
354
  .weak  TIM1_UP_TIM16_IRQHandler
355
  .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
356
357
  .weak  TIM1_TRG_COM_TIM17_IRQHandler
358
  .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
359
360
  .weak  TIM1_CC_IRQHandler
361
  .thumb_set TIM1_CC_IRQHandler,Default_Handler
362
363
  .weak  TIM2_IRQHandler
364
  .thumb_set TIM2_IRQHandler,Default_Handler
365
366
  .weak  TIM3_IRQHandler
367
  .thumb_set TIM3_IRQHandler,Default_Handler
368
369
  .weak  TIM4_IRQHandler
370
  .thumb_set TIM4_IRQHandler,Default_Handler
371
372
  .weak  I2C1_EV_IRQHandler
373
  .thumb_set I2C1_EV_IRQHandler,Default_Handler
374
375
  .weak  I2C1_ER_IRQHandler
376
  .thumb_set I2C1_ER_IRQHandler,Default_Handler
377
378
  .weak  I2C2_EV_IRQHandler
379
  .thumb_set I2C2_EV_IRQHandler,Default_Handler
380
381
  .weak  I2C2_ER_IRQHandler
382
  .thumb_set I2C2_ER_IRQHandler,Default_Handler
383
384
  .weak  SPI1_IRQHandler
385
  .thumb_set SPI1_IRQHandler,Default_Handler
386
387
  .weak  SPI2_IRQHandler
388
  .thumb_set SPI2_IRQHandler,Default_Handler
389
390
  .weak  USART1_IRQHandler
391
  .thumb_set USART1_IRQHandler,Default_Handler
392
393
  .weak  USART2_IRQHandler
394
  .thumb_set USART2_IRQHandler,Default_Handler
395
396
  .weak  USART3_IRQHandler
397
  .thumb_set USART3_IRQHandler,Default_Handler
398
399
  .weak  EXTI15_10_IRQHandler
400
  .thumb_set EXTI15_10_IRQHandler,Default_Handler
401
402
  .weak  RTCAlarm_IRQHandler
403
  .thumb_set RTCAlarm_IRQHandler,Default_Handler
404
405
  .weak  CEC_IRQHandler
406
  .thumb_set CEC_IRQHandler,Default_Handler
407
408
  .weak  TIM12_IRQHandler
409
  .thumb_set TIM12_IRQHandler,Default_Handler
410
411
  .weak  TIM13_IRQHandler
412
  .thumb_set TIM13_IRQHandler,Default_Handler
413
414
  .weak  TIM14_IRQHandler
415
  .thumb_set TIM14_IRQHandler,Default_Handler
416
417
  .weak  TIM5_IRQHandler
418
  .thumb_set TIM5_IRQHandler,Default_Handler
419
420
  .weak  SPI3_IRQHandler
421
  .thumb_set SPI3_IRQHandler,Default_Handler
422
423
  .weak  UART4_IRQHandler
424
  .thumb_set UART4_IRQHandler,Default_Handler
425
426
  .weak  UART5_IRQHandler
427
  .thumb_set UART5_IRQHandler,Default_Handler
428
  
429
  .weak  TIM6_DAC_IRQHandler
430
  .thumb_set TIM6_DAC_IRQHandler,Default_Handler
431
432
  .weak  TIM7_IRQHandler
433
  .thumb_set TIM7_IRQHandler,Default_Handler 
434
435
  .weak  DMA2_Channel1_IRQHandler
436
  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
437
438
  .weak  DMA2_Channel2_IRQHandler
439
  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
440
441
  .weak  DMA2_Channel3_IRQHandler
442
  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
443
444
  .weak  DMA2_Channel4_5_IRQHandler
445
  .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler  
446
447
  .weak  DMA2_Channel5_IRQHandler
448
  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
449
  
450
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
451