amiro-blt / Target / Modules / DiWheelDrive_1-1 / Boot / lib / CMSIS / CM3 / DeviceSupport / ST / STM32F10x / startup / arm / startup_stm32f10x_hd_vl.s @ 367c0652
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1 | 69661903 | Thomas Schöpping | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** |
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2 | ;* File Name : startup_stm32f10x_hd_vl.s |
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3 | ;* Author : MCD Application Team |
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4 | ;* Version : V3.5.0 |
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5 | ;* Date : 11-March-2011 |
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6 | ;* Description : STM32F10x High Density Value Line Devices vector table |
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7 | ;* for MDK-ARM toolchain. |
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8 | ;* This module performs: |
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9 | ;* - Set the initial SP |
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10 | ;* - Set the initial PC == Reset_Handler |
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11 | ;* - Set the vector table entries with the exceptions ISR address |
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12 | ;* - Configure the clock system and also configure the external |
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13 | ;* SRAM mounted on STM32100E-EVAL board to be used as data |
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14 | ;* memory (optional, to be enabled by user) |
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15 | ;* - Branches to __main in the C library (which eventually |
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16 | ;* calls main()). |
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17 | ;* After Reset the CortexM3 processor is in Thread mode, |
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18 | ;* priority is Privileged, and the Stack is set to Main. |
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19 | ;* <<< Use Configuration Wizard in Context Menu >>> |
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20 | ;******************************************************************************* |
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21 | ; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
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22 | ; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. |
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23 | ; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, |
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24 | ; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE |
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25 | ; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING |
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26 | ; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
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27 | ;******************************************************************************* |
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28 | |||
29 | ; Amount of memory (in bytes) allocated for Stack |
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30 | ; Tailor this value to your application needs |
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31 | ; <h> Stack Configuration |
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32 | ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> |
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33 | ; </h> |
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34 | |||
35 | Stack_Size EQU 0x00000400 |
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36 | |||
37 | AREA STACK, NOINIT, READWRITE, ALIGN=3 |
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38 | Stack_Mem SPACE Stack_Size |
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39 | __initial_sp |
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40 | |||
41 | |||
42 | ; <h> Heap Configuration |
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43 | ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> |
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44 | ; </h> |
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45 | |||
46 | Heap_Size EQU 0x00000200 |
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47 | |||
48 | AREA HEAP, NOINIT, READWRITE, ALIGN=3 |
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49 | __heap_base |
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50 | Heap_Mem SPACE Heap_Size |
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51 | __heap_limit |
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52 | |||
53 | PRESERVE8 |
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54 | THUMB |
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55 | |||
56 | |||
57 | ; Vector Table Mapped to Address 0 at Reset |
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58 | AREA RESET, DATA, READONLY |
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59 | EXPORT __Vectors |
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60 | EXPORT __Vectors_End |
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61 | EXPORT __Vectors_Size |
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62 | |||
63 | __Vectors DCD __initial_sp ; Top of Stack |
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64 | DCD Reset_Handler ; Reset Handler |
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65 | DCD NMI_Handler ; NMI Handler |
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66 | DCD HardFault_Handler ; Hard Fault Handler |
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67 | DCD MemManage_Handler ; MPU Fault Handler |
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68 | DCD BusFault_Handler ; Bus Fault Handler |
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69 | DCD UsageFault_Handler ; Usage Fault Handler |
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70 | DCD 0 ; Reserved |
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71 | DCD 0 ; Reserved |
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72 | DCD 0 ; Reserved |
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73 | DCD 0 ; Reserved |
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74 | DCD SVC_Handler ; SVCall Handler |
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75 | DCD DebugMon_Handler ; Debug Monitor Handler |
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76 | DCD 0 ; Reserved |
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77 | DCD PendSV_Handler ; PendSV Handler |
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78 | DCD SysTick_Handler ; SysTick Handler |
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79 | |||
80 | ; External Interrupts |
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81 | DCD WWDG_IRQHandler ; Window Watchdog |
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82 | DCD PVD_IRQHandler ; PVD through EXTI Line detect |
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83 | DCD TAMPER_IRQHandler ; Tamper |
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84 | DCD RTC_IRQHandler ; RTC |
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85 | DCD FLASH_IRQHandler ; Flash |
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86 | DCD RCC_IRQHandler ; RCC |
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87 | DCD EXTI0_IRQHandler ; EXTI Line 0 |
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88 | DCD EXTI1_IRQHandler ; EXTI Line 1 |
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89 | DCD EXTI2_IRQHandler ; EXTI Line 2 |
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90 | DCD EXTI3_IRQHandler ; EXTI Line 3 |
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91 | DCD EXTI4_IRQHandler ; EXTI Line 4 |
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92 | DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 |
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93 | DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 |
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94 | DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 |
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95 | DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 |
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96 | DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 |
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97 | DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 |
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98 | DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 |
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99 | DCD ADC1_IRQHandler ; ADC1 |
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100 | DCD 0 ; Reserved |
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101 | DCD 0 ; Reserved |
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102 | DCD 0 ; Reserved |
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103 | DCD 0 ; Reserved |
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104 | DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 |
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105 | DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 |
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106 | DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 |
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107 | DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 |
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108 | DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare |
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109 | DCD TIM2_IRQHandler ; TIM2 |
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110 | DCD TIM3_IRQHandler ; TIM3 |
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111 | DCD TIM4_IRQHandler ; TIM4 |
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112 | DCD I2C1_EV_IRQHandler ; I2C1 Event |
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113 | DCD I2C1_ER_IRQHandler ; I2C1 Error |
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114 | DCD I2C2_EV_IRQHandler ; I2C2 Event |
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115 | DCD I2C2_ER_IRQHandler ; I2C2 Error |
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116 | DCD SPI1_IRQHandler ; SPI1 |
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117 | DCD SPI2_IRQHandler ; SPI2 |
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118 | DCD USART1_IRQHandler ; USART1 |
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119 | DCD USART2_IRQHandler ; USART2 |
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120 | DCD USART3_IRQHandler ; USART3 |
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121 | DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 |
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122 | DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line |
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123 | DCD CEC_IRQHandler ; HDMI-CEC |
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124 | DCD TIM12_IRQHandler ; TIM12 |
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125 | DCD TIM13_IRQHandler ; TIM13 |
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126 | DCD TIM14_IRQHandler ; TIM14 |
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127 | DCD 0 ; Reserved |
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128 | DCD 0 ; Reserved |
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129 | DCD 0 ; Reserved |
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130 | DCD 0 ; Reserved |
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131 | DCD TIM5_IRQHandler ; TIM5 |
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132 | DCD SPI3_IRQHandler ; SPI3 |
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133 | DCD UART4_IRQHandler ; UART4 |
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134 | DCD UART5_IRQHandler ; UART5 |
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135 | DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun |
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136 | DCD TIM7_IRQHandler ; TIM7 |
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137 | DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1 |
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138 | DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2 |
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139 | DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3 |
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140 | DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5 |
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141 | DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5 |
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142 | __Vectors_End |
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143 | |||
144 | __Vectors_Size EQU __Vectors_End - __Vectors |
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145 | |||
146 | AREA |.text|, CODE, READONLY |
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147 | |||
148 | ; Reset handler |
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149 | Reset_Handler PROC |
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150 | EXPORT Reset_Handler [WEAK] |
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151 | IMPORT __main |
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152 | IMPORT SystemInit |
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153 | LDR R0, =SystemInit |
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154 | BLX R0 |
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155 | LDR R0, =__main |
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156 | BX R0 |
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157 | ENDP |
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158 | |||
159 | ; Dummy Exception Handlers (infinite loops which can be modified) |
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160 | |||
161 | NMI_Handler PROC |
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162 | EXPORT NMI_Handler [WEAK] |
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163 | B . |
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164 | ENDP |
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165 | HardFault_Handler\ |
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166 | PROC |
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167 | EXPORT HardFault_Handler [WEAK] |
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168 | B . |
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169 | ENDP |
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170 | MemManage_Handler\ |
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171 | PROC |
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172 | EXPORT MemManage_Handler [WEAK] |
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173 | B . |
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174 | ENDP |
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175 | BusFault_Handler\ |
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176 | PROC |
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177 | EXPORT BusFault_Handler [WEAK] |
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178 | B . |
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179 | ENDP |
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180 | UsageFault_Handler\ |
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181 | PROC |
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182 | EXPORT UsageFault_Handler [WEAK] |
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183 | B . |
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184 | ENDP |
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185 | SVC_Handler PROC |
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186 | EXPORT SVC_Handler [WEAK] |
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187 | B . |
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188 | ENDP |
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189 | DebugMon_Handler\ |
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190 | PROC |
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191 | EXPORT DebugMon_Handler [WEAK] |
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192 | B . |
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193 | ENDP |
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194 | PendSV_Handler PROC |
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195 | EXPORT PendSV_Handler [WEAK] |
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196 | B . |
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197 | ENDP |
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198 | SysTick_Handler PROC |
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199 | EXPORT SysTick_Handler [WEAK] |
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200 | B . |
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201 | ENDP |
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202 | |||
203 | Default_Handler PROC |
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204 | |||
205 | EXPORT WWDG_IRQHandler [WEAK] |
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206 | EXPORT PVD_IRQHandler [WEAK] |
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207 | EXPORT TAMPER_IRQHandler [WEAK] |
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208 | EXPORT RTC_IRQHandler [WEAK] |
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209 | EXPORT FLASH_IRQHandler [WEAK] |
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210 | EXPORT RCC_IRQHandler [WEAK] |
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211 | EXPORT EXTI0_IRQHandler [WEAK] |
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212 | EXPORT EXTI1_IRQHandler [WEAK] |
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213 | EXPORT EXTI2_IRQHandler [WEAK] |
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214 | EXPORT EXTI3_IRQHandler [WEAK] |
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215 | EXPORT EXTI4_IRQHandler [WEAK] |
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216 | EXPORT DMA1_Channel1_IRQHandler [WEAK] |
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217 | EXPORT DMA1_Channel2_IRQHandler [WEAK] |
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218 | EXPORT DMA1_Channel3_IRQHandler [WEAK] |
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219 | EXPORT DMA1_Channel4_IRQHandler [WEAK] |
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220 | EXPORT DMA1_Channel5_IRQHandler [WEAK] |
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221 | EXPORT DMA1_Channel6_IRQHandler [WEAK] |
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222 | EXPORT DMA1_Channel7_IRQHandler [WEAK] |
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223 | EXPORT ADC1_IRQHandler [WEAK] |
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224 | EXPORT EXTI9_5_IRQHandler [WEAK] |
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225 | EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK] |
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226 | EXPORT TIM1_UP_TIM16_IRQHandler [WEAK] |
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227 | EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK] |
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228 | EXPORT TIM1_CC_IRQHandler [WEAK] |
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229 | EXPORT TIM2_IRQHandler [WEAK] |
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230 | EXPORT TIM3_IRQHandler [WEAK] |
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231 | EXPORT TIM4_IRQHandler [WEAK] |
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232 | EXPORT I2C1_EV_IRQHandler [WEAK] |
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233 | EXPORT I2C1_ER_IRQHandler [WEAK] |
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234 | EXPORT I2C2_EV_IRQHandler [WEAK] |
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235 | EXPORT I2C2_ER_IRQHandler [WEAK] |
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236 | EXPORT SPI1_IRQHandler [WEAK] |
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237 | EXPORT SPI2_IRQHandler [WEAK] |
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238 | EXPORT USART1_IRQHandler [WEAK] |
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239 | EXPORT USART2_IRQHandler [WEAK] |
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240 | EXPORT USART3_IRQHandler [WEAK] |
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241 | EXPORT EXTI15_10_IRQHandler [WEAK] |
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242 | EXPORT RTCAlarm_IRQHandler [WEAK] |
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243 | EXPORT CEC_IRQHandler [WEAK] |
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244 | EXPORT TIM12_IRQHandler [WEAK] |
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245 | EXPORT TIM13_IRQHandler [WEAK] |
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246 | EXPORT TIM14_IRQHandler [WEAK] |
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247 | EXPORT TIM5_IRQHandler [WEAK] |
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248 | EXPORT SPI3_IRQHandler [WEAK] |
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249 | EXPORT UART4_IRQHandler [WEAK] |
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250 | EXPORT UART5_IRQHandler [WEAK] |
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251 | EXPORT TIM6_DAC_IRQHandler [WEAK] |
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252 | EXPORT TIM7_IRQHandler [WEAK] |
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253 | EXPORT DMA2_Channel1_IRQHandler [WEAK] |
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254 | EXPORT DMA2_Channel2_IRQHandler [WEAK] |
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255 | EXPORT DMA2_Channel3_IRQHandler [WEAK] |
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256 | EXPORT DMA2_Channel4_5_IRQHandler [WEAK] |
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257 | EXPORT DMA2_Channel5_IRQHandler [WEAK] |
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258 | |||
259 | WWDG_IRQHandler |
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260 | PVD_IRQHandler |
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261 | TAMPER_IRQHandler |
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262 | RTC_IRQHandler |
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263 | FLASH_IRQHandler |
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264 | RCC_IRQHandler |
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265 | EXTI0_IRQHandler |
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266 | EXTI1_IRQHandler |
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267 | EXTI2_IRQHandler |
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268 | EXTI3_IRQHandler |
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269 | EXTI4_IRQHandler |
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270 | DMA1_Channel1_IRQHandler |
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271 | DMA1_Channel2_IRQHandler |
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272 | DMA1_Channel3_IRQHandler |
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273 | DMA1_Channel4_IRQHandler |
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274 | DMA1_Channel5_IRQHandler |
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275 | DMA1_Channel6_IRQHandler |
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276 | DMA1_Channel7_IRQHandler |
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277 | ADC1_IRQHandler |
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278 | EXTI9_5_IRQHandler |
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279 | TIM1_BRK_TIM15_IRQHandler |
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280 | TIM1_UP_TIM16_IRQHandler |
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281 | TIM1_TRG_COM_TIM17_IRQHandler |
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282 | TIM1_CC_IRQHandler |
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283 | TIM2_IRQHandler |
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284 | TIM3_IRQHandler |
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285 | TIM4_IRQHandler |
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286 | I2C1_EV_IRQHandler |
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287 | I2C1_ER_IRQHandler |
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288 | I2C2_EV_IRQHandler |
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289 | I2C2_ER_IRQHandler |
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290 | SPI1_IRQHandler |
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291 | SPI2_IRQHandler |
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292 | USART1_IRQHandler |
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293 | USART2_IRQHandler |
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294 | USART3_IRQHandler |
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295 | EXTI15_10_IRQHandler |
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296 | RTCAlarm_IRQHandler |
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297 | CEC_IRQHandler |
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298 | TIM12_IRQHandler |
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299 | TIM13_IRQHandler |
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300 | TIM14_IRQHandler |
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301 | TIM5_IRQHandler |
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302 | SPI3_IRQHandler |
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303 | UART4_IRQHandler |
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304 | UART5_IRQHandler |
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305 | TIM6_DAC_IRQHandler |
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306 | TIM7_IRQHandler |
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307 | DMA2_Channel1_IRQHandler |
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308 | DMA2_Channel2_IRQHandler |
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309 | DMA2_Channel3_IRQHandler |
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310 | DMA2_Channel4_5_IRQHandler |
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311 | DMA2_Channel5_IRQHandler |
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312 | B . |
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313 | |||
314 | ENDP |
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315 | |||
316 | ALIGN |
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317 | |||
318 | ;******************************************************************************* |
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319 | ; User Stack and Heap initialization |
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320 | ;******************************************************************************* |
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321 | IF :DEF:__MICROLIB |
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322 | |||
323 | EXPORT __initial_sp |
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324 | EXPORT __heap_base |
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325 | EXPORT __heap_limit |
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326 | |||
327 | ELSE |
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328 | |||
329 | IMPORT __use_two_region_memory |
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330 | EXPORT __user_initial_stackheap |
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331 | |||
332 | __user_initial_stackheap |
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333 | |||
334 | LDR R0, = Heap_Mem |
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335 | LDR R1, =(Stack_Mem + Stack_Size) |
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336 | LDR R2, = (Heap_Mem + Heap_Size) |
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337 | LDR R3, = Stack_Mem |
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338 | BX LR |
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339 | |||
340 | ALIGN |
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341 | |||
342 | ENDIF |
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343 | |||
344 | END |
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345 | |||
346 | ;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE***** |