amiro-blt / Target / Modules / DiWheelDrive_1-1 / Boot / lib / fatfs / mmc.c @ 367c0652
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1 | 69661903 | Thomas Schöpping | /*------------------------------------------------------------------------/
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2 | / MMCv3/SDv1/SDv2 (in SPI mode) control module
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3 | /-------------------------------------------------------------------------/
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4 | /
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5 | / Copyright (C) 2013, ChaN, all right reserved.
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6 | /
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7 | / * This software is a free software and there is NO WARRANTY.
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8 | / * No restriction on use. You can use, modify and redistribute it for
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9 | / personal, non-profit or commercial products UNDER YOUR RESPONSIBILITY.
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10 | / * Redistributions of source code must retain the above copyright notice.
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11 | /
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12 | /-------------------------------------------------------------------------*/
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13 | |||
14 | |||
15 | /*
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16 | * This file was modified from a sample available from the FatFs
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17 | * web site. It was modified to work with a Olimex STM32-P103
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18 | * evaluation board.
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19 | *
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20 | */
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21 | #include "diskio.h" |
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22 | #include "stm32f10x.h" /* STM32 registers */ |
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23 | #include "stm32f10x_conf.h" /* STM32 peripheral drivers */ |
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24 | #include "boot.h" |
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25 | |||
26 | |||
27 | |||
28 | /*--------------------------------------------------------------------------
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29 | |||
30 | Module Private Functions
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31 | |||
32 | ---------------------------------------------------------------------------*/
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33 | |||
34 | /* Definitions for MMC/SDC command */
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35 | #define CMD0 (0) /* GO_IDLE_STATE */ |
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36 | #define CMD1 (1) /* SEND_OP_COND */ |
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37 | #define ACMD41 (41|0x80) /* SEND_OP_COND (SDC) */ |
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38 | #define CMD8 (8) /* SEND_IF_COND */ |
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39 | #define CMD9 (9) /* SEND_CSD */ |
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40 | #define CMD10 (10) /* SEND_CID */ |
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41 | #define CMD12 (12) /* STOP_TRANSMISSION */ |
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42 | #define ACMD13 (13|0x80) /* SD_STATUS (SDC) */ |
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43 | #define CMD16 (16) /* SET_BLOCKLEN */ |
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44 | #define CMD17 (17) /* READ_SINGLE_BLOCK */ |
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45 | #define CMD18 (18) /* READ_MULTIPLE_BLOCK */ |
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46 | #define CMD23 (23) /* SET_BLOCK_COUNT */ |
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47 | #define ACMD23 (23|0x80) /* SET_WR_BLK_ERASE_COUNT (SDC) */ |
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48 | #define CMD24 (24) /* WRITE_BLOCK */ |
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49 | #define CMD25 (25) /* WRITE_MULTIPLE_BLOCK */ |
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50 | #define CMD41 (41) /* SEND_OP_COND (ACMD) */ |
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51 | #define CMD55 (55) /* APP_CMD */ |
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52 | #define CMD58 (58) /* READ_OCR */ |
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53 | |||
54 | |||
55 | /* Control signals (Platform dependent) */
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56 | #define CS_LOW() GPIO_ResetBits(GPIOB, GPIO_Pin_12) /* MMC CS = L */ |
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57 | #define CS_HIGH() GPIO_SetBits(GPIOB, GPIO_Pin_12) /* MMC CS = H */ |
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58 | |||
59 | |||
60 | |||
61 | #define FCLK_SLOW() /* Set slow clock (100k-400k) */ |
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62 | #define FCLK_FAST() set_max_speed() /* Set fast clock (depends on the CSD) */ |
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63 | |||
64 | static volatile |
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65 | DSTATUS Stat = STA_NOINIT; /* Disk status */
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66 | |||
67 | static
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68 | UINT CardType; |
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69 | |||
70 | |||
71 | /*-----------------------------------------------------------------------*/
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72 | /* Send 80 or so clock transitions with CS and DI held high. This is */
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73 | /* required after card power up to get it into SPI mode */
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74 | /*-----------------------------------------------------------------------*/
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75 | static
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76 | void send_initial_clock_train(void) |
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77 | { |
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78 | GPIO_InitTypeDef GPIO_InitStructure; |
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79 | unsigned int i; |
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80 | |||
81 | /* Ensure CS is held high. */
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82 | CS_HIGH(); |
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83 | |||
84 | /* Switch the SSI TX line to a GPIO and drive it high too. */
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85 | GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15; |
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86 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; |
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87 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; |
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88 | GPIO_Init(GPIOB, &GPIO_InitStructure); |
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89 | GPIO_SetBits(GPIOB, GPIO_Pin_15); |
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90 | |||
91 | /* Send 10 bytes over the SSI. This causes the clock to wiggle the */
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92 | /* required number of times. */
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93 | for(i = 0 ; i < 10 ; i++) |
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94 | { |
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95 | /* Loop while DR register in not empty */
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96 | while (SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_TXE) == RESET) { ; }
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97 | |||
98 | /* Send byte through the SPI peripheral */
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99 | SPI_I2S_SendData(SPI2, 0xff);
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100 | |||
101 | /* Wait to receive a byte */
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102 | while (SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_RXNE) == RESET) { ; }
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103 | } |
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104 | |||
105 | /* Revert to hardware control of the SSI TX line. */
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106 | GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15; |
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107 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; |
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108 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; |
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109 | GPIO_Init(GPIOB, &GPIO_InitStructure); |
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110 | } |
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111 | |||
112 | |||
113 | /*-----------------------------------------------------------------------*/
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114 | /* Power Control (Platform dependent) */
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115 | /*-----------------------------------------------------------------------*/
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116 | /* When the target system does not support socket power control, there */
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117 | /* is nothing to do in these functions. */
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118 | |||
119 | static
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120 | void power_on (void) |
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121 | { |
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122 | SPI_InitTypeDef SPI_InitStructure; |
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123 | GPIO_InitTypeDef GPIO_InitStructure; |
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124 | |||
125 | /*
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126 | * This doesn't really turn the power on, but initializes the
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127 | * SSI port and pins needed to talk to the card.
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128 | */
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129 | |||
130 | /* Enable GPIO clock for CS */
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131 | RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE); |
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132 | /* Enable SPI clock, SPI2: APB1 */
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133 | RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE); |
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134 | /* Configure I/O for Flash Chip select (PB12) */
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135 | GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12; |
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136 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; |
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137 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; |
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138 | GPIO_Init(GPIOB, &GPIO_InitStructure); |
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139 | |||
140 | /* De-select the Card: Chip Select high */
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141 | GPIO_SetBits(GPIOB, GPIO_Pin_12); |
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142 | |||
143 | /* Configure SPI pins: SCK (PB13) and MOSI (PB15) with default alternate function (not re-mapped) push-pull */
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144 | GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13 | GPIO_Pin_15; |
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145 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; |
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146 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; |
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147 | GPIO_Init(GPIOB, &GPIO_InitStructure); |
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148 | /* Configure MISO (PB14) as Input with internal pull-up */
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149 | GPIO_InitStructure.GPIO_Pin = GPIO_Pin_14; |
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150 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; |
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151 | GPIO_Init(GPIOB, &GPIO_InitStructure); |
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152 | |||
153 | /* SPI configuration */
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154 | SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; |
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155 | SPI_InitStructure.SPI_Mode = SPI_Mode_Master; |
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156 | SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b; |
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157 | SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low; |
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158 | SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge; |
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159 | SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; |
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160 | SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_256; // 72000kHz/256=281kHz < 400kHz
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161 | SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; |
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162 | SPI_InitStructure.SPI_CRCPolynomial = 7;
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163 | |||
164 | SPI_Init(SPI2, &SPI_InitStructure); |
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165 | SPI_CalculateCRC(SPI2, DISABLE); |
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166 | SPI_Cmd(SPI2, ENABLE); |
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167 | |||
168 | /* Set DI and CS high and apply more than 74 pulses to SCLK for the card */
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169 | /* to be able to accept a native command. */
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170 | send_initial_clock_train(); |
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171 | |||
172 | } |
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173 | // set the SSI speed to the max setting
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174 | static
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175 | void set_max_speed(void) |
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176 | { |
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177 | SPI_InitTypeDef SPI_InitStructure; |
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178 | |||
179 | /* Disable the SPI system */
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180 | SPI_Cmd(SPI2, DISABLE); |
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181 | |||
182 | /* MMC/SDC can work at the clock frequency up to 20/25MHz so pick a speed close to
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183 | * this but not higher
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184 | */
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185 | SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; |
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186 | SPI_InitStructure.SPI_Mode = SPI_Mode_Master; |
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187 | SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b; |
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188 | SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low; |
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189 | SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge; |
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190 | SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; |
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191 | SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4; // 72MHz/4=18MHz < 20MHz
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192 | SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; |
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193 | SPI_InitStructure.SPI_CRCPolynomial = 7;
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194 | SPI_Init(SPI2, &SPI_InitStructure); |
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195 | SPI_CalculateCRC(SPI2, DISABLE); |
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196 | |||
197 | /* Enable the SPI system */
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198 | SPI_Cmd(SPI2, ENABLE); |
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199 | } |
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200 | |||
201 | static
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202 | void power_off (void) |
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203 | { |
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204 | Stat |= STA_NOINIT; /* Force uninitialized */
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205 | } |
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206 | |||
207 | |||
208 | /*-----------------------------------------------------------------------*/
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209 | /* Transmit/Receive data to/from MMC via SPI (Platform dependent) */
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210 | /*-----------------------------------------------------------------------*/
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211 | |||
212 | static
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213 | BYTE xchg_spi (BYTE dat) |
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214 | { |
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215 | /* Send byte through the SPI peripheral */
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216 | SPI_I2S_SendData(SPI2, dat); |
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217 | |||
218 | /* Wait to receive a byte */
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219 | while (SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_RXNE) == RESET) { ; }
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220 | |||
221 | /* Return the byte read from the SPI bus */
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222 | return (BYTE)SPI_I2S_ReceiveData(SPI2);
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223 | } |
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224 | |||
225 | static
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226 | void rcvr_spi_m (BYTE *dst)
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227 | { |
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228 | *dst = xchg_spi(0xFF);
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229 | } |
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230 | |||
231 | |||
232 | /*-----------------------------------------------------------------------*/
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233 | /* Wait for card ready */
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234 | /*-----------------------------------------------------------------------*/
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235 | |||
236 | static
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237 | int wait_ready (void) |
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238 | { |
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239 | BYTE d; |
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240 | ULONG timeOutTime; |
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241 | |||
242 | /* set timeout for 500 ms from now */
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243 | timeOutTime = TimerGet() + 500;
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244 | |||
245 | do {
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246 | d = xchg_spi(0xFF);
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247 | } while ((d != 0xFF) && (TimerGet() < timeOutTime)); |
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248 | |||
249 | return (d == 0xFF) ? 1 : 0; |
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250 | } |
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251 | |||
252 | |||
253 | /*-----------------------------------------------------------------------*/
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254 | /* Deselect the card and release SPI bus */
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255 | /*-----------------------------------------------------------------------*/
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256 | |||
257 | static
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258 | void deselect (void) |
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259 | { |
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260 | CS_HIGH(); |
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261 | xchg_spi(0xFF); /* Dummy clock (force DO hi-z for multiple slave SPI) */ |
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262 | } |
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263 | |||
264 | |||
265 | |||
266 | /*-----------------------------------------------------------------------*/
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267 | /* Select the card and wait ready */
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268 | /*-----------------------------------------------------------------------*/
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269 | |||
270 | static
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271 | int select (void) /* 1:Successful, 0:Timeout */ |
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272 | { |
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273 | CS_LOW(); |
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274 | xchg_spi(0xFF); /* Dummy clock (force DO enabled) */ |
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275 | |||
276 | if (wait_ready()) return 1; /* OK */ |
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277 | deselect(); |
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278 | return 0; /* Timeout */ |
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279 | } |
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280 | |||
281 | |||
282 | |||
283 | /*-----------------------------------------------------------------------*/
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284 | /* Receive a data packet from MMC */
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285 | /*-----------------------------------------------------------------------*/
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286 | |||
287 | static
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288 | int rcvr_datablock ( /* 1:OK, 0:Failed */ |
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289 | BYTE *buff, /* Data buffer to store received data */
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290 | UINT btr /* Byte count (must be multiple of 4) */
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291 | ) |
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292 | { |
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293 | BYTE token; |
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294 | ULONG timeOutTime; |
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295 | |||
296 | /* set timeout for 100 ms from now */
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297 | timeOutTime = TimerGet() + 100;
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298 | |||
299 | do { /* Wait for data packet in timeout of 100ms */ |
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300 | token = xchg_spi(0xFF);
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301 | } while ((token == 0xFF) && (TimerGet() < timeOutTime)); |
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302 | |||
303 | if(token != 0xFE) return 0; /* If not valid data token, retutn with error */ |
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304 | |||
305 | do { /* Receive the data block into buffer */ |
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306 | rcvr_spi_m(buff++); |
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307 | rcvr_spi_m(buff++); |
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308 | } while (btr -= 2); |
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309 | xchg_spi(0xFF); /* Discard CRC */ |
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310 | xchg_spi(0xFF);
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311 | |||
312 | return 1; /* Return with success */ |
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313 | } |
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314 | |||
315 | |||
316 | |||
317 | /*-----------------------------------------------------------------------*/
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318 | /* Send a data packet to MMC */
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319 | /*-----------------------------------------------------------------------*/
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320 | |||
321 | #if _USE_WRITE
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322 | static
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323 | int xmit_datablock ( /* 1:OK, 0:Failed */ |
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324 | const BYTE *buff, /* 512 byte data block to be transmitted */ |
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325 | BYTE token /* Data token */
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326 | ) |
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327 | { |
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328 | BYTE resp; |
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329 | UINT wc; |
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330 | |||
331 | |||
332 | if (!wait_ready()) return 0; |
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333 | |||
334 | xchg_spi(token); /* Xmit a token */
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335 | if (token != 0xFD) { /* Not StopTran token */ |
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336 | wc = 512;
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337 | do { /* Xmit the 512 byte data block to MMC */ |
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338 | xchg_spi(*buff++); |
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339 | xchg_spi(*buff++); |
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340 | } while (wc -= 2); |
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341 | xchg_spi(0xFF); /* CRC (Dummy) */ |
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342 | xchg_spi(0xFF);
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343 | resp = xchg_spi(0xFF); /* Receive a data response */ |
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344 | if ((resp & 0x1F) != 0x05) /* If not accepted, return with error */ |
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345 | return 0; |
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346 | } |
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347 | |||
348 | return 1; |
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349 | } |
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350 | #endif
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351 | |||
352 | |||
353 | |||
354 | /*-----------------------------------------------------------------------*/
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355 | /* Send a command packet to MMC */
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356 | /*-----------------------------------------------------------------------*/
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357 | |||
358 | static
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359 | BYTE send_cmd ( |
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360 | BYTE cmd, /* Command byte */
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361 | DWORD arg /* Argument */
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362 | ) |
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363 | { |
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364 | BYTE n, res; |
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365 | |||
366 | |||
367 | if (cmd & 0x80) { /* ACMD<n> is the command sequense of CMD55-CMD<n> */ |
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368 | cmd &= 0x7F;
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369 | res = send_cmd(CMD55, 0);
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370 | if (res > 1) return res; |
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371 | } |
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372 | |||
373 | /* Select the card and wait for ready */
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374 | deselect(); |
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375 | if (!select()) return 0xFF; |
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376 | |||
377 | /* Send command packet */
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378 | xchg_spi(0x40 | cmd); /* Start + Command index */ |
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379 | xchg_spi((BYTE)(arg >> 24)); /* Argument[31..24] */ |
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380 | xchg_spi((BYTE)(arg >> 16)); /* Argument[23..16] */ |
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381 | xchg_spi((BYTE)(arg >> 8)); /* Argument[15..8] */ |
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382 | xchg_spi((BYTE)arg); /* Argument[7..0] */
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383 | n = 0x01; /* Dummy CRC + Stop */ |
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384 | if (cmd == CMD0) n = 0x95; /* Valid CRC for CMD0(0) + Stop */ |
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385 | if (cmd == CMD8) n = 0x87; /* Valid CRC for CMD8(0x1AA) + Stop */ |
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386 | xchg_spi(n); |
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387 | |||
388 | /* Receive command response */
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389 | if (cmd == CMD12) xchg_spi(0xFF); /* Skip a stuff byte on stop to read */ |
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390 | n = 10; /* Wait for a valid response in timeout of 10 attempts */ |
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391 | do
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392 | res = xchg_spi(0xFF);
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393 | while ((res & 0x80) && --n); |
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394 | |||
395 | return res; /* Return with the response value */ |
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396 | } |
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397 | |||
398 | |||
399 | |||
400 | /*--------------------------------------------------------------------------
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401 | |||
402 | Public Functions
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403 | |||
404 | ---------------------------------------------------------------------------*/
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405 | |||
406 | |||
407 | /*-----------------------------------------------------------------------*/
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408 | /* Initialize Disk Drive */
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409 | /*-----------------------------------------------------------------------*/
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410 | |||
411 | DSTATUS disk_initialize ( |
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412 | BYTE pdrv /* Physical drive nmuber (0) */
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413 | ) |
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414 | { |
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415 | BYTE n, cmd, ty, ocr[4];
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416 | ULONG timeOutTime; |
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417 | |||
418 | |||
419 | if (pdrv) return STA_NOINIT; /* Supports only single drive */ |
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420 | if (Stat & STA_NODISK) return Stat; /* No card in the socket */ |
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421 | |||
422 | power_on(); /* Force socket power on */
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423 | |||
424 | CS_LOW(); /* CS = L */
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425 | |||
426 | ty = 0;
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427 | if (send_cmd(CMD0, 0) == 1) { /* Enter Idle state */ |
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428 | timeOutTime = TimerGet() + 1000; /* Initialization timeout of 1000 msec */ |
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429 | |||
430 | if (send_cmd(CMD8, 0x1AA) == 1) { /* SDv2? */ |
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431 | for (n = 0; n < 4; n++) ocr[n] = xchg_spi(0xFF); /* Get trailing return value of R7 resp */ |
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432 | if (ocr[2] == 0x01 && ocr[3] == 0xAA) { /* The card can work at vdd range of 2.7-3.6V */ |
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433 | while ((TimerGet() < timeOutTime) && send_cmd(ACMD41, 0x40000000)); /* Wait for leaving idle state (ACMD41 with HCS bit) */ |
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434 | if ((TimerGet() < timeOutTime) && send_cmd(CMD58, 0) == 0) { /* Check CCS bit in the OCR */ |
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435 | for (n = 0; n < 4; n++) ocr[n] = xchg_spi(0xFF); |
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436 | ty = (ocr[0] & 0x40) ? CT_SD2|CT_BLOCK : CT_SD2; /* SDv2 */ |
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437 | } |
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438 | } |
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439 | } else { /* SDv1 or MMCv3 */ |
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440 | if (send_cmd(ACMD41, 0) <= 1) { |
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441 | ty = CT_SD1; cmd = ACMD41; /* SDv1 */
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442 | } else {
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443 | ty = CT_MMC; cmd = CMD1; /* MMCv3 */
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444 | } |
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445 | while ((TimerGet() < timeOutTime) && send_cmd(cmd, 0)); /* Wait for leaving idle state */ |
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446 | if (!(TimerGet() < timeOutTime) || send_cmd(CMD16, 512) != 0) /* Set read/write block length to 512 */ |
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447 | ty = 0;
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448 | } |
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449 | } |
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450 | CardType = ty; |
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451 | deselect(); |
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452 | |||
453 | if (ty) { /* Initialization succeded */ |
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454 | Stat &= ~STA_NOINIT; /* Clear STA_NOINIT */
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455 | FCLK_FAST(); |
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456 | } else { /* Initialization failed */ |
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457 | power_off(); |
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458 | } |
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459 | |||
460 | return Stat;
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461 | } |
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462 | |||
463 | |||
464 | |||
465 | /*-----------------------------------------------------------------------*/
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466 | /* Get Disk Status */
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467 | /*-----------------------------------------------------------------------*/
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468 | |||
469 | DSTATUS disk_status ( |
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470 | BYTE pdrv /* Physical drive nmuber (0) */
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471 | ) |
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472 | { |
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473 | if (pdrv) return STA_NOINIT; /* Supports only single drive */ |
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474 | return Stat;
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475 | } |
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476 | |||
477 | |||
478 | |||
479 | /*-----------------------------------------------------------------------*/
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480 | /* Read Sector(s) */
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481 | /*-----------------------------------------------------------------------*/
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482 | |||
483 | DRESULT disk_read ( |
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484 | BYTE pdrv, /* Physical drive number (0) */
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485 | BYTE *buff, /* Pointer to the data buffer to store read data */
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486 | DWORD sector, /* Start sector number (LBA) */
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487 | BYTE count /* Sector count (1..255) */
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488 | ) |
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489 | { |
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490 | if (pdrv || !count) return RES_PARERR; |
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491 | if (Stat & STA_NOINIT) return RES_NOTRDY; |
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492 | |||
493 | if (!(CardType & CT_BLOCK)) sector *= 512; /* Convert to byte address if needed */ |
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494 | |||
495 | if (count == 1) { /* Single block read */ |
||
496 | if ((send_cmd(CMD17, sector) == 0) /* READ_SINGLE_BLOCK */ |
||
497 | && rcvr_datablock(buff, 512))
|
||
498 | count = 0;
|
||
499 | } |
||
500 | else { /* Multiple block read */ |
||
501 | if (send_cmd(CMD18, sector) == 0) { /* READ_MULTIPLE_BLOCK */ |
||
502 | do {
|
||
503 | if (!rcvr_datablock(buff, 512)) break; |
||
504 | buff += 512;
|
||
505 | } while (--count);
|
||
506 | send_cmd(CMD12, 0); /* STOP_TRANSMISSION */ |
||
507 | } |
||
508 | } |
||
509 | deselect(); |
||
510 | |||
511 | return count ? RES_ERROR : RES_OK;
|
||
512 | } |
||
513 | |||
514 | |||
515 | |||
516 | /*-----------------------------------------------------------------------*/
|
||
517 | /* Write Sector(s) */
|
||
518 | /*-----------------------------------------------------------------------*/
|
||
519 | |||
520 | #if _USE_WRITE
|
||
521 | DRESULT disk_write ( |
||
522 | BYTE pdrv, /* Physical drive nmuber (0) */
|
||
523 | const BYTE *buff, /* Pointer to the data to be written */ |
||
524 | DWORD sector, /* Start sector number (LBA) */
|
||
525 | BYTE count /* Sector count (1..255) */
|
||
526 | ) |
||
527 | { |
||
528 | if (pdrv || !count) return RES_PARERR; |
||
529 | if (Stat & STA_NOINIT) return RES_NOTRDY; |
||
530 | if (Stat & STA_PROTECT) return RES_WRPRT; |
||
531 | |||
532 | if (!(CardType & CT_BLOCK)) sector *= 512; /* Convert to byte address if needed */ |
||
533 | |||
534 | if (count == 1) { /* Single block write */ |
||
535 | if ((send_cmd(CMD24, sector) == 0) /* WRITE_BLOCK */ |
||
536 | && xmit_datablock(buff, 0xFE))
|
||
537 | count = 0;
|
||
538 | } |
||
539 | else { /* Multiple block write */ |
||
540 | if (CardType & CT_SDC) send_cmd(ACMD23, count);
|
||
541 | if (send_cmd(CMD25, sector) == 0) { /* WRITE_MULTIPLE_BLOCK */ |
||
542 | do {
|
||
543 | if (!xmit_datablock(buff, 0xFC)) break; |
||
544 | buff += 512;
|
||
545 | } while (--count);
|
||
546 | if (!xmit_datablock(0, 0xFD)) /* STOP_TRAN token */ |
||
547 | count = 1;
|
||
548 | } |
||
549 | } |
||
550 | deselect(); |
||
551 | |||
552 | return count ? RES_ERROR : RES_OK;
|
||
553 | } |
||
554 | #endif
|
||
555 | |||
556 | |||
557 | |||
558 | /*-----------------------------------------------------------------------*/
|
||
559 | /* Miscellaneous Functions */
|
||
560 | /*-----------------------------------------------------------------------*/
|
||
561 | |||
562 | #if _USE_IOCTL
|
||
563 | DRESULT disk_ioctl ( |
||
564 | BYTE pdrv, /* Physical drive nmuber (0) */
|
||
565 | BYTE cmd, /* Control code */
|
||
566 | void *buff /* Buffer to send/receive data block */ |
||
567 | ) |
||
568 | { |
||
569 | DRESULT res; |
||
570 | BYTE n, csd[16], *ptr = buff;
|
||
571 | DWORD csz; |
||
572 | |||
573 | |||
574 | if (pdrv) return RES_PARERR; |
||
575 | if (Stat & STA_NOINIT) return RES_NOTRDY; |
||
576 | |||
577 | res = RES_ERROR; |
||
578 | switch (cmd) {
|
||
579 | case CTRL_SYNC : /* Flush write-back cache, Wait for end of internal process */ |
||
580 | if (select()) res = RES_OK;
|
||
581 | break;
|
||
582 | |||
583 | case GET_SECTOR_COUNT : /* Get number of sectors on the disk (WORD) */ |
||
584 | if ((send_cmd(CMD9, 0) == 0) && rcvr_datablock(csd, 16)) { |
||
585 | if ((csd[0] >> 6) == 1) { /* SDv2? */ |
||
586 | csz = csd[9] + ((WORD)csd[8] << 8) + ((DWORD)(csd[7] & 63) << 16) + 1; |
||
587 | *(DWORD*)buff = csz << 10;
|
||
588 | } else { /* SDv1 or MMCv3 */ |
||
589 | n = (csd[5] & 15) + ((csd[10] & 128) >> 7) + ((csd[9] & 3) << 1) + 2; |
||
590 | csz = (csd[8] >> 6) + ((WORD)csd[7] << 2) + ((WORD)(csd[6] & 3) << 10) + 1; |
||
591 | *(DWORD*)buff = csz << (n - 9);
|
||
592 | } |
||
593 | res = RES_OK; |
||
594 | } |
||
595 | break;
|
||
596 | |||
597 | case GET_BLOCK_SIZE : /* Get erase block size in unit of sectors (DWORD) */ |
||
598 | if (CardType & CT_SD2) { /* SDv2? */ |
||
599 | if (send_cmd(ACMD13, 0) == 0) { /* Read SD status */ |
||
600 | xchg_spi(0xFF);
|
||
601 | if (rcvr_datablock(csd, 16)) { /* Read partial block */ |
||
602 | for (n = 64 - 16; n; n--) xchg_spi(0xFF); /* Purge trailing data */ |
||
603 | *(DWORD*)buff = 16UL << (csd[10] >> 4); |
||
604 | res = RES_OK; |
||
605 | } |
||
606 | } |
||
607 | } else { /* SDv1 or MMCv3 */ |
||
608 | if ((send_cmd(CMD9, 0) == 0) && rcvr_datablock(csd, 16)) { /* Read CSD */ |
||
609 | if (CardType & CT_SD1) { /* SDv1 */ |
||
610 | *(DWORD*)buff = (((csd[10] & 63) << 1) + ((WORD)(csd[11] & 128) >> 7) + 1) << ((csd[13] >> 6) - 1); |
||
611 | } else { /* MMCv3 */ |
||
612 | *(DWORD*)buff = ((WORD)((csd[10] & 124) >> 2) + 1) * (((csd[11] & 3) << 3) + ((csd[11] & 224) >> 5) + 1); |
||
613 | } |
||
614 | res = RES_OK; |
||
615 | } |
||
616 | } |
||
617 | break;
|
||
618 | |||
619 | case MMC_GET_TYPE : /* Get card type flags (1 byte) */ |
||
620 | *ptr = CardType; |
||
621 | res = RES_OK; |
||
622 | break;
|
||
623 | |||
624 | case MMC_GET_CSD : /* Receive CSD as a data block (16 bytes) */ |
||
625 | if ((send_cmd(CMD9, 0) == 0) /* READ_CSD */ |
||
626 | && rcvr_datablock(buff, 16))
|
||
627 | res = RES_OK; |
||
628 | break;
|
||
629 | |||
630 | case MMC_GET_CID : /* Receive CID as a data block (16 bytes) */ |
||
631 | if ((send_cmd(CMD10, 0) == 0) /* READ_CID */ |
||
632 | && rcvr_datablock(buff, 16))
|
||
633 | res = RES_OK; |
||
634 | break;
|
||
635 | |||
636 | case MMC_GET_OCR : /* Receive OCR as an R3 resp (4 bytes) */ |
||
637 | if (send_cmd(CMD58, 0) == 0) { /* READ_OCR */ |
||
638 | for (n = 0; n < 4; n++) |
||
639 | *((BYTE*)buff+n) = xchg_spi(0xFF);
|
||
640 | res = RES_OK; |
||
641 | } |
||
642 | break;
|
||
643 | |||
644 | case MMC_GET_SDSTAT : /* Receive SD status as a data block (64 bytes) */ |
||
645 | if ((CardType & CT_SD2) && send_cmd(ACMD13, 0) == 0) { /* SD_STATUS */ |
||
646 | xchg_spi(0xFF);
|
||
647 | if (rcvr_datablock(buff, 64)) |
||
648 | res = RES_OK; |
||
649 | } |
||
650 | break;
|
||
651 | |||
652 | default:
|
||
653 | res = RES_PARERR; |
||
654 | } |
||
655 | |||
656 | deselect(); |
||
657 | |||
658 | return res;
|
||
659 | } |
||
660 | #endif
|
||
661 | |||
662 | |||
663 | /*---------------------------------------------------------*/
|
||
664 | /* User Provided Timer Function for FatFs module */
|
||
665 | /*---------------------------------------------------------*/
|
||
666 | /* This is a real time clock service to be called from */
|
||
667 | /* FatFs module. Any valid time must be returned even if */
|
||
668 | /* the system does not support a real time clock. */
|
||
669 | /* This is not required in read-only configuration. */
|
||
670 | |||
671 | DWORD get_fattime (void)
|
||
672 | { |
||
673 | /* No RTC supprt. Return a fixed value 2013/5/10 0:00:00 */
|
||
674 | return ((DWORD)(2013 - 1980) << 25) /* Y */ |
||
675 | | ((DWORD)5 << 21) /* M */ |
||
676 | | ((DWORD)10 << 16) /* D */ |
||
677 | | ((DWORD)0 << 11) /* H */ |
||
678 | | ((DWORD)0 << 5) /* M */ |
||
679 | | ((DWORD)0 >> 1); /* S */ |
||
680 | } |
||
681 | |||
682 | |||
683 |