amiro-blt / Target / Modules / LightRing_1-0 / Boot / lib / CMSIS / CM3 / CoreSupport / core_cm3.h @ 367c0652
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| 1 | 69661903 | Thomas Schöpping | /**************************************************************************//** |
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| 2 | * @file core_cm3.h
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| 3 | * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
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| 4 | * @version V1.30
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| 5 | * @date 30. October 2009
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| 6 | *
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| 7 | * @note
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| 8 | * Copyright (C) 2009 ARM Limited. All rights reserved.
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| 9 | *
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| 10 | * @par
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| 11 | * ARM Limited (ARM) is supplying this software for use with Cortex-M
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| 12 | * processor based microcontrollers. This file can be freely distributed
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| 13 | * within development tools that are supporting such ARM based processors.
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| 14 | *
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| 15 | * @par
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| 16 | * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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| 17 | * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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| 18 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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| 19 | * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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| 20 | * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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| 21 | *
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| 22 | ******************************************************************************/
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| 23 | |||
| 24 | #ifndef __CM3_CORE_H__
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| 25 | #define __CM3_CORE_H__
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| 26 | |||
| 27 | /** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration
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| 28 | *
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| 29 | * List of Lint messages which will be suppressed and not shown:
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| 30 | * - Error 10: \n
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| 31 | * register uint32_t __regBasePri __asm("basepri"); \n
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| 32 | * Error 10: Expecting ';'
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| 33 | * .
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| 34 | * - Error 530: \n
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| 35 | * return(__regBasePri); \n
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| 36 | * Warning 530: Symbol '__regBasePri' (line 264) not initialized
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| 37 | * .
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| 38 | * - Error 550: \n
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| 39 | * __regBasePri = (basePri & 0x1ff); \n
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| 40 | * Warning 550: Symbol '__regBasePri' (line 271) not accessed
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| 41 | * .
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| 42 | * - Error 754: \n
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| 43 | * uint32_t RESERVED0[24]; \n
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| 44 | * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced
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| 45 | * .
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| 46 | * - Error 750: \n
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| 47 | * #define __CM3_CORE_H__ \n
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| 48 | * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced
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| 49 | * .
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| 50 | * - Error 528: \n
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| 51 | * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
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| 52 | * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced
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| 53 | * .
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| 54 | * - Error 751: \n
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| 55 | * } InterruptType_Type; \n
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| 56 | * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced
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| 57 | * .
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| 58 | * Note: To re-enable a Message, insert a space before 'lint' *
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| 59 | *
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| 60 | */
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| 61 | |||
| 62 | /*lint -save */
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| 63 | /*lint -e10 */
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| 64 | /*lint -e530 */
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| 65 | /*lint -e550 */
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| 66 | /*lint -e754 */
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| 67 | /*lint -e750 */
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| 68 | /*lint -e528 */
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| 69 | /*lint -e751 */
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| 70 | |||
| 71 | |||
| 72 | /** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions
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| 73 | This file defines all structures and symbols for CMSIS core:
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| 74 | - CMSIS version number
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| 75 | - Cortex-M core registers and bitfields
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| 76 | - Cortex-M core peripheral base address
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| 77 | @{
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| 78 | */
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| 79 | |||
| 80 | #ifdef __cplusplus
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| 81 | extern "C" { |
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| 82 | #endif
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| 83 | |||
| 84 | #define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */ |
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| 85 | #define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */ |
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| 86 | #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ |
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| 87 | |||
| 88 | #define __CORTEX_M (0x03) /*!< Cortex core */ |
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| 89 | |||
| 90 | #include <stdint.h> /* Include standard types */ |
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| 91 | |||
| 92 | #if defined (__ICCARM__)
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| 93 | #include <intrinsics.h> /* IAR Intrinsics */ |
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| 94 | #endif
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| 95 | |||
| 96 | |||
| 97 | #ifndef __NVIC_PRIO_BITS
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| 98 | #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */ |
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| 99 | #endif
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| 100 | |||
| 101 | |||
| 102 | |||
| 103 | |||
| 104 | /**
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| 105 | * IO definitions
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| 106 | *
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| 107 | * define access restrictions to peripheral registers
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| 108 | */
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| 109 | |||
| 110 | #ifdef __cplusplus
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| 111 | #define __I volatile /*!< defines 'read only' permissions */ |
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| 112 | #else
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| 113 | #define __I volatile const /*!< defines 'read only' permissions */ |
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| 114 | #endif
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| 115 | #define __O volatile /*!< defines 'write only' permissions */ |
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| 116 | #define __IO volatile /*!< defines 'read / write' permissions */ |
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| 117 | |||
| 118 | |||
| 119 | |||
| 120 | /*******************************************************************************
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| 121 | * Register Abstraction
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| 122 | ******************************************************************************/
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| 123 | /** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register
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| 124 | @{
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| 125 | */
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| 126 | |||
| 127 | |||
| 128 | /** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC
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| 129 | memory mapped structure for Nested Vectored Interrupt Controller (NVIC)
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| 130 | @{
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| 131 | */
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| 132 | typedef struct |
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| 133 | {
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| 134 | __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */ |
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| 135 | uint32_t RESERVED0[24];
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| 136 | __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */ |
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| 137 | uint32_t RSERVED1[24];
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| 138 | __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */ |
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| 139 | uint32_t RESERVED2[24];
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| 140 | __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */ |
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| 141 | uint32_t RESERVED3[24];
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| 142 | __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */ |
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| 143 | uint32_t RESERVED4[56];
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| 144 | __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */ |
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| 145 | uint32_t RESERVED5[644];
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| 146 | __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */
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| 147 | } NVIC_Type; |
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| 148 | /*@}*/ /* end of group CMSIS_CM3_NVIC */ |
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| 149 | |||
| 150 | |||
| 151 | /** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB
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| 152 | memory mapped structure for System Control Block (SCB)
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| 153 | @{
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| 154 | */
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| 155 | typedef struct |
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| 156 | {
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| 157 | __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */
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| 158 | __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */
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| 159 | __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */
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| 160 | __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */
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| 161 | __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */
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| 162 | __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */
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| 163 | __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */ |
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| 164 | __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */
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| 165 | __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */
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| 166 | __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */
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| 167 | __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */
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| 168 | __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */
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| 169 | __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */
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| 170 | __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */
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| 171 | __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */ |
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| 172 | __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */
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| 173 | __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */
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| 174 | __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */ |
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| 175 | __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */ |
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| 176 | } SCB_Type; |
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| 177 | |||
| 178 | /* SCB CPUID Register Definitions */
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| 179 | #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ |
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| 180 | #define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ |
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| 181 | |||
| 182 | #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ |
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| 183 | #define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ |
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| 184 | |||
| 185 | #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ |
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| 186 | #define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ |
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| 187 | |||
| 188 | #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ |
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| 189 | #define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ |
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| 190 | |||
| 191 | /* SCB Interrupt Control State Register Definitions */
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| 192 | #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ |
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| 193 | #define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ |
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| 194 | |||
| 195 | #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ |
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| 196 | #define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ |
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| 197 | |||
| 198 | #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ |
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| 199 | #define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ |
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| 200 | |||
| 201 | #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ |
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| 202 | #define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ |
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| 203 | |||
| 204 | #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ |
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| 205 | #define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ |
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| 206 | |||
| 207 | #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ |
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| 208 | #define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ |
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| 209 | |||
| 210 | #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ |
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| 211 | #define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ |
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| 212 | |||
| 213 | #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ |
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| 214 | #define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ |
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| 215 | |||
| 216 | #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ |
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| 217 | #define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ |
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| 218 | |||
| 219 | #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ |
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| 220 | #define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ |
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| 221 | |||
| 222 | /* SCB Interrupt Control State Register Definitions */
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| 223 | #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ |
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| 224 | #define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ |
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| 225 | |||
| 226 | #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ |
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| 227 | #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ |
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| 228 | |||
| 229 | /* SCB Application Interrupt and Reset Control Register Definitions */
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| 230 | #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ |
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| 231 | #define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ |
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| 232 | |||
| 233 | #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ |
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| 234 | #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ |
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| 235 | |||
| 236 | #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ |
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| 237 | #define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ |
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| 238 | |||
| 239 | #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ |
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| 240 | #define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ |
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| 241 | |||
| 242 | #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ |
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| 243 | #define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ |
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| 244 | |||
| 245 | #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ |
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| 246 | #define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ |
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| 247 | |||
| 248 | #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ |
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| 249 | #define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ |
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| 250 | |||
| 251 | /* SCB System Control Register Definitions */
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| 252 | #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ |
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| 253 | #define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ |
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| 254 | |||
| 255 | #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ |
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| 256 | #define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ |
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| 257 | |||
| 258 | #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ |
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| 259 | #define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ |
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| 260 | |||
| 261 | /* SCB Configuration Control Register Definitions */
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| 262 | #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ |
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| 263 | #define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ |
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| 264 | |||
| 265 | #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ |
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| 266 | #define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ |
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| 267 | |||
| 268 | #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ |
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| 269 | #define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ |
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| 270 | |||
| 271 | #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ |
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| 272 | #define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ |
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| 273 | |||
| 274 | #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ |
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| 275 | #define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ |
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| 276 | |||
| 277 | #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ |
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| 278 | #define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ |
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| 279 | |||
| 280 | /* SCB System Handler Control and State Register Definitions */
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| 281 | #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ |
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| 282 | #define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ |
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| 283 | |||
| 284 | #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ |
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| 285 | #define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ |
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| 286 | |||
| 287 | #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ |
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| 288 | #define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ |
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| 289 | |||
| 290 | #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ |
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| 291 | #define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ |
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| 292 | |||
| 293 | #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ |
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| 294 | #define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ |
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| 295 | |||
| 296 | #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ |
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| 297 | #define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ |
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| 298 | |||
| 299 | #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ |
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| 300 | #define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ |
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| 301 | |||
| 302 | #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ |
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| 303 | #define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ |
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| 304 | |||
| 305 | #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ |
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| 306 | #define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ |
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| 307 | |||
| 308 | #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ |
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| 309 | #define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ |
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| 310 | |||
| 311 | #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ |
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| 312 | #define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ |
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| 313 | |||
| 314 | #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ |
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| 315 | #define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ |
||
| 316 | |||
| 317 | #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ |
||
| 318 | #define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ |
||
| 319 | |||
| 320 | #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ |
||
| 321 | #define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ |
||
| 322 | |||
| 323 | /* SCB Configurable Fault Status Registers Definitions */
|
||
| 324 | #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ |
||
| 325 | #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ |
||
| 326 | |||
| 327 | #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ |
||
| 328 | #define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ |
||
| 329 | |||
| 330 | #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ |
||
| 331 | #define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ |
||
| 332 | |||
| 333 | /* SCB Hard Fault Status Registers Definitions */
|
||
| 334 | #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ |
||
| 335 | #define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ |
||
| 336 | |||
| 337 | #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ |
||
| 338 | #define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ |
||
| 339 | |||
| 340 | #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ |
||
| 341 | #define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ |
||
| 342 | |||
| 343 | /* SCB Debug Fault Status Register Definitions */
|
||
| 344 | #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ |
||
| 345 | #define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ |
||
| 346 | |||
| 347 | #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ |
||
| 348 | #define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ |
||
| 349 | |||
| 350 | #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ |
||
| 351 | #define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ |
||
| 352 | |||
| 353 | #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ |
||
| 354 | #define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ |
||
| 355 | |||
| 356 | #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ |
||
| 357 | #define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ |
||
| 358 | /*@}*/ /* end of group CMSIS_CM3_SCB */ |
||
| 359 | |||
| 360 | |||
| 361 | /** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick
|
||
| 362 | memory mapped structure for SysTick
|
||
| 363 | @{
|
||
| 364 | */
|
||
| 365 | typedef struct |
||
| 366 | {
|
||
| 367 | __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */
|
||
| 368 | __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */
|
||
| 369 | __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */
|
||
| 370 | __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */
|
||
| 371 | } SysTick_Type; |
||
| 372 | |||
| 373 | /* SysTick Control / Status Register Definitions */
|
||
| 374 | #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ |
||
| 375 | #define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ |
||
| 376 | |||
| 377 | #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ |
||
| 378 | #define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ |
||
| 379 | |||
| 380 | #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ |
||
| 381 | #define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ |
||
| 382 | |||
| 383 | #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ |
||
| 384 | #define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ |
||
| 385 | |||
| 386 | /* SysTick Reload Register Definitions */
|
||
| 387 | #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ |
||
| 388 | #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ |
||
| 389 | |||
| 390 | /* SysTick Current Register Definitions */
|
||
| 391 | #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ |
||
| 392 | #define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ |
||
| 393 | |||
| 394 | /* SysTick Calibration Register Definitions */
|
||
| 395 | #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ |
||
| 396 | #define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ |
||
| 397 | |||
| 398 | #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ |
||
| 399 | #define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ |
||
| 400 | |||
| 401 | #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ |
||
| 402 | #define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ |
||
| 403 | /*@}*/ /* end of group CMSIS_CM3_SysTick */ |
||
| 404 | |||
| 405 | |||
| 406 | /** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM
|
||
| 407 | memory mapped structure for Instrumentation Trace Macrocell (ITM)
|
||
| 408 | @{
|
||
| 409 | */
|
||
| 410 | typedef struct |
||
| 411 | {
|
||
| 412 | __O union
|
||
| 413 | {
|
||
| 414 | __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */
|
||
| 415 | __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */
|
||
| 416 | __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */
|
||
| 417 | } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */ |
||
| 418 | uint32_t RESERVED0[864];
|
||
| 419 | __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */
|
||
| 420 | uint32_t RESERVED1[15];
|
||
| 421 | __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */
|
||
| 422 | uint32_t RESERVED2[15];
|
||
| 423 | __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */
|
||
| 424 | uint32_t RESERVED3[29];
|
||
| 425 | __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */
|
||
| 426 | __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */
|
||
| 427 | __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */
|
||
| 428 | uint32_t RESERVED4[43];
|
||
| 429 | __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */
|
||
| 430 | __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */
|
||
| 431 | uint32_t RESERVED5[6];
|
||
| 432 | __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */
|
||
| 433 | __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */
|
||
| 434 | __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */
|
||
| 435 | __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */
|
||
| 436 | __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */
|
||
| 437 | __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */
|
||
| 438 | __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */
|
||
| 439 | __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */
|
||
| 440 | __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */
|
||
| 441 | __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */
|
||
| 442 | __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */
|
||
| 443 | __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */
|
||
| 444 | } ITM_Type; |
||
| 445 | |||
| 446 | /* ITM Trace Privilege Register Definitions */
|
||
| 447 | #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ |
||
| 448 | #define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ |
||
| 449 | |||
| 450 | /* ITM Trace Control Register Definitions */
|
||
| 451 | #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ |
||
| 452 | #define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ |
||
| 453 | |||
| 454 | #define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */ |
||
| 455 | #define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */ |
||
| 456 | |||
| 457 | #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ |
||
| 458 | #define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ |
||
| 459 | |||
| 460 | #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ |
||
| 461 | #define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ |
||
| 462 | |||
| 463 | #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ |
||
| 464 | #define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ |
||
| 465 | |||
| 466 | #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ |
||
| 467 | #define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ |
||
| 468 | |||
| 469 | #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ |
||
| 470 | #define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ |
||
| 471 | |||
| 472 | #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ |
||
| 473 | #define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ |
||
| 474 | |||
| 475 | /* ITM Integration Write Register Definitions */
|
||
| 476 | #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ |
||
| 477 | #define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ |
||
| 478 | |||
| 479 | /* ITM Integration Read Register Definitions */
|
||
| 480 | #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ |
||
| 481 | #define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ |
||
| 482 | |||
| 483 | /* ITM Integration Mode Control Register Definitions */
|
||
| 484 | #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ |
||
| 485 | #define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ |
||
| 486 | |||
| 487 | /* ITM Lock Status Register Definitions */
|
||
| 488 | #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ |
||
| 489 | #define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ |
||
| 490 | |||
| 491 | #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ |
||
| 492 | #define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ |
||
| 493 | |||
| 494 | #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ |
||
| 495 | #define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ |
||
| 496 | /*@}*/ /* end of group CMSIS_CM3_ITM */ |
||
| 497 | |||
| 498 | |||
| 499 | /** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type
|
||
| 500 | memory mapped structure for Interrupt Type
|
||
| 501 | @{
|
||
| 502 | */
|
||
| 503 | typedef struct |
||
| 504 | {
|
||
| 505 | uint32_t RESERVED0; |
||
| 506 | __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */
|
||
| 507 | #if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) |
||
| 508 | __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */
|
||
| 509 | #else
|
||
| 510 | uint32_t RESERVED1; |
||
| 511 | #endif
|
||
| 512 | } InterruptType_Type; |
||
| 513 | |||
| 514 | /* Interrupt Controller Type Register Definitions */
|
||
| 515 | #define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */ |
||
| 516 | #define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */ |
||
| 517 | |||
| 518 | /* Auxiliary Control Register Definitions */
|
||
| 519 | #define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */ |
||
| 520 | #define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */ |
||
| 521 | |||
| 522 | #define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */ |
||
| 523 | #define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */ |
||
| 524 | |||
| 525 | #define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */ |
||
| 526 | #define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */ |
||
| 527 | /*@}*/ /* end of group CMSIS_CM3_InterruptType */ |
||
| 528 | |||
| 529 | |||
| 530 | #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) |
||
| 531 | /** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU
|
||
| 532 | memory mapped structure for Memory Protection Unit (MPU)
|
||
| 533 | @{
|
||
| 534 | */
|
||
| 535 | typedef struct |
||
| 536 | {
|
||
| 537 | __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */
|
||
| 538 | __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */
|
||
| 539 | __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */
|
||
| 540 | __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */
|
||
| 541 | __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */
|
||
| 542 | __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */
|
||
| 543 | __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */
|
||
| 544 | __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */
|
||
| 545 | __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */
|
||
| 546 | __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */
|
||
| 547 | __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */
|
||
| 548 | } MPU_Type; |
||
| 549 | |||
| 550 | /* MPU Type Register */
|
||
| 551 | #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ |
||
| 552 | #define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ |
||
| 553 | |||
| 554 | #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ |
||
| 555 | #define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ |
||
| 556 | |||
| 557 | #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ |
||
| 558 | #define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ |
||
| 559 | |||
| 560 | /* MPU Control Register */
|
||
| 561 | #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ |
||
| 562 | #define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ |
||
| 563 | |||
| 564 | #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ |
||
| 565 | #define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ |
||
| 566 | |||
| 567 | #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ |
||
| 568 | #define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ |
||
| 569 | |||
| 570 | /* MPU Region Number Register */
|
||
| 571 | #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ |
||
| 572 | #define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ |
||
| 573 | |||
| 574 | /* MPU Region Base Address Register */
|
||
| 575 | #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ |
||
| 576 | #define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ |
||
| 577 | |||
| 578 | #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ |
||
| 579 | #define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ |
||
| 580 | |||
| 581 | #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ |
||
| 582 | #define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ |
||
| 583 | |||
| 584 | /* MPU Region Attribute and Size Register */
|
||
| 585 | #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */ |
||
| 586 | #define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */ |
||
| 587 | |||
| 588 | #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */ |
||
| 589 | #define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */ |
||
| 590 | |||
| 591 | #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */ |
||
| 592 | #define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */ |
||
| 593 | |||
| 594 | #define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */ |
||
| 595 | #define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */ |
||
| 596 | |||
| 597 | #define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */ |
||
| 598 | #define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */ |
||
| 599 | |||
| 600 | #define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */ |
||
| 601 | #define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */ |
||
| 602 | |||
| 603 | #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ |
||
| 604 | #define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ |
||
| 605 | |||
| 606 | #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ |
||
| 607 | #define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ |
||
| 608 | |||
| 609 | #define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */ |
||
| 610 | #define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ |
||
| 611 | |||
| 612 | /*@}*/ /* end of group CMSIS_CM3_MPU */ |
||
| 613 | #endif
|
||
| 614 | |||
| 615 | |||
| 616 | /** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug
|
||
| 617 | memory mapped structure for Core Debug Register
|
||
| 618 | @{
|
||
| 619 | */
|
||
| 620 | typedef struct |
||
| 621 | {
|
||
| 622 | __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */
|
||
| 623 | __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */
|
||
| 624 | __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */
|
||
| 625 | __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */
|
||
| 626 | } CoreDebug_Type; |
||
| 627 | |||
| 628 | /* Debug Halting Control and Status Register */
|
||
| 629 | #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ |
||
| 630 | #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ |
||
| 631 | |||
| 632 | #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ |
||
| 633 | #define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ |
||
| 634 | |||
| 635 | #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ |
||
| 636 | #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ |
||
| 637 | |||
| 638 | #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ |
||
| 639 | #define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ |
||
| 640 | |||
| 641 | #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ |
||
| 642 | #define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ |
||
| 643 | |||
| 644 | #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ |
||
| 645 | #define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ |
||
| 646 | |||
| 647 | #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ |
||
| 648 | #define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ |
||
| 649 | |||
| 650 | #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ |
||
| 651 | #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ |
||
| 652 | |||
| 653 | #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ |
||
| 654 | #define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ |
||
| 655 | |||
| 656 | #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ |
||
| 657 | #define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ |
||
| 658 | |||
| 659 | #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ |
||
| 660 | #define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ |
||
| 661 | |||
| 662 | #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ |
||
| 663 | #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ |
||
| 664 | |||
| 665 | /* Debug Core Register Selector Register */
|
||
| 666 | #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ |
||
| 667 | #define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ |
||
| 668 | |||
| 669 | #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ |
||
| 670 | #define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ |
||
| 671 | |||
| 672 | /* Debug Exception and Monitor Control Register */
|
||
| 673 | #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ |
||
| 674 | #define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ |
||
| 675 | |||
| 676 | #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ |
||
| 677 | #define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ |
||
| 678 | |||
| 679 | #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ |
||
| 680 | #define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ |
||
| 681 | |||
| 682 | #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ |
||
| 683 | #define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ |
||
| 684 | |||
| 685 | #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ |
||
| 686 | #define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ |
||
| 687 | |||
| 688 | #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ |
||
| 689 | #define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ |
||
| 690 | |||
| 691 | #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ |
||
| 692 | #define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ |
||
| 693 | |||
| 694 | #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ |
||
| 695 | #define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ |
||
| 696 | |||
| 697 | #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ |
||
| 698 | #define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ |
||
| 699 | |||
| 700 | #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ |
||
| 701 | #define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ |
||
| 702 | |||
| 703 | #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ |
||
| 704 | #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ |
||
| 705 | |||
| 706 | #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ |
||
| 707 | #define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ |
||
| 708 | |||
| 709 | #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ |
||
| 710 | #define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ |
||
| 711 | /*@}*/ /* end of group CMSIS_CM3_CoreDebug */ |
||
| 712 | |||
| 713 | |||
| 714 | /* Memory mapping of Cortex-M3 Hardware */
|
||
| 715 | #define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */ |
||
| 716 | #define ITM_BASE (0xE0000000) /*!< ITM Base Address */ |
||
| 717 | #define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */ |
||
| 718 | #define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */ |
||
| 719 | #define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */ |
||
| 720 | #define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */ |
||
| 721 | |||
| 722 | #define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */ |
||
| 723 | #define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */ |
||
| 724 | #define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */ |
||
| 725 | #define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */ |
||
| 726 | #define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */ |
||
| 727 | #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ |
||
| 728 | |||
| 729 | #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) |
||
| 730 | #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */ |
||
| 731 | #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */ |
||
| 732 | #endif
|
||
| 733 | |||
| 734 | /*@}*/ /* end of group CMSIS_CM3_core_register */ |
||
| 735 | |||
| 736 | |||
| 737 | /*******************************************************************************
|
||
| 738 | * Hardware Abstraction Layer
|
||
| 739 | ******************************************************************************/
|
||
| 740 | |||
| 741 | #if defined ( __CC_ARM )
|
||
| 742 | #define __ASM __asm /*!< asm keyword for ARM Compiler */ |
||
| 743 | #define __INLINE __inline /*!< inline keyword for ARM Compiler */ |
||
| 744 | |||
| 745 | #elif defined ( __ICCARM__ )
|
||
| 746 | #define __ASM __asm /*!< asm keyword for IAR Compiler */ |
||
| 747 | #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ |
||
| 748 | |||
| 749 | #elif defined ( __GNUC__ )
|
||
| 750 | #define __ASM __asm /*!< asm keyword for GNU Compiler */ |
||
| 751 | #define __INLINE inline /*!< inline keyword for GNU Compiler */ |
||
| 752 | |||
| 753 | #elif defined ( __TASKING__ )
|
||
| 754 | #define __ASM __asm /*!< asm keyword for TASKING Compiler */ |
||
| 755 | #define __INLINE inline /*!< inline keyword for TASKING Compiler */ |
||
| 756 | |||
| 757 | #endif
|
||
| 758 | |||
| 759 | |||
| 760 | /* ################### Compiler specific Intrinsics ########################### */
|
||
| 761 | |||
| 762 | #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ |
||
| 763 | /* ARM armcc specific functions */
|
||
| 764 | |||
| 765 | #define __enable_fault_irq __enable_fiq
|
||
| 766 | #define __disable_fault_irq __disable_fiq
|
||
| 767 | |||
| 768 | #define __NOP __nop
|
||
| 769 | #define __WFI __wfi
|
||
| 770 | #define __WFE __wfe
|
||
| 771 | #define __SEV __sev
|
||
| 772 | #define __ISB() __isb(0) |
||
| 773 | #define __DSB() __dsb(0) |
||
| 774 | #define __DMB() __dmb(0) |
||
| 775 | #define __REV __rev
|
||
| 776 | #define __RBIT __rbit
|
||
| 777 | #define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr)) |
||
| 778 | #define __LDREXH(ptr) ((unsigned short) __ldrex(ptr)) |
||
| 779 | #define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr)) |
||
| 780 | #define __STREXB(value, ptr) __strex(value, ptr)
|
||
| 781 | #define __STREXH(value, ptr) __strex(value, ptr)
|
||
| 782 | #define __STREXW(value, ptr) __strex(value, ptr)
|
||
| 783 | |||
| 784 | |||
| 785 | /* intrinsic unsigned long long __ldrexd(volatile void *ptr) */
|
||
| 786 | /* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */
|
||
| 787 | /* intrinsic void __enable_irq(); */
|
||
| 788 | /* intrinsic void __disable_irq(); */
|
||
| 789 | |||
| 790 | |||
| 791 | /**
|
||
| 792 | * @brief Return the Process Stack Pointer
|
||
| 793 | *
|
||
| 794 | * @return ProcessStackPointer
|
||
| 795 | *
|
||
| 796 | * Return the actual process stack pointer
|
||
| 797 | */
|
||
| 798 | extern uint32_t __get_PSP(void); |
||
| 799 | |||
| 800 | /**
|
||
| 801 | * @brief Set the Process Stack Pointer
|
||
| 802 | *
|
||
| 803 | * @param topOfProcStack Process Stack Pointer
|
||
| 804 | *
|
||
| 805 | * Assign the value ProcessStackPointer to the MSP
|
||
| 806 | * (process stack pointer) Cortex processor register
|
||
| 807 | */
|
||
| 808 | extern void __set_PSP(uint32_t topOfProcStack); |
||
| 809 | |||
| 810 | /**
|
||
| 811 | * @brief Return the Main Stack Pointer
|
||
| 812 | *
|
||
| 813 | * @return Main Stack Pointer
|
||
| 814 | *
|
||
| 815 | * Return the current value of the MSP (main stack pointer)
|
||
| 816 | * Cortex processor register
|
||
| 817 | */
|
||
| 818 | extern uint32_t __get_MSP(void); |
||
| 819 | |||
| 820 | /**
|
||
| 821 | * @brief Set the Main Stack Pointer
|
||
| 822 | *
|
||
| 823 | * @param topOfMainStack Main Stack Pointer
|
||
| 824 | *
|
||
| 825 | * Assign the value mainStackPointer to the MSP
|
||
| 826 | * (main stack pointer) Cortex processor register
|
||
| 827 | */
|
||
| 828 | extern void __set_MSP(uint32_t topOfMainStack); |
||
| 829 | |||
| 830 | /**
|
||
| 831 | * @brief Reverse byte order in unsigned short value
|
||
| 832 | *
|
||
| 833 | * @param value value to reverse
|
||
| 834 | * @return reversed value
|
||
| 835 | *
|
||
| 836 | * Reverse byte order in unsigned short value
|
||
| 837 | */
|
||
| 838 | extern uint32_t __REV16(uint16_t value);
|
||
| 839 | |||
| 840 | /**
|
||
| 841 | * @brief Reverse byte order in signed short value with sign extension to integer
|
||
| 842 | *
|
||
| 843 | * @param value value to reverse
|
||
| 844 | * @return reversed value
|
||
| 845 | *
|
||
| 846 | * Reverse byte order in signed short value with sign extension to integer
|
||
| 847 | */
|
||
| 848 | extern int32_t __REVSH(int16_t value);
|
||
| 849 | |||
| 850 | |||
| 851 | #if (__ARMCC_VERSION < 400000) |
||
| 852 | |||
| 853 | /**
|
||
| 854 | * @brief Remove the exclusive lock created by ldrex
|
||
| 855 | *
|
||
| 856 | * Removes the exclusive lock which is created by ldrex.
|
||
| 857 | */
|
||
| 858 | extern void __CLREX(void); |
||
| 859 | |||
| 860 | /**
|
||
| 861 | * @brief Return the Base Priority value
|
||
| 862 | *
|
||
| 863 | * @return BasePriority
|
||
| 864 | *
|
||
| 865 | * Return the content of the base priority register
|
||
| 866 | */
|
||
| 867 | extern uint32_t __get_BASEPRI(void); |
||
| 868 | |||
| 869 | /**
|
||
| 870 | * @brief Set the Base Priority value
|
||
| 871 | *
|
||
| 872 | * @param basePri BasePriority
|
||
| 873 | *
|
||
| 874 | * Set the base priority register
|
||
| 875 | */
|
||
| 876 | extern void __set_BASEPRI(uint32_t basePri); |
||
| 877 | |||
| 878 | /**
|
||
| 879 | * @brief Return the Priority Mask value
|
||
| 880 | *
|
||
| 881 | * @return PriMask
|
||
| 882 | *
|
||
| 883 | * Return state of the priority mask bit from the priority mask register
|
||
| 884 | */
|
||
| 885 | extern uint32_t __get_PRIMASK(void); |
||
| 886 | |||
| 887 | /**
|
||
| 888 | * @brief Set the Priority Mask value
|
||
| 889 | *
|
||
| 890 | * @param priMask PriMask
|
||
| 891 | *
|
||
| 892 | * Set the priority mask bit in the priority mask register
|
||
| 893 | */
|
||
| 894 | extern void __set_PRIMASK(uint32_t priMask); |
||
| 895 | |||
| 896 | /**
|
||
| 897 | * @brief Return the Fault Mask value
|
||
| 898 | *
|
||
| 899 | * @return FaultMask
|
||
| 900 | *
|
||
| 901 | * Return the content of the fault mask register
|
||
| 902 | */
|
||
| 903 | extern uint32_t __get_FAULTMASK(void); |
||
| 904 | |||
| 905 | /**
|
||
| 906 | * @brief Set the Fault Mask value
|
||
| 907 | *
|
||
| 908 | * @param faultMask faultMask value
|
||
| 909 | *
|
||
| 910 | * Set the fault mask register
|
||
| 911 | */
|
||
| 912 | extern void __set_FAULTMASK(uint32_t faultMask); |
||
| 913 | |||
| 914 | /**
|
||
| 915 | * @brief Return the Control Register value
|
||
| 916 | *
|
||
| 917 | * @return Control value
|
||
| 918 | *
|
||
| 919 | * Return the content of the control register
|
||
| 920 | */
|
||
| 921 | extern uint32_t __get_CONTROL(void); |
||
| 922 | |||
| 923 | /**
|
||
| 924 | * @brief Set the Control Register value
|
||
| 925 | *
|
||
| 926 | * @param control Control value
|
||
| 927 | *
|
||
| 928 | * Set the control register
|
||
| 929 | */
|
||
| 930 | extern void __set_CONTROL(uint32_t control); |
||
| 931 | |||
| 932 | #else /* (__ARMCC_VERSION >= 400000) */ |
||
| 933 | |||
| 934 | /**
|
||
| 935 | * @brief Remove the exclusive lock created by ldrex
|
||
| 936 | *
|
||
| 937 | * Removes the exclusive lock which is created by ldrex.
|
||
| 938 | */
|
||
| 939 | #define __CLREX __clrex
|
||
| 940 | |||
| 941 | /**
|
||
| 942 | * @brief Return the Base Priority value
|
||
| 943 | *
|
||
| 944 | * @return BasePriority
|
||
| 945 | *
|
||
| 946 | * Return the content of the base priority register
|
||
| 947 | */
|
||
| 948 | static __INLINE uint32_t __get_BASEPRI(void) |
||
| 949 | {
|
||
| 950 | register uint32_t __regBasePri __ASM("basepri"); |
||
| 951 | return(__regBasePri);
|
||
| 952 | } |
||
| 953 | |||
| 954 | /**
|
||
| 955 | * @brief Set the Base Priority value
|
||
| 956 | *
|
||
| 957 | * @param basePri BasePriority
|
||
| 958 | *
|
||
| 959 | * Set the base priority register
|
||
| 960 | */
|
||
| 961 | static __INLINE void __set_BASEPRI(uint32_t basePri) |
||
| 962 | {
|
||
| 963 | register uint32_t __regBasePri __ASM("basepri"); |
||
| 964 | __regBasePri = (basePri & 0xff);
|
||
| 965 | } |
||
| 966 | |||
| 967 | /**
|
||
| 968 | * @brief Return the Priority Mask value
|
||
| 969 | *
|
||
| 970 | * @return PriMask
|
||
| 971 | *
|
||
| 972 | * Return state of the priority mask bit from the priority mask register
|
||
| 973 | */
|
||
| 974 | static __INLINE uint32_t __get_PRIMASK(void) |
||
| 975 | {
|
||
| 976 | register uint32_t __regPriMask __ASM("primask"); |
||
| 977 | return(__regPriMask);
|
||
| 978 | } |
||
| 979 | |||
| 980 | /**
|
||
| 981 | * @brief Set the Priority Mask value
|
||
| 982 | *
|
||
| 983 | * @param priMask PriMask
|
||
| 984 | *
|
||
| 985 | * Set the priority mask bit in the priority mask register
|
||
| 986 | */
|
||
| 987 | static __INLINE void __set_PRIMASK(uint32_t priMask) |
||
| 988 | {
|
||
| 989 | register uint32_t __regPriMask __ASM("primask"); |
||
| 990 | __regPriMask = (priMask); |
||
| 991 | } |
||
| 992 | |||
| 993 | /**
|
||
| 994 | * @brief Return the Fault Mask value
|
||
| 995 | *
|
||
| 996 | * @return FaultMask
|
||
| 997 | *
|
||
| 998 | * Return the content of the fault mask register
|
||
| 999 | */
|
||
| 1000 | static __INLINE uint32_t __get_FAULTMASK(void) |
||
| 1001 | {
|
||
| 1002 | register uint32_t __regFaultMask __ASM("faultmask"); |
||
| 1003 | return(__regFaultMask);
|
||
| 1004 | } |
||
| 1005 | |||
| 1006 | /**
|
||
| 1007 | * @brief Set the Fault Mask value
|
||
| 1008 | *
|
||
| 1009 | * @param faultMask faultMask value
|
||
| 1010 | *
|
||
| 1011 | * Set the fault mask register
|
||
| 1012 | */
|
||
| 1013 | static __INLINE void __set_FAULTMASK(uint32_t faultMask) |
||
| 1014 | {
|
||
| 1015 | register uint32_t __regFaultMask __ASM("faultmask"); |
||
| 1016 | __regFaultMask = (faultMask & 1);
|
||
| 1017 | } |
||
| 1018 | |||
| 1019 | /**
|
||
| 1020 | * @brief Return the Control Register value
|
||
| 1021 | *
|
||
| 1022 | * @return Control value
|
||
| 1023 | *
|
||
| 1024 | * Return the content of the control register
|
||
| 1025 | */
|
||
| 1026 | static __INLINE uint32_t __get_CONTROL(void) |
||
| 1027 | {
|
||
| 1028 | register uint32_t __regControl __ASM("control"); |
||
| 1029 | return(__regControl);
|
||
| 1030 | } |
||
| 1031 | |||
| 1032 | /**
|
||
| 1033 | * @brief Set the Control Register value
|
||
| 1034 | *
|
||
| 1035 | * @param control Control value
|
||
| 1036 | *
|
||
| 1037 | * Set the control register
|
||
| 1038 | */
|
||
| 1039 | static __INLINE void __set_CONTROL(uint32_t control) |
||
| 1040 | {
|
||
| 1041 | register uint32_t __regControl __ASM("control"); |
||
| 1042 | __regControl = control; |
||
| 1043 | } |
||
| 1044 | |||
| 1045 | #endif /* __ARMCC_VERSION */ |
||
| 1046 | |||
| 1047 | |||
| 1048 | |||
| 1049 | #elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ |
||
| 1050 | /* IAR iccarm specific functions */
|
||
| 1051 | |||
| 1052 | #define __enable_irq __enable_interrupt /*!< global Interrupt enable */ |
||
| 1053 | #define __disable_irq __disable_interrupt /*!< global Interrupt disable */ |
||
| 1054 | |||
| 1055 | static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); } |
||
| 1056 | static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); } |
||
| 1057 | |||
| 1058 | #define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */ |
||
| 1059 | static __INLINE void __WFI() { __ASM ("wfi"); } |
||
| 1060 | static __INLINE void __WFE() { __ASM ("wfe"); } |
||
| 1061 | static __INLINE void __SEV() { __ASM ("sev"); } |
||
| 1062 | static __INLINE void __CLREX() { __ASM ("clrex"); } |
||
| 1063 | |||
| 1064 | /* intrinsic void __ISB(void) */
|
||
| 1065 | /* intrinsic void __DSB(void) */
|
||
| 1066 | /* intrinsic void __DMB(void) */
|
||
| 1067 | /* intrinsic void __set_PRIMASK(); */
|
||
| 1068 | /* intrinsic void __get_PRIMASK(); */
|
||
| 1069 | /* intrinsic void __set_FAULTMASK(); */
|
||
| 1070 | /* intrinsic void __get_FAULTMASK(); */
|
||
| 1071 | /* intrinsic uint32_t __REV(uint32_t value); */
|
||
| 1072 | /* intrinsic uint32_t __REVSH(uint32_t value); */
|
||
| 1073 | /* intrinsic unsigned long __STREX(unsigned long, unsigned long); */
|
||
| 1074 | /* intrinsic unsigned long __LDREX(unsigned long *); */
|
||
| 1075 | |||
| 1076 | |||
| 1077 | /**
|
||
| 1078 | * @brief Return the Process Stack Pointer
|
||
| 1079 | *
|
||
| 1080 | * @return ProcessStackPointer
|
||
| 1081 | *
|
||
| 1082 | * Return the actual process stack pointer
|
||
| 1083 | */
|
||
| 1084 | extern uint32_t __get_PSP(void); |
||
| 1085 | |||
| 1086 | /**
|
||
| 1087 | * @brief Set the Process Stack Pointer
|
||
| 1088 | *
|
||
| 1089 | * @param topOfProcStack Process Stack Pointer
|
||
| 1090 | *
|
||
| 1091 | * Assign the value ProcessStackPointer to the MSP
|
||
| 1092 | * (process stack pointer) Cortex processor register
|
||
| 1093 | */
|
||
| 1094 | extern void __set_PSP(uint32_t topOfProcStack); |
||
| 1095 | |||
| 1096 | /**
|
||
| 1097 | * @brief Return the Main Stack Pointer
|
||
| 1098 | *
|
||
| 1099 | * @return Main Stack Pointer
|
||
| 1100 | *
|
||
| 1101 | * Return the current value of the MSP (main stack pointer)
|
||
| 1102 | * Cortex processor register
|
||
| 1103 | */
|
||
| 1104 | extern uint32_t __get_MSP(void); |
||
| 1105 | |||
| 1106 | /**
|
||
| 1107 | * @brief Set the Main Stack Pointer
|
||
| 1108 | *
|
||
| 1109 | * @param topOfMainStack Main Stack Pointer
|
||
| 1110 | *
|
||
| 1111 | * Assign the value mainStackPointer to the MSP
|
||
| 1112 | * (main stack pointer) Cortex processor register
|
||
| 1113 | */
|
||
| 1114 | extern void __set_MSP(uint32_t topOfMainStack); |
||
| 1115 | |||
| 1116 | /**
|
||
| 1117 | * @brief Reverse byte order in unsigned short value
|
||
| 1118 | *
|
||
| 1119 | * @param value value to reverse
|
||
| 1120 | * @return reversed value
|
||
| 1121 | *
|
||
| 1122 | * Reverse byte order in unsigned short value
|
||
| 1123 | */
|
||
| 1124 | extern uint32_t __REV16(uint16_t value);
|
||
| 1125 | |||
| 1126 | /**
|
||
| 1127 | * @brief Reverse bit order of value
|
||
| 1128 | *
|
||
| 1129 | * @param value value to reverse
|
||
| 1130 | * @return reversed value
|
||
| 1131 | *
|
||
| 1132 | * Reverse bit order of value
|
||
| 1133 | */
|
||
| 1134 | extern uint32_t __RBIT(uint32_t value);
|
||
| 1135 | |||
| 1136 | /**
|
||
| 1137 | * @brief LDR Exclusive (8 bit)
|
||
| 1138 | *
|
||
| 1139 | * @param *addr address pointer
|
||
| 1140 | * @return value of (*address)
|
||
| 1141 | *
|
||
| 1142 | * Exclusive LDR command for 8 bit values)
|
||
| 1143 | */
|
||
| 1144 | extern uint8_t __LDREXB(uint8_t *addr);
|
||
| 1145 | |||
| 1146 | /**
|
||
| 1147 | * @brief LDR Exclusive (16 bit)
|
||
| 1148 | *
|
||
| 1149 | * @param *addr address pointer
|
||
| 1150 | * @return value of (*address)
|
||
| 1151 | *
|
||
| 1152 | * Exclusive LDR command for 16 bit values
|
||
| 1153 | */
|
||
| 1154 | extern uint16_t __LDREXH(uint16_t *addr);
|
||
| 1155 | |||
| 1156 | /**
|
||
| 1157 | * @brief LDR Exclusive (32 bit)
|
||
| 1158 | *
|
||
| 1159 | * @param *addr address pointer
|
||
| 1160 | * @return value of (*address)
|
||
| 1161 | *
|
||
| 1162 | * Exclusive LDR command for 32 bit values
|
||
| 1163 | */
|
||
| 1164 | extern uint32_t __LDREXW(uint32_t *addr);
|
||
| 1165 | |||
| 1166 | /**
|
||
| 1167 | * @brief STR Exclusive (8 bit)
|
||
| 1168 | *
|
||
| 1169 | * @param value value to store
|
||
| 1170 | * @param *addr address pointer
|
||
| 1171 | * @return successful / failed
|
||
| 1172 | *
|
||
| 1173 | * Exclusive STR command for 8 bit values
|
||
| 1174 | */
|
||
| 1175 | extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
|
||
| 1176 | |||
| 1177 | /**
|
||
| 1178 | * @brief STR Exclusive (16 bit)
|
||
| 1179 | *
|
||
| 1180 | * @param value value to store
|
||
| 1181 | * @param *addr address pointer
|
||
| 1182 | * @return successful / failed
|
||
| 1183 | *
|
||
| 1184 | * Exclusive STR command for 16 bit values
|
||
| 1185 | */
|
||
| 1186 | extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
|
||
| 1187 | |||
| 1188 | /**
|
||
| 1189 | * @brief STR Exclusive (32 bit)
|
||
| 1190 | *
|
||
| 1191 | * @param value value to store
|
||
| 1192 | * @param *addr address pointer
|
||
| 1193 | * @return successful / failed
|
||
| 1194 | *
|
||
| 1195 | * Exclusive STR command for 32 bit values
|
||
| 1196 | */
|
||
| 1197 | extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
|
||
| 1198 | |||
| 1199 | |||
| 1200 | |||
| 1201 | #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ |
||
| 1202 | /* GNU gcc specific functions */
|
||
| 1203 | |||
| 1204 | static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); } |
||
| 1205 | static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); } |
||
| 1206 | |||
| 1207 | static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); } |
||
| 1208 | static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); } |
||
| 1209 | |||
| 1210 | static __INLINE void __NOP() { __ASM volatile ("nop"); } |
||
| 1211 | static __INLINE void __WFI() { __ASM volatile ("wfi"); } |
||
| 1212 | static __INLINE void __WFE() { __ASM volatile ("wfe"); } |
||
| 1213 | static __INLINE void __SEV() { __ASM volatile ("sev"); } |
||
| 1214 | static __INLINE void __ISB() { __ASM volatile ("isb"); } |
||
| 1215 | static __INLINE void __DSB() { __ASM volatile ("dsb"); } |
||
| 1216 | static __INLINE void __DMB() { __ASM volatile ("dmb"); } |
||
| 1217 | static __INLINE void __CLREX() { __ASM volatile ("clrex"); } |
||
| 1218 | |||
| 1219 | |||
| 1220 | /**
|
||
| 1221 | * @brief Return the Process Stack Pointer
|
||
| 1222 | *
|
||
| 1223 | * @return ProcessStackPointer
|
||
| 1224 | *
|
||
| 1225 | * Return the actual process stack pointer
|
||
| 1226 | */
|
||
| 1227 | extern uint32_t __get_PSP(void); |
||
| 1228 | |||
| 1229 | /**
|
||
| 1230 | * @brief Set the Process Stack Pointer
|
||
| 1231 | *
|
||
| 1232 | * @param topOfProcStack Process Stack Pointer
|
||
| 1233 | *
|
||
| 1234 | * Assign the value ProcessStackPointer to the MSP
|
||
| 1235 | * (process stack pointer) Cortex processor register
|
||
| 1236 | */
|
||
| 1237 | extern void __set_PSP(uint32_t topOfProcStack); |
||
| 1238 | |||
| 1239 | /**
|
||
| 1240 | * @brief Return the Main Stack Pointer
|
||
| 1241 | *
|
||
| 1242 | * @return Main Stack Pointer
|
||
| 1243 | *
|
||
| 1244 | * Return the current value of the MSP (main stack pointer)
|
||
| 1245 | * Cortex processor register
|
||
| 1246 | */
|
||
| 1247 | extern uint32_t __get_MSP(void); |
||
| 1248 | |||
| 1249 | /**
|
||
| 1250 | * @brief Set the Main Stack Pointer
|
||
| 1251 | *
|
||
| 1252 | * @param topOfMainStack Main Stack Pointer
|
||
| 1253 | *
|
||
| 1254 | * Assign the value mainStackPointer to the MSP
|
||
| 1255 | * (main stack pointer) Cortex processor register
|
||
| 1256 | */
|
||
| 1257 | extern void __set_MSP(uint32_t topOfMainStack); |
||
| 1258 | |||
| 1259 | /**
|
||
| 1260 | * @brief Return the Base Priority value
|
||
| 1261 | *
|
||
| 1262 | * @return BasePriority
|
||
| 1263 | *
|
||
| 1264 | * Return the content of the base priority register
|
||
| 1265 | */
|
||
| 1266 | extern uint32_t __get_BASEPRI(void); |
||
| 1267 | |||
| 1268 | /**
|
||
| 1269 | * @brief Set the Base Priority value
|
||
| 1270 | *
|
||
| 1271 | * @param basePri BasePriority
|
||
| 1272 | *
|
||
| 1273 | * Set the base priority register
|
||
| 1274 | */
|
||
| 1275 | extern void __set_BASEPRI(uint32_t basePri); |
||
| 1276 | |||
| 1277 | /**
|
||
| 1278 | * @brief Return the Priority Mask value
|
||
| 1279 | *
|
||
| 1280 | * @return PriMask
|
||
| 1281 | *
|
||
| 1282 | * Return state of the priority mask bit from the priority mask register
|
||
| 1283 | */
|
||
| 1284 | extern uint32_t __get_PRIMASK(void); |
||
| 1285 | |||
| 1286 | /**
|
||
| 1287 | * @brief Set the Priority Mask value
|
||
| 1288 | *
|
||
| 1289 | * @param priMask PriMask
|
||
| 1290 | *
|
||
| 1291 | * Set the priority mask bit in the priority mask register
|
||
| 1292 | */
|
||
| 1293 | extern void __set_PRIMASK(uint32_t priMask); |
||
| 1294 | |||
| 1295 | /**
|
||
| 1296 | * @brief Return the Fault Mask value
|
||
| 1297 | *
|
||
| 1298 | * @return FaultMask
|
||
| 1299 | *
|
||
| 1300 | * Return the content of the fault mask register
|
||
| 1301 | */
|
||
| 1302 | extern uint32_t __get_FAULTMASK(void); |
||
| 1303 | |||
| 1304 | /**
|
||
| 1305 | * @brief Set the Fault Mask value
|
||
| 1306 | *
|
||
| 1307 | * @param faultMask faultMask value
|
||
| 1308 | *
|
||
| 1309 | * Set the fault mask register
|
||
| 1310 | */
|
||
| 1311 | extern void __set_FAULTMASK(uint32_t faultMask); |
||
| 1312 | |||
| 1313 | /**
|
||
| 1314 | * @brief Return the Control Register value
|
||
| 1315 | *
|
||
| 1316 | * @return Control value
|
||
| 1317 | *
|
||
| 1318 | * Return the content of the control register
|
||
| 1319 | */
|
||
| 1320 | extern uint32_t __get_CONTROL(void); |
||
| 1321 | |||
| 1322 | /**
|
||
| 1323 | * @brief Set the Control Register value
|
||
| 1324 | *
|
||
| 1325 | * @param control Control value
|
||
| 1326 | *
|
||
| 1327 | * Set the control register
|
||
| 1328 | */
|
||
| 1329 | extern void __set_CONTROL(uint32_t control); |
||
| 1330 | |||
| 1331 | /**
|
||
| 1332 | * @brief Reverse byte order in integer value
|
||
| 1333 | *
|
||
| 1334 | * @param value value to reverse
|
||
| 1335 | * @return reversed value
|
||
| 1336 | *
|
||
| 1337 | * Reverse byte order in integer value
|
||
| 1338 | */
|
||
| 1339 | extern uint32_t __REV(uint32_t value);
|
||
| 1340 | |||
| 1341 | /**
|
||
| 1342 | * @brief Reverse byte order in unsigned short value
|
||
| 1343 | *
|
||
| 1344 | * @param value value to reverse
|
||
| 1345 | * @return reversed value
|
||
| 1346 | *
|
||
| 1347 | * Reverse byte order in unsigned short value
|
||
| 1348 | */
|
||
| 1349 | extern uint32_t __REV16(uint16_t value);
|
||
| 1350 | |||
| 1351 | /**
|
||
| 1352 | * @brief Reverse byte order in signed short value with sign extension to integer
|
||
| 1353 | *
|
||
| 1354 | * @param value value to reverse
|
||
| 1355 | * @return reversed value
|
||
| 1356 | *
|
||
| 1357 | * Reverse byte order in signed short value with sign extension to integer
|
||
| 1358 | */
|
||
| 1359 | extern int32_t __REVSH(int16_t value);
|
||
| 1360 | |||
| 1361 | /**
|
||
| 1362 | * @brief Reverse bit order of value
|
||
| 1363 | *
|
||
| 1364 | * @param value value to reverse
|
||
| 1365 | * @return reversed value
|
||
| 1366 | *
|
||
| 1367 | * Reverse bit order of value
|
||
| 1368 | */
|
||
| 1369 | extern uint32_t __RBIT(uint32_t value);
|
||
| 1370 | |||
| 1371 | /**
|
||
| 1372 | * @brief LDR Exclusive (8 bit)
|
||
| 1373 | *
|
||
| 1374 | * @param *addr address pointer
|
||
| 1375 | * @return value of (*address)
|
||
| 1376 | *
|
||
| 1377 | * Exclusive LDR command for 8 bit value
|
||
| 1378 | */
|
||
| 1379 | extern uint8_t __LDREXB(uint8_t *addr);
|
||
| 1380 | |||
| 1381 | /**
|
||
| 1382 | * @brief LDR Exclusive (16 bit)
|
||
| 1383 | *
|
||
| 1384 | * @param *addr address pointer
|
||
| 1385 | * @return value of (*address)
|
||
| 1386 | *
|
||
| 1387 | * Exclusive LDR command for 16 bit values
|
||
| 1388 | */
|
||
| 1389 | extern uint16_t __LDREXH(uint16_t *addr);
|
||
| 1390 | |||
| 1391 | /**
|
||
| 1392 | * @brief LDR Exclusive (32 bit)
|
||
| 1393 | *
|
||
| 1394 | * @param *addr address pointer
|
||
| 1395 | * @return value of (*address)
|
||
| 1396 | *
|
||
| 1397 | * Exclusive LDR command for 32 bit values
|
||
| 1398 | */
|
||
| 1399 | extern uint32_t __LDREXW(uint32_t *addr);
|
||
| 1400 | |||
| 1401 | /**
|
||
| 1402 | * @brief STR Exclusive (8 bit)
|
||
| 1403 | *
|
||
| 1404 | * @param value value to store
|
||
| 1405 | * @param *addr address pointer
|
||
| 1406 | * @return successful / failed
|
||
| 1407 | *
|
||
| 1408 | * Exclusive STR command for 8 bit values
|
||
| 1409 | */
|
||
| 1410 | extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
|
||
| 1411 | |||
| 1412 | /**
|
||
| 1413 | * @brief STR Exclusive (16 bit)
|
||
| 1414 | *
|
||
| 1415 | * @param value value to store
|
||
| 1416 | * @param *addr address pointer
|
||
| 1417 | * @return successful / failed
|
||
| 1418 | *
|
||
| 1419 | * Exclusive STR command for 16 bit values
|
||
| 1420 | */
|
||
| 1421 | extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
|
||
| 1422 | |||
| 1423 | /**
|
||
| 1424 | * @brief STR Exclusive (32 bit)
|
||
| 1425 | *
|
||
| 1426 | * @param value value to store
|
||
| 1427 | * @param *addr address pointer
|
||
| 1428 | * @return successful / failed
|
||
| 1429 | *
|
||
| 1430 | * Exclusive STR command for 32 bit values
|
||
| 1431 | */
|
||
| 1432 | extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
|
||
| 1433 | |||
| 1434 | |||
| 1435 | #elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ |
||
| 1436 | /* TASKING carm specific functions */
|
||
| 1437 | |||
| 1438 | /*
|
||
| 1439 | * The CMSIS functions have been implemented as intrinsics in the compiler.
|
||
| 1440 | * Please use "carm -?i" to get an up to date list of all instrinsics,
|
||
| 1441 | * Including the CMSIS ones.
|
||
| 1442 | */
|
||
| 1443 | |||
| 1444 | #endif
|
||
| 1445 | |||
| 1446 | |||
| 1447 | /** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface
|
||
| 1448 | Core Function Interface containing:
|
||
| 1449 | - Core NVIC Functions
|
||
| 1450 | - Core SysTick Functions
|
||
| 1451 | - Core Reset Functions
|
||
| 1452 | */
|
||
| 1453 | /*@{*/
|
||
| 1454 | |||
| 1455 | /* ########################## NVIC functions #################################### */
|
||
| 1456 | |||
| 1457 | /**
|
||
| 1458 | * @brief Set the Priority Grouping in NVIC Interrupt Controller
|
||
| 1459 | *
|
||
| 1460 | * @param PriorityGroup is priority grouping field
|
||
| 1461 | *
|
||
| 1462 | * Set the priority grouping field using the required unlock sequence.
|
||
| 1463 | * The parameter priority_grouping is assigned to the field
|
||
| 1464 | * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.
|
||
| 1465 | * In case of a conflict between priority grouping and available
|
||
| 1466 | * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
|
||
| 1467 | */
|
||
| 1468 | static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) |
||
| 1469 | {
|
||
| 1470 | uint32_t reg_value; |
||
| 1471 | uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ |
||
| 1472 | |||
| 1473 | reg_value = SCB->AIRCR; /* read old register configuration */
|
||
| 1474 | reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
|
||
| 1475 | reg_value = (reg_value | |
||
| 1476 | (0x5FA << SCB_AIRCR_VECTKEY_Pos) |
|
||
| 1477 | (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ |
||
| 1478 | SCB->AIRCR = reg_value; |
||
| 1479 | } |
||
| 1480 | |||
| 1481 | /**
|
||
| 1482 | * @brief Get the Priority Grouping from NVIC Interrupt Controller
|
||
| 1483 | *
|
||
| 1484 | * @return priority grouping field
|
||
| 1485 | *
|
||
| 1486 | * Get the priority grouping from NVIC Interrupt Controller.
|
||
| 1487 | * priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
|
||
| 1488 | */
|
||
| 1489 | static __INLINE uint32_t NVIC_GetPriorityGrouping(void) |
||
| 1490 | {
|
||
| 1491 | return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ |
||
| 1492 | } |
||
| 1493 | |||
| 1494 | /**
|
||
| 1495 | * @brief Enable Interrupt in NVIC Interrupt Controller
|
||
| 1496 | *
|
||
| 1497 | * @param IRQn The positive number of the external interrupt to enable
|
||
| 1498 | *
|
||
| 1499 | * Enable a device specific interupt in the NVIC interrupt controller.
|
||
| 1500 | * The interrupt number cannot be a negative value.
|
||
| 1501 | */
|
||
| 1502 | static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) |
||
| 1503 | {
|
||
| 1504 | NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ |
||
| 1505 | } |
||
| 1506 | |||
| 1507 | /**
|
||
| 1508 | * @brief Disable the interrupt line for external interrupt specified
|
||
| 1509 | *
|
||
| 1510 | * @param IRQn The positive number of the external interrupt to disable
|
||
| 1511 | *
|
||
| 1512 | * Disable a device specific interupt in the NVIC interrupt controller.
|
||
| 1513 | * The interrupt number cannot be a negative value.
|
||
| 1514 | */
|
||
| 1515 | static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) |
||
| 1516 | {
|
||
| 1517 | NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ |
||
| 1518 | } |
||
| 1519 | |||
| 1520 | /**
|
||
| 1521 | * @brief Read the interrupt pending bit for a device specific interrupt source
|
||
| 1522 | *
|
||
| 1523 | * @param IRQn The number of the device specifc interrupt
|
||
| 1524 | * @return 1 = interrupt pending, 0 = interrupt not pending
|
||
| 1525 | *
|
||
| 1526 | * Read the pending register in NVIC and return 1 if its status is pending,
|
||
| 1527 | * otherwise it returns 0
|
||
| 1528 | */
|
||
| 1529 | static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||
| 1530 | {
|
||
| 1531 | return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ |
||
| 1532 | } |
||
| 1533 | |||
| 1534 | /**
|
||
| 1535 | * @brief Set the pending bit for an external interrupt
|
||
| 1536 | *
|
||
| 1537 | * @param IRQn The number of the interrupt for set pending
|
||
| 1538 | *
|
||
| 1539 | * Set the pending bit for the specified interrupt.
|
||
| 1540 | * The interrupt number cannot be a negative value.
|
||
| 1541 | */
|
||
| 1542 | static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) |
||
| 1543 | {
|
||
| 1544 | NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ |
||
| 1545 | } |
||
| 1546 | |||
| 1547 | /**
|
||
| 1548 | * @brief Clear the pending bit for an external interrupt
|
||
| 1549 | *
|
||
| 1550 | * @param IRQn The number of the interrupt for clear pending
|
||
| 1551 | *
|
||
| 1552 | * Clear the pending bit for the specified interrupt.
|
||
| 1553 | * The interrupt number cannot be a negative value.
|
||
| 1554 | */
|
||
| 1555 | static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) |
||
| 1556 | {
|
||
| 1557 | NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ |
||
| 1558 | } |
||
| 1559 | |||
| 1560 | /**
|
||
| 1561 | * @brief Read the active bit for an external interrupt
|
||
| 1562 | *
|
||
| 1563 | * @param IRQn The number of the interrupt for read active bit
|
||
| 1564 | * @return 1 = interrupt active, 0 = interrupt not active
|
||
| 1565 | *
|
||
| 1566 | * Read the active register in NVIC and returns 1 if its status is active,
|
||
| 1567 | * otherwise it returns 0.
|
||
| 1568 | */
|
||
| 1569 | static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
|
||
| 1570 | {
|
||
| 1571 | return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ |
||
| 1572 | } |
||
| 1573 | |||
| 1574 | /**
|
||
| 1575 | * @brief Set the priority for an interrupt
|
||
| 1576 | *
|
||
| 1577 | * @param IRQn The number of the interrupt for set priority
|
||
| 1578 | * @param priority The priority to set
|
||
| 1579 | *
|
||
| 1580 | * Set the priority for the specified interrupt. The interrupt
|
||
| 1581 | * number can be positive to specify an external (device specific)
|
||
| 1582 | * interrupt, or negative to specify an internal (core) interrupt.
|
||
| 1583 | *
|
||
| 1584 | * Note: The priority cannot be set for every core interrupt.
|
||
| 1585 | */
|
||
| 1586 | static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) |
||
| 1587 | {
|
||
| 1588 | if(IRQn < 0) { |
||
| 1589 | SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */ |
||
| 1590 | else {
|
||
| 1591 | NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ |
||
| 1592 | } |
||
| 1593 | |||
| 1594 | /**
|
||
| 1595 | * @brief Read the priority for an interrupt
|
||
| 1596 | *
|
||
| 1597 | * @param IRQn The number of the interrupt for get priority
|
||
| 1598 | * @return The priority for the interrupt
|
||
| 1599 | *
|
||
| 1600 | * Read the priority for the specified interrupt. The interrupt
|
||
| 1601 | * number can be positive to specify an external (device specific)
|
||
| 1602 | * interrupt, or negative to specify an internal (core) interrupt.
|
||
| 1603 | *
|
||
| 1604 | * The returned priority value is automatically aligned to the implemented
|
||
| 1605 | * priority bits of the microcontroller.
|
||
| 1606 | *
|
||
| 1607 | * Note: The priority cannot be set for every core interrupt.
|
||
| 1608 | */
|
||
| 1609 | static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
|
||
| 1610 | {
|
||
| 1611 | |||
| 1612 | if(IRQn < 0) { |
||
| 1613 | return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */ |
||
| 1614 | else {
|
||
| 1615 | return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ |
||
| 1616 | } |
||
| 1617 | |||
| 1618 | |||
| 1619 | /**
|
||
| 1620 | * @brief Encode the priority for an interrupt
|
||
| 1621 | *
|
||
| 1622 | * @param PriorityGroup The used priority group
|
||
| 1623 | * @param PreemptPriority The preemptive priority value (starting from 0)
|
||
| 1624 | * @param SubPriority The sub priority value (starting from 0)
|
||
| 1625 | * @return The encoded priority for the interrupt
|
||
| 1626 | *
|
||
| 1627 | * Encode the priority for an interrupt with the given priority group,
|
||
| 1628 | * preemptive priority value and sub priority value.
|
||
| 1629 | * In case of a conflict between priority grouping and available
|
||
| 1630 | * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
|
||
| 1631 | *
|
||
| 1632 | * The returned priority value can be used for NVIC_SetPriority(...) function
|
||
| 1633 | */
|
||
| 1634 | static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
||
| 1635 | {
|
||
| 1636 | uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ |
||
| 1637 | uint32_t PreemptPriorityBits; |
||
| 1638 | uint32_t SubPriorityBits; |
||
| 1639 | |||
| 1640 | PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; |
||
| 1641 | SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; |
||
| 1642 | |||
| 1643 | return (
|
||
| 1644 | ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | |
||
| 1645 | ((SubPriority & ((1 << (SubPriorityBits )) - 1))) |
||
| 1646 | ); |
||
| 1647 | } |
||
| 1648 | |||
| 1649 | |||
| 1650 | /**
|
||
| 1651 | * @brief Decode the priority of an interrupt
|
||
| 1652 | *
|
||
| 1653 | * @param Priority The priority for the interrupt
|
||
| 1654 | * @param PriorityGroup The used priority group
|
||
| 1655 | * @param pPreemptPriority The preemptive priority value (starting from 0)
|
||
| 1656 | * @param pSubPriority The sub priority value (starting from 0)
|
||
| 1657 | *
|
||
| 1658 | * Decode an interrupt priority value with the given priority group to
|
||
| 1659 | * preemptive priority value and sub priority value.
|
||
| 1660 | * In case of a conflict between priority grouping and available
|
||
| 1661 | * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
|
||
| 1662 | *
|
||
| 1663 | * The priority value can be retrieved with NVIC_GetPriority(...) function
|
||
| 1664 | */
|
||
| 1665 | static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) |
||
| 1666 | {
|
||
| 1667 | uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ |
||
| 1668 | uint32_t PreemptPriorityBits; |
||
| 1669 | uint32_t SubPriorityBits; |
||
| 1670 | |||
| 1671 | PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; |
||
| 1672 | SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; |
||
| 1673 | |||
| 1674 | *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); |
||
| 1675 | *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); |
||
| 1676 | } |
||
| 1677 | |||
| 1678 | |||
| 1679 | |||
| 1680 | /* ################################## SysTick function ############################################ */
|
||
| 1681 | |||
| 1682 | #if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0) |
||
| 1683 | |||
| 1684 | /**
|
||
| 1685 | * @brief Initialize and start the SysTick counter and its interrupt.
|
||
| 1686 | *
|
||
| 1687 | * @param ticks number of ticks between two interrupts
|
||
| 1688 | * @return 1 = failed, 0 = successful
|
||
| 1689 | *
|
||
| 1690 | * Initialise the system tick timer and its interrupt and start the
|
||
| 1691 | * system tick timer / counter in free running mode to generate
|
||
| 1692 | * periodical interrupts.
|
||
| 1693 | */
|
||
| 1694 | static __INLINE uint32_t SysTick_Config(uint32_t ticks)
|
||
| 1695 | {
|
||
| 1696 | if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ |
||
| 1697 | |||
| 1698 | SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ |
||
| 1699 | NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ |
||
| 1700 | SysTick->VAL = 0; /* Load the SysTick Counter Value */ |
||
| 1701 | SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | |
||
| 1702 | SysTick_CTRL_TICKINT_Msk | |
||
| 1703 | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
||
| 1704 | return (0); /* Function successful */ |
||
| 1705 | } |
||
| 1706 | |||
| 1707 | #endif
|
||
| 1708 | |||
| 1709 | |||
| 1710 | |||
| 1711 | |||
| 1712 | /* ################################## Reset function ############################################ */
|
||
| 1713 | |||
| 1714 | /**
|
||
| 1715 | * @brief Initiate a system reset request.
|
||
| 1716 | *
|
||
| 1717 | * Initiate a system reset request to reset the MCU
|
||
| 1718 | */
|
||
| 1719 | static __INLINE void NVIC_SystemReset(void) |
||
| 1720 | {
|
||
| 1721 | SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
|
||
| 1722 | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | |
||
| 1723 | SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
|
||
| 1724 | __DSB(); /* Ensure completion of memory access */
|
||
| 1725 | while(1); /* wait until reset */ |
||
| 1726 | } |
||
| 1727 | |||
| 1728 | /*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */ |
||
| 1729 | |||
| 1730 | |||
| 1731 | |||
| 1732 | /* ##################################### Debug In/Output function ########################################### */
|
||
| 1733 | |||
| 1734 | /** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface
|
||
| 1735 | Core Debug Interface containing:
|
||
| 1736 | - Core Debug Receive / Transmit Functions
|
||
| 1737 | - Core Debug Defines
|
||
| 1738 | - Core Debug Variables
|
||
| 1739 | */
|
||
| 1740 | /*@{*/
|
||
| 1741 | |||
| 1742 | extern volatile int ITM_RxBuffer; /*!< variable to receive characters */ |
||
| 1743 | #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ |
||
| 1744 | |||
| 1745 | |||
| 1746 | /**
|
||
| 1747 | * @brief Outputs a character via the ITM channel 0
|
||
| 1748 | *
|
||
| 1749 | * @param ch character to output
|
||
| 1750 | * @return character to output
|
||
| 1751 | *
|
||
| 1752 | * The function outputs a character via the ITM channel 0.
|
||
| 1753 | * The function returns when no debugger is connected that has booked the output.
|
||
| 1754 | * It is blocking when a debugger is connected, but the previous character send is not transmitted.
|
||
| 1755 | */
|
||
| 1756 | static __INLINE uint32_t ITM_SendChar (uint32_t ch)
|
||
| 1757 | {
|
||
| 1758 | if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ |
||
| 1759 | (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
|
||
| 1760 | (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */ |
||
| 1761 | {
|
||
| 1762 | while (ITM->PORT[0].u32 == 0); |
||
| 1763 | ITM->PORT[0].u8 = (uint8_t) ch;
|
||
| 1764 | } |
||
| 1765 | return (ch);
|
||
| 1766 | } |
||
| 1767 | |||
| 1768 | |||
| 1769 | /**
|
||
| 1770 | * @brief Inputs a character via variable ITM_RxBuffer
|
||
| 1771 | *
|
||
| 1772 | * @return received character, -1 = no character received
|
||
| 1773 | *
|
||
| 1774 | * The function inputs a character via variable ITM_RxBuffer.
|
||
| 1775 | * The function returns when no debugger is connected that has booked the output.
|
||
| 1776 | * It is blocking when a debugger is connected, but the previous character send is not transmitted.
|
||
| 1777 | */
|
||
| 1778 | static __INLINE int ITM_ReceiveChar (void) { |
||
| 1779 | int ch = -1; /* no character available */ |
||
| 1780 | |||
| 1781 | if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
|
||
| 1782 | ch = ITM_RxBuffer; |
||
| 1783 | ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
|
||
| 1784 | } |
||
| 1785 | |||
| 1786 | return (ch);
|
||
| 1787 | } |
||
| 1788 | |||
| 1789 | |||
| 1790 | /**
|
||
| 1791 | * @brief Check if a character via variable ITM_RxBuffer is available
|
||
| 1792 | *
|
||
| 1793 | * @return 1 = character available, 0 = no character available
|
||
| 1794 | *
|
||
| 1795 | * The function checks variable ITM_RxBuffer whether a character is available or not.
|
||
| 1796 | * The function returns '1' if a character is available and '0' if no character is available.
|
||
| 1797 | */
|
||
| 1798 | static __INLINE int ITM_CheckChar (void) { |
||
| 1799 | |||
| 1800 | if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
|
||
| 1801 | return (0); /* no character available */ |
||
| 1802 | } else {
|
||
| 1803 | return (1); /* character available */ |
||
| 1804 | } |
||
| 1805 | } |
||
| 1806 | |||
| 1807 | /*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */ |
||
| 1808 | |||
| 1809 | |||
| 1810 | #ifdef __cplusplus
|
||
| 1811 | } |
||
| 1812 | #endif
|
||
| 1813 | |||
| 1814 | /*@}*/ /* end of group CMSIS_CM3_core_definitions */ |
||
| 1815 | |||
| 1816 | #endif /* __CM3_CORE_H__ */ |
||
| 1817 | |||
| 1818 | /*lint -restore */
|