amiro-blt / Target / Modules / LightRing_1-0 / Boot / lib / CMSIS / CM3 / DeviceSupport / ST / STM32F10x / startup / TrueSTUDIO / startup_stm32f10x_hd_vl.s @ 367c0652
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1 | 69661903 | Thomas Schöpping | /** |
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2 | ****************************************************************************** |
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3 | * @file startup_stm32f10x_hd_vl.s |
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4 | * @author MCD Application Team |
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5 | * @version V3.5.0 |
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6 | * @date 11-March-2011 |
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7 | * @brief STM32F10x High Density Value Line Devices vector table for Atollic |
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8 | * toolchain. |
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9 | * This module performs: |
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10 | * - Set the initial SP |
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11 | * - Set the initial PC == Reset_Handler, |
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12 | * - Set the vector table entries with the exceptions ISR address |
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13 | * - Configure the clock system |
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14 | * - Configure external SRAM mounted on STM32100E-EVAL board |
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15 | * to be used as data memory (optional, to be enabled by user) |
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16 | * - Branches to main in the C library (which eventually |
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17 | * calls main()). |
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18 | * After Reset the Cortex-M3 processor is in Thread mode, |
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19 | * priority is Privileged, and the Stack is set to Main. |
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20 | ****************************************************************************** |
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21 | * @attention |
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22 | * |
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23 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
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24 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE |
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25 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY |
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26 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING |
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27 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE |
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28 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
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29 | * |
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30 | * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> |
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31 | ****************************************************************************** |
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32 | */ |
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33 | |||
34 | .syntax unified |
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35 | .cpu cortex-m3 |
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36 | .fpu softvfp |
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37 | .thumb |
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38 | |||
39 | .global g_pfnVectors |
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40 | .global Default_Handler |
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41 | |||
42 | /* start address for the initialization values of the .data section. |
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43 | defined in linker script */ |
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44 | .word _sidata |
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45 | /* start address for the .data section. defined in linker script */ |
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46 | .word _sdata |
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47 | /* end address for the .data section. defined in linker script */ |
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48 | .word _edata |
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49 | /* start address for the .bss section. defined in linker script */ |
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50 | .word _sbss |
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51 | /* end address for the .bss section. defined in linker script */ |
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52 | .word _ebss |
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53 | |||
54 | .equ BootRAM, 0xF108F85F |
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55 | /** |
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56 | * @brief This is the code that gets called when the processor first |
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57 | * starts execution following a reset event. Only the absolutely |
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58 | * necessary set is performed, after which the application |
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59 | * supplied main() routine is called. |
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60 | * @param None |
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61 | * @retval : None |
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62 | */ |
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63 | |||
64 | .section .text.Reset_Handler |
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65 | .weak Reset_Handler |
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66 | .type Reset_Handler, %function |
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67 | Reset_Handler: |
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68 | |||
69 | /* Copy the data segment initializers from flash to SRAM */ |
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70 | movs r1, #0 |
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71 | b LoopCopyDataInit |
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72 | |||
73 | CopyDataInit: |
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74 | ldr r3, =_sidata |
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75 | ldr r3, [r3, r1] |
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76 | str r3, [r0, r1] |
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77 | adds r1, r1, #4 |
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78 | |||
79 | LoopCopyDataInit: |
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80 | ldr r0, =_sdata |
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81 | ldr r3, =_edata |
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82 | adds r2, r0, r1 |
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83 | cmp r2, r3 |
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84 | bcc CopyDataInit |
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85 | ldr r2, =_sbss |
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86 | b LoopFillZerobss |
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87 | /* Zero fill the bss segment. */ |
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88 | FillZerobss: |
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89 | movs r3, #0 |
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90 | str r3, [r2], #4 |
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91 | |||
92 | LoopFillZerobss: |
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93 | ldr r3, = _ebss |
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94 | cmp r2, r3 |
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95 | bcc FillZerobss |
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96 | |||
97 | /* Call the clock system intitialization function.*/ |
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98 | bl SystemInit |
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99 | /* Call static constructors */ |
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100 | bl __libc_init_array |
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101 | /* Call the application's entry point.*/ |
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102 | bl main |
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103 | bx lr |
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104 | .size Reset_Handler, .-Reset_Handler |
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105 | |||
106 | /** |
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107 | * @brief This is the code that gets called when the processor receives an |
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108 | * unexpected interrupt. This simply enters an infinite loop, preserving |
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109 | * the system state for examination by a debugger. |
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110 | * |
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111 | * @param None |
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112 | * @retval : None |
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113 | */ |
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114 | .section .text.Default_Handler,"ax",%progbits |
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115 | Default_Handler: |
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116 | Infinite_Loop: |
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117 | b Infinite_Loop |
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118 | .size Default_Handler, .-Default_Handler |
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119 | /****************************************************************************** |
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120 | * |
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121 | * The minimal vector table for a Cortex M3. Note that the proper constructs |
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122 | * must be placed on this to ensure that it ends up at physical address |
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123 | * 0x0000.0000. |
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124 | * |
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125 | ******************************************************************************/ |
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126 | .section .isr_vector,"a",%progbits |
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127 | .type g_pfnVectors, %object |
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128 | .size g_pfnVectors, .-g_pfnVectors |
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129 | |||
130 | |||
131 | g_pfnVectors: |
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132 | .word _estack |
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133 | .word Reset_Handler |
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134 | .word NMI_Handler |
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135 | .word HardFault_Handler |
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136 | .word MemManage_Handler |
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137 | .word BusFault_Handler |
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138 | .word UsageFault_Handler |
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139 | .word 0 |
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140 | .word 0 |
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141 | .word 0 |
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142 | .word 0 |
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143 | .word SVC_Handler |
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144 | .word DebugMon_Handler |
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145 | .word 0 |
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146 | .word PendSV_Handler |
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147 | .word SysTick_Handler |
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148 | .word WWDG_IRQHandler |
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149 | .word PVD_IRQHandler |
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150 | .word TAMPER_IRQHandler |
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151 | .word RTC_IRQHandler |
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152 | .word FLASH_IRQHandler |
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153 | .word RCC_IRQHandler |
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154 | .word EXTI0_IRQHandler |
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155 | .word EXTI1_IRQHandler |
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156 | .word EXTI2_IRQHandler |
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157 | .word EXTI3_IRQHandler |
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158 | .word EXTI4_IRQHandler |
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159 | .word DMA1_Channel1_IRQHandler |
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160 | .word DMA1_Channel2_IRQHandler |
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161 | .word DMA1_Channel3_IRQHandler |
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162 | .word DMA1_Channel4_IRQHandler |
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163 | .word DMA1_Channel5_IRQHandler |
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164 | .word DMA1_Channel6_IRQHandler |
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165 | .word DMA1_Channel7_IRQHandler |
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166 | .word ADC1_IRQHandler |
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167 | .word 0 |
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168 | .word 0 |
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169 | .word 0 |
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170 | .word 0 |
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171 | .word EXTI9_5_IRQHandler |
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172 | .word TIM1_BRK_TIM15_IRQHandler |
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173 | .word TIM1_UP_TIM16_IRQHandler |
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174 | .word TIM1_TRG_COM_TIM17_IRQHandler |
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175 | .word TIM1_CC_IRQHandler |
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176 | .word TIM2_IRQHandler |
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177 | .word TIM3_IRQHandler |
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178 | .word TIM4_IRQHandler |
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179 | .word I2C1_EV_IRQHandler |
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180 | .word I2C1_ER_IRQHandler |
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181 | .word I2C2_EV_IRQHandler |
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182 | .word I2C2_ER_IRQHandler |
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183 | .word SPI1_IRQHandler |
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184 | .word SPI2_IRQHandler |
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185 | .word USART1_IRQHandler |
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186 | .word USART2_IRQHandler |
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187 | .word USART3_IRQHandler |
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188 | .word EXTI15_10_IRQHandler |
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189 | .word RTCAlarm_IRQHandler |
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190 | .word CEC_IRQHandler |
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191 | .word TIM12_IRQHandler |
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192 | .word TIM13_IRQHandler |
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193 | .word TIM14_IRQHandler |
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194 | .word 0 |
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195 | .word 0 |
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196 | .word 0 |
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197 | .word 0 |
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198 | .word TIM5_IRQHandler |
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199 | .word SPI3_IRQHandler |
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200 | .word UART4_IRQHandler |
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201 | .word UART5_IRQHandler |
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202 | .word TIM6_DAC_IRQHandler |
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203 | .word TIM7_IRQHandler |
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204 | .word DMA2_Channel1_IRQHandler |
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205 | .word DMA2_Channel2_IRQHandler |
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206 | .word DMA2_Channel3_IRQHandler |
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207 | .word DMA2_Channel4_5_IRQHandler |
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208 | .word DMA2_Channel5_IRQHandler |
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209 | .word 0 |
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210 | .word 0 |
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211 | .word 0 |
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212 | .word 0 |
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213 | .word 0 |
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214 | .word 0 |
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215 | .word 0 |
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216 | .word 0 |
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217 | .word 0 |
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218 | .word 0 |
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219 | .word 0 |
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220 | .word 0 |
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221 | .word 0 |
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222 | .word 0 |
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223 | .word 0 |
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224 | .word 0 |
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225 | .word 0 |
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226 | .word 0 |
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227 | .word 0 |
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228 | .word 0 |
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229 | .word 0 |
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230 | .word 0 |
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231 | .word 0 |
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232 | .word 0 |
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233 | .word 0 |
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234 | .word 0 |
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235 | .word 0 |
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236 | .word 0 |
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237 | .word 0 |
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238 | .word 0 |
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239 | .word 0 |
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240 | .word 0 |
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241 | .word 0 |
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242 | .word 0 |
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243 | .word 0 |
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244 | .word 0 |
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245 | .word 0 |
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246 | .word 0 |
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247 | .word 0 |
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248 | .word 0 |
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249 | .word 0 |
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250 | .word 0 |
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251 | .word 0 |
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252 | .word BootRAM /* @0x1E0. This is for boot in RAM mode for |
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253 | STM32F10x High Density Value line devices. */ |
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254 | |||
255 | /******************************************************************************* |
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256 | * |
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257 | * Provide weak aliases for each Exception handler to the Default_Handler. |
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258 | * As they are weak aliases, any function with the same name will override |
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259 | * this definition. |
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260 | * |
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261 | *******************************************************************************/ |
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262 | |||
263 | |||
264 | .weak NMI_Handler |
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265 | .thumb_set NMI_Handler,Default_Handler |
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266 | |||
267 | .weak HardFault_Handler |
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268 | .thumb_set HardFault_Handler,Default_Handler |
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269 | |||
270 | .weak MemManage_Handler |
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271 | .thumb_set MemManage_Handler,Default_Handler |
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272 | |||
273 | .weak BusFault_Handler |
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274 | .thumb_set BusFault_Handler,Default_Handler |
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275 | |||
276 | .weak UsageFault_Handler |
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277 | .thumb_set UsageFault_Handler,Default_Handler |
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278 | |||
279 | .weak SVC_Handler |
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280 | .thumb_set SVC_Handler,Default_Handler |
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281 | |||
282 | .weak DebugMon_Handler |
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283 | .thumb_set DebugMon_Handler,Default_Handler |
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284 | |||
285 | .weak PendSV_Handler |
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286 | .thumb_set PendSV_Handler,Default_Handler |
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287 | |||
288 | .weak SysTick_Handler |
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289 | .thumb_set SysTick_Handler,Default_Handler |
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290 | |||
291 | .weak WWDG_IRQHandler |
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292 | .thumb_set WWDG_IRQHandler,Default_Handler |
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293 | |||
294 | .weak PVD_IRQHandler |
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295 | .thumb_set PVD_IRQHandler,Default_Handler |
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296 | |||
297 | .weak TAMPER_IRQHandler |
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298 | .thumb_set TAMPER_IRQHandler,Default_Handler |
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299 | |||
300 | .weak RTC_IRQHandler |
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301 | .thumb_set RTC_IRQHandler,Default_Handler |
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302 | |||
303 | .weak FLASH_IRQHandler |
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304 | .thumb_set FLASH_IRQHandler,Default_Handler |
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305 | |||
306 | .weak RCC_IRQHandler |
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307 | .thumb_set RCC_IRQHandler,Default_Handler |
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308 | |||
309 | .weak EXTI0_IRQHandler |
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310 | .thumb_set EXTI0_IRQHandler,Default_Handler |
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311 | |||
312 | .weak EXTI1_IRQHandler |
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313 | .thumb_set EXTI1_IRQHandler,Default_Handler |
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314 | |||
315 | .weak EXTI2_IRQHandler |
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316 | .thumb_set EXTI2_IRQHandler,Default_Handler |
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317 | |||
318 | .weak EXTI3_IRQHandler |
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319 | .thumb_set EXTI3_IRQHandler,Default_Handler |
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320 | |||
321 | .weak EXTI4_IRQHandler |
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322 | .thumb_set EXTI4_IRQHandler,Default_Handler |
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323 | |||
324 | .weak DMA1_Channel1_IRQHandler |
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325 | .thumb_set DMA1_Channel1_IRQHandler,Default_Handler |
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326 | |||
327 | .weak DMA1_Channel2_IRQHandler |
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328 | .thumb_set DMA1_Channel2_IRQHandler,Default_Handler |
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329 | |||
330 | .weak DMA1_Channel3_IRQHandler |
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331 | .thumb_set DMA1_Channel3_IRQHandler,Default_Handler |
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332 | |||
333 | .weak DMA1_Channel4_IRQHandler |
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334 | .thumb_set DMA1_Channel4_IRQHandler,Default_Handler |
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335 | |||
336 | .weak DMA1_Channel5_IRQHandler |
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337 | .thumb_set DMA1_Channel5_IRQHandler,Default_Handler |
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338 | |||
339 | .weak DMA1_Channel6_IRQHandler |
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340 | .thumb_set DMA1_Channel6_IRQHandler,Default_Handler |
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341 | |||
342 | .weak DMA1_Channel7_IRQHandler |
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343 | .thumb_set DMA1_Channel7_IRQHandler,Default_Handler |
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344 | |||
345 | .weak ADC1_IRQHandler |
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346 | .thumb_set ADC1_IRQHandler,Default_Handler |
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347 | |||
348 | .weak EXTI9_5_IRQHandler |
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349 | .thumb_set EXTI9_5_IRQHandler,Default_Handler |
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350 | |||
351 | .weak TIM1_BRK_TIM15_IRQHandler |
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352 | .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler |
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353 | |||
354 | .weak TIM1_UP_TIM16_IRQHandler |
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355 | .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler |
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356 | |||
357 | .weak TIM1_TRG_COM_TIM17_IRQHandler |
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358 | .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler |
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359 | |||
360 | .weak TIM1_CC_IRQHandler |
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361 | .thumb_set TIM1_CC_IRQHandler,Default_Handler |
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362 | |||
363 | .weak TIM2_IRQHandler |
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364 | .thumb_set TIM2_IRQHandler,Default_Handler |
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365 | |||
366 | .weak TIM3_IRQHandler |
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367 | .thumb_set TIM3_IRQHandler,Default_Handler |
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368 | |||
369 | .weak TIM4_IRQHandler |
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370 | .thumb_set TIM4_IRQHandler,Default_Handler |
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371 | |||
372 | .weak I2C1_EV_IRQHandler |
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373 | .thumb_set I2C1_EV_IRQHandler,Default_Handler |
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374 | |||
375 | .weak I2C1_ER_IRQHandler |
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376 | .thumb_set I2C1_ER_IRQHandler,Default_Handler |
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377 | |||
378 | .weak I2C2_EV_IRQHandler |
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379 | .thumb_set I2C2_EV_IRQHandler,Default_Handler |
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380 | |||
381 | .weak I2C2_ER_IRQHandler |
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382 | .thumb_set I2C2_ER_IRQHandler,Default_Handler |
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383 | |||
384 | .weak SPI1_IRQHandler |
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385 | .thumb_set SPI1_IRQHandler,Default_Handler |
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386 | |||
387 | .weak SPI2_IRQHandler |
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388 | .thumb_set SPI2_IRQHandler,Default_Handler |
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389 | |||
390 | .weak USART1_IRQHandler |
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391 | .thumb_set USART1_IRQHandler,Default_Handler |
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392 | |||
393 | .weak USART2_IRQHandler |
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394 | .thumb_set USART2_IRQHandler,Default_Handler |
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395 | |||
396 | .weak USART3_IRQHandler |
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397 | .thumb_set USART3_IRQHandler,Default_Handler |
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398 | |||
399 | .weak EXTI15_10_IRQHandler |
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400 | .thumb_set EXTI15_10_IRQHandler,Default_Handler |
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401 | |||
402 | .weak RTCAlarm_IRQHandler |
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403 | .thumb_set RTCAlarm_IRQHandler,Default_Handler |
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404 | |||
405 | .weak CEC_IRQHandler |
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406 | .thumb_set CEC_IRQHandler,Default_Handler |
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407 | |||
408 | .weak TIM12_IRQHandler |
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409 | .thumb_set TIM12_IRQHandler,Default_Handler |
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410 | |||
411 | .weak TIM13_IRQHandler |
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412 | .thumb_set TIM13_IRQHandler,Default_Handler |
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413 | |||
414 | .weak TIM14_IRQHandler |
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415 | .thumb_set TIM14_IRQHandler,Default_Handler |
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416 | |||
417 | .weak TIM5_IRQHandler |
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418 | .thumb_set TIM5_IRQHandler,Default_Handler |
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419 | |||
420 | .weak SPI3_IRQHandler |
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421 | .thumb_set SPI3_IRQHandler,Default_Handler |
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422 | |||
423 | .weak UART4_IRQHandler |
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424 | .thumb_set UART4_IRQHandler,Default_Handler |
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425 | |||
426 | .weak UART5_IRQHandler |
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427 | .thumb_set UART5_IRQHandler,Default_Handler |
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428 | |||
429 | .weak TIM6_DAC_IRQHandler |
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430 | .thumb_set TIM6_DAC_IRQHandler,Default_Handler |
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431 | |||
432 | .weak TIM7_IRQHandler |
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433 | .thumb_set TIM7_IRQHandler,Default_Handler |
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434 | |||
435 | .weak DMA2_Channel1_IRQHandler |
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436 | .thumb_set DMA2_Channel1_IRQHandler,Default_Handler |
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437 | |||
438 | .weak DMA2_Channel2_IRQHandler |
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439 | .thumb_set DMA2_Channel2_IRQHandler,Default_Handler |
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440 | |||
441 | .weak DMA2_Channel3_IRQHandler |
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442 | .thumb_set DMA2_Channel3_IRQHandler,Default_Handler |
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443 | |||
444 | .weak DMA2_Channel4_5_IRQHandler |
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445 | .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler |
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446 | |||
447 | .weak DMA2_Channel5_IRQHandler |
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448 | .thumb_set DMA2_Channel5_IRQHandler,Default_Handler |
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449 | |||
450 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ |
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451 |