amiro-blt / Target / Modules / PowerManagement_1-1 / Boot / lib / stdperiphlib / STM32F4xx_StdPeriph_Driver / inc / stm32f4xx_adc.h @ 367c0652
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| 1 | 69661903 | Thomas Schöpping | /**
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| 2 | ******************************************************************************
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| 3 | * @file stm32f4xx_adc.h
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| 4 | * @author MCD Application Team
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| 5 | * @version V1.1.0
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| 6 | * @date 11-January-2013
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| 7 | * @brief This file contains all the functions prototypes for the ADC firmware
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| 8 | * library.
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| 9 | ******************************************************************************
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| 10 | * @attention
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| 11 | *
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| 12 | * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
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| 13 | *
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| 14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
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| 15 | * You may not use this file except in compliance with the License.
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| 16 | * You may obtain a copy of the License at:
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| 17 | *
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| 18 | * http://www.st.com/software_license_agreement_liberty_v2
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| 19 | *
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| 20 | * Unless required by applicable law or agreed to in writing, software
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| 21 | * distributed under the License is distributed on an "AS IS" BASIS,
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| 22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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| 23 | * See the License for the specific language governing permissions and
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| 24 | * limitations under the License.
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| 25 | *
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| 26 | ******************************************************************************
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| 27 | */
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| 28 | |||
| 29 | /* Define to prevent recursive inclusion -------------------------------------*/
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| 30 | #ifndef __STM32F4xx_ADC_H
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| 31 | #define __STM32F4xx_ADC_H
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| 32 | |||
| 33 | #ifdef __cplusplus
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| 34 | extern "C" { |
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| 35 | #endif
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| 36 | |||
| 37 | /* Includes ------------------------------------------------------------------*/
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| 38 | #include "stm32f4xx.h" |
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| 39 | |||
| 40 | /** @addtogroup STM32F4xx_StdPeriph_Driver
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| 41 | * @{
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| 42 | */
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| 43 | |||
| 44 | /** @addtogroup ADC
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| 45 | * @{
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| 46 | */
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| 47 | |||
| 48 | /* Exported types ------------------------------------------------------------*/
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| 49 | |||
| 50 | /**
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| 51 | * @brief ADC Init structure definition
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| 52 | */
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| 53 | typedef struct |
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| 54 | {
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| 55 | uint32_t ADC_Resolution; /*!< Configures the ADC resolution dual mode.
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| 56 | This parameter can be a value of @ref ADC_resolution */
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| 57 | FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion
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| 58 | is performed in Scan (multichannels)
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| 59 | or Single (one channel) mode.
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| 60 | This parameter can be set to ENABLE or DISABLE */
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| 61 | FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion
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| 62 | is performed in Continuous or Single mode.
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| 63 | This parameter can be set to ENABLE or DISABLE. */
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| 64 | uint32_t ADC_ExternalTrigConvEdge; /*!< Select the external trigger edge and
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| 65 | enable the trigger of a regular group.
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| 66 | This parameter can be a value of
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| 67 | @ref ADC_external_trigger_edge_for_regular_channels_conversion */
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| 68 | uint32_t ADC_ExternalTrigConv; /*!< Select the external event used to trigger
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| 69 | the start of conversion of a regular group.
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| 70 | This parameter can be a value of
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| 71 | @ref ADC_extrenal_trigger_sources_for_regular_channels_conversion */
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| 72 | uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment
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| 73 | is left or right. This parameter can be
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| 74 | a value of @ref ADC_data_align */
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| 75 | uint8_t ADC_NbrOfConversion; /*!< Specifies the number of ADC conversions
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| 76 | that will be done using the sequencer for
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| 77 | regular channel group.
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| 78 | This parameter must range from 1 to 16. */
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| 79 | }ADC_InitTypeDef; |
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| 80 | |||
| 81 | /**
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| 82 | * @brief ADC Common Init structure definition
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| 83 | */
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| 84 | typedef struct |
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| 85 | {
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| 86 | uint32_t ADC_Mode; /*!< Configures the ADC to operate in
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| 87 | independent or multi mode.
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| 88 | This parameter can be a value of @ref ADC_Common_mode */
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| 89 | uint32_t ADC_Prescaler; /*!< Select the frequency of the clock
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| 90 | to the ADC. The clock is common for all the ADCs.
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| 91 | This parameter can be a value of @ref ADC_Prescaler */
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| 92 | uint32_t ADC_DMAAccessMode; /*!< Configures the Direct memory access
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| 93 | mode for multi ADC mode.
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| 94 | This parameter can be a value of
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| 95 | @ref ADC_Direct_memory_access_mode_for_multi_mode */
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| 96 | uint32_t ADC_TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases.
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| 97 | This parameter can be a value of
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| 98 | @ref ADC_delay_between_2_sampling_phases */
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| 99 | |||
| 100 | }ADC_CommonInitTypeDef; |
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| 101 | |||
| 102 | |||
| 103 | /* Exported constants --------------------------------------------------------*/
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| 104 | |||
| 105 | /** @defgroup ADC_Exported_Constants
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| 106 | * @{
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| 107 | */
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| 108 | #define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
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| 109 | ((PERIPH) == ADC2) || \ |
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| 110 | ((PERIPH) == ADC3)) |
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| 111 | |||
| 112 | /** @defgroup ADC_Common_mode
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| 113 | * @{
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| 114 | */
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| 115 | #define ADC_Mode_Independent ((uint32_t)0x00000000) |
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| 116 | #define ADC_DualMode_RegSimult_InjecSimult ((uint32_t)0x00000001) |
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| 117 | #define ADC_DualMode_RegSimult_AlterTrig ((uint32_t)0x00000002) |
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| 118 | #define ADC_DualMode_InjecSimult ((uint32_t)0x00000005) |
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| 119 | #define ADC_DualMode_RegSimult ((uint32_t)0x00000006) |
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| 120 | #define ADC_DualMode_Interl ((uint32_t)0x00000007) |
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| 121 | #define ADC_DualMode_AlterTrig ((uint32_t)0x00000009) |
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| 122 | #define ADC_TripleMode_RegSimult_InjecSimult ((uint32_t)0x00000011) |
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| 123 | #define ADC_TripleMode_RegSimult_AlterTrig ((uint32_t)0x00000012) |
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| 124 | #define ADC_TripleMode_InjecSimult ((uint32_t)0x00000015) |
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| 125 | #define ADC_TripleMode_RegSimult ((uint32_t)0x00000016) |
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| 126 | #define ADC_TripleMode_Interl ((uint32_t)0x00000017) |
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| 127 | #define ADC_TripleMode_AlterTrig ((uint32_t)0x00000019) |
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| 128 | #define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \
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| 129 | ((MODE) == ADC_DualMode_RegSimult_InjecSimult) || \ |
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| 130 | ((MODE) == ADC_DualMode_RegSimult_AlterTrig) || \ |
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| 131 | ((MODE) == ADC_DualMode_InjecSimult) || \ |
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| 132 | ((MODE) == ADC_DualMode_RegSimult) || \ |
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| 133 | ((MODE) == ADC_DualMode_Interl) || \ |
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| 134 | ((MODE) == ADC_DualMode_AlterTrig) || \ |
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| 135 | ((MODE) == ADC_TripleMode_RegSimult_InjecSimult) || \ |
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| 136 | ((MODE) == ADC_TripleMode_RegSimult_AlterTrig) || \ |
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| 137 | ((MODE) == ADC_TripleMode_InjecSimult) || \ |
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| 138 | ((MODE) == ADC_TripleMode_RegSimult) || \ |
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| 139 | ((MODE) == ADC_TripleMode_Interl) || \ |
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| 140 | ((MODE) == ADC_TripleMode_AlterTrig)) |
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| 141 | /**
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| 142 | * @}
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| 143 | */
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| 144 | |||
| 145 | |||
| 146 | /** @defgroup ADC_Prescaler
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| 147 | * @{
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| 148 | */
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| 149 | #define ADC_Prescaler_Div2 ((uint32_t)0x00000000) |
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| 150 | #define ADC_Prescaler_Div4 ((uint32_t)0x00010000) |
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| 151 | #define ADC_Prescaler_Div6 ((uint32_t)0x00020000) |
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| 152 | #define ADC_Prescaler_Div8 ((uint32_t)0x00030000) |
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| 153 | #define IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_Div2) || \
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| 154 | ((PRESCALER) == ADC_Prescaler_Div4) || \ |
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| 155 | ((PRESCALER) == ADC_Prescaler_Div6) || \ |
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| 156 | ((PRESCALER) == ADC_Prescaler_Div8)) |
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| 157 | /**
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| 158 | * @}
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| 159 | */
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| 160 | |||
| 161 | |||
| 162 | /** @defgroup ADC_Direct_memory_access_mode_for_multi_mode
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| 163 | * @{
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| 164 | */
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| 165 | #define ADC_DMAAccessMode_Disabled ((uint32_t)0x00000000) /* DMA mode disabled */ |
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| 166 | #define ADC_DMAAccessMode_1 ((uint32_t)0x00004000) /* DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/ |
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| 167 | #define ADC_DMAAccessMode_2 ((uint32_t)0x00008000) /* DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/ |
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| 168 | #define ADC_DMAAccessMode_3 ((uint32_t)0x0000C000) /* DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */ |
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| 169 | #define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAAccessMode_Disabled) || \
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| 170 | ((MODE) == ADC_DMAAccessMode_1) || \ |
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| 171 | ((MODE) == ADC_DMAAccessMode_2) || \ |
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| 172 | ((MODE) == ADC_DMAAccessMode_3)) |
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| 173 | |||
| 174 | /**
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| 175 | * @}
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| 176 | */
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| 177 | |||
| 178 | |||
| 179 | /** @defgroup ADC_delay_between_2_sampling_phases
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| 180 | * @{
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| 181 | */
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| 182 | #define ADC_TwoSamplingDelay_5Cycles ((uint32_t)0x00000000) |
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| 183 | #define ADC_TwoSamplingDelay_6Cycles ((uint32_t)0x00000100) |
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| 184 | #define ADC_TwoSamplingDelay_7Cycles ((uint32_t)0x00000200) |
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| 185 | #define ADC_TwoSamplingDelay_8Cycles ((uint32_t)0x00000300) |
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| 186 | #define ADC_TwoSamplingDelay_9Cycles ((uint32_t)0x00000400) |
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| 187 | #define ADC_TwoSamplingDelay_10Cycles ((uint32_t)0x00000500) |
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| 188 | #define ADC_TwoSamplingDelay_11Cycles ((uint32_t)0x00000600) |
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| 189 | #define ADC_TwoSamplingDelay_12Cycles ((uint32_t)0x00000700) |
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| 190 | #define ADC_TwoSamplingDelay_13Cycles ((uint32_t)0x00000800) |
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| 191 | #define ADC_TwoSamplingDelay_14Cycles ((uint32_t)0x00000900) |
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| 192 | #define ADC_TwoSamplingDelay_15Cycles ((uint32_t)0x00000A00) |
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| 193 | #define ADC_TwoSamplingDelay_16Cycles ((uint32_t)0x00000B00) |
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| 194 | #define ADC_TwoSamplingDelay_17Cycles ((uint32_t)0x00000C00) |
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| 195 | #define ADC_TwoSamplingDelay_18Cycles ((uint32_t)0x00000D00) |
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| 196 | #define ADC_TwoSamplingDelay_19Cycles ((uint32_t)0x00000E00) |
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| 197 | #define ADC_TwoSamplingDelay_20Cycles ((uint32_t)0x00000F00) |
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| 198 | #define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TwoSamplingDelay_5Cycles) || \
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| 199 | ((DELAY) == ADC_TwoSamplingDelay_6Cycles) || \ |
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| 200 | ((DELAY) == ADC_TwoSamplingDelay_7Cycles) || \ |
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| 201 | ((DELAY) == ADC_TwoSamplingDelay_8Cycles) || \ |
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| 202 | ((DELAY) == ADC_TwoSamplingDelay_9Cycles) || \ |
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| 203 | ((DELAY) == ADC_TwoSamplingDelay_10Cycles) || \ |
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| 204 | ((DELAY) == ADC_TwoSamplingDelay_11Cycles) || \ |
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| 205 | ((DELAY) == ADC_TwoSamplingDelay_12Cycles) || \ |
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| 206 | ((DELAY) == ADC_TwoSamplingDelay_13Cycles) || \ |
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| 207 | ((DELAY) == ADC_TwoSamplingDelay_14Cycles) || \ |
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| 208 | ((DELAY) == ADC_TwoSamplingDelay_15Cycles) || \ |
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| 209 | ((DELAY) == ADC_TwoSamplingDelay_16Cycles) || \ |
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| 210 | ((DELAY) == ADC_TwoSamplingDelay_17Cycles) || \ |
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| 211 | ((DELAY) == ADC_TwoSamplingDelay_18Cycles) || \ |
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| 212 | ((DELAY) == ADC_TwoSamplingDelay_19Cycles) || \ |
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| 213 | ((DELAY) == ADC_TwoSamplingDelay_20Cycles)) |
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| 214 | |||
| 215 | /**
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| 216 | * @}
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| 217 | */
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| 218 | |||
| 219 | |||
| 220 | /** @defgroup ADC_resolution
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| 221 | * @{
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| 222 | */
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| 223 | #define ADC_Resolution_12b ((uint32_t)0x00000000) |
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| 224 | #define ADC_Resolution_10b ((uint32_t)0x01000000) |
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| 225 | #define ADC_Resolution_8b ((uint32_t)0x02000000) |
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| 226 | #define ADC_Resolution_6b ((uint32_t)0x03000000) |
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| 227 | #define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \
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| 228 | ((RESOLUTION) == ADC_Resolution_10b) || \ |
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| 229 | ((RESOLUTION) == ADC_Resolution_8b) || \ |
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| 230 | ((RESOLUTION) == ADC_Resolution_6b)) |
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| 231 | |||
| 232 | /**
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| 233 | * @}
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| 234 | */
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| 235 | |||
| 236 | |||
| 237 | /** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion
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| 238 | * @{
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| 239 | */
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| 240 | #define ADC_ExternalTrigConvEdge_None ((uint32_t)0x00000000) |
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| 241 | #define ADC_ExternalTrigConvEdge_Rising ((uint32_t)0x10000000) |
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| 242 | #define ADC_ExternalTrigConvEdge_Falling ((uint32_t)0x20000000) |
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| 243 | #define ADC_ExternalTrigConvEdge_RisingFalling ((uint32_t)0x30000000) |
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| 244 | #define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \
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| 245 | ((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \ |
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| 246 | ((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \ |
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| 247 | ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling)) |
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| 248 | /**
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| 249 | * @}
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| 250 | */
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| 251 | |||
| 252 | |||
| 253 | /** @defgroup ADC_extrenal_trigger_sources_for_regular_channels_conversion
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| 254 | * @{
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| 255 | */
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| 256 | #define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) |
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| 257 | #define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x01000000) |
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| 258 | #define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x02000000) |
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| 259 | #define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x03000000) |
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| 260 | #define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x04000000) |
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| 261 | #define ADC_ExternalTrigConv_T2_CC4 ((uint32_t)0x05000000) |
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| 262 | #define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x06000000) |
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| 263 | #define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x07000000) |
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| 264 | #define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x08000000) |
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| 265 | #define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x09000000) |
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| 266 | #define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x0A000000) |
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| 267 | #define ADC_ExternalTrigConv_T5_CC2 ((uint32_t)0x0B000000) |
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| 268 | #define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x0C000000) |
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| 269 | #define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x0D000000) |
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| 270 | #define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x0E000000) |
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| 271 | #define ADC_ExternalTrigConv_Ext_IT11 ((uint32_t)0x0F000000) |
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| 272 | #define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \
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| 273 | ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \ |
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| 274 | ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \ |
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| 275 | ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \ |
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| 276 | ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \ |
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| 277 | ((REGTRIG) == ADC_ExternalTrigConv_T2_CC4) || \ |
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| 278 | ((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) || \ |
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| 279 | ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \ |
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| 280 | ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \ |
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| 281 | ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \ |
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| 282 | ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \ |
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| 283 | ((REGTRIG) == ADC_ExternalTrigConv_T5_CC2) || \ |
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| 284 | ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3) || \ |
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| 285 | ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \ |
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| 286 | ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \ |
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| 287 | ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11)) |
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| 288 | /**
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| 289 | * @}
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| 290 | */
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| 291 | |||
| 292 | |||
| 293 | /** @defgroup ADC_data_align
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| 294 | * @{
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| 295 | */
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| 296 | #define ADC_DataAlign_Right ((uint32_t)0x00000000) |
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| 297 | #define ADC_DataAlign_Left ((uint32_t)0x00000800) |
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| 298 | #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
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| 299 | ((ALIGN) == ADC_DataAlign_Left)) |
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| 300 | /**
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| 301 | * @}
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| 302 | */
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| 303 | |||
| 304 | |||
| 305 | /** @defgroup ADC_channels
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| 306 | * @{
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| 307 | */
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| 308 | #define ADC_Channel_0 ((uint8_t)0x00) |
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| 309 | #define ADC_Channel_1 ((uint8_t)0x01) |
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| 310 | #define ADC_Channel_2 ((uint8_t)0x02) |
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| 311 | #define ADC_Channel_3 ((uint8_t)0x03) |
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| 312 | #define ADC_Channel_4 ((uint8_t)0x04) |
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| 313 | #define ADC_Channel_5 ((uint8_t)0x05) |
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| 314 | #define ADC_Channel_6 ((uint8_t)0x06) |
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| 315 | #define ADC_Channel_7 ((uint8_t)0x07) |
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| 316 | #define ADC_Channel_8 ((uint8_t)0x08) |
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| 317 | #define ADC_Channel_9 ((uint8_t)0x09) |
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| 318 | #define ADC_Channel_10 ((uint8_t)0x0A) |
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| 319 | #define ADC_Channel_11 ((uint8_t)0x0B) |
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| 320 | #define ADC_Channel_12 ((uint8_t)0x0C) |
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| 321 | #define ADC_Channel_13 ((uint8_t)0x0D) |
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| 322 | #define ADC_Channel_14 ((uint8_t)0x0E) |
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| 323 | #define ADC_Channel_15 ((uint8_t)0x0F) |
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| 324 | #define ADC_Channel_16 ((uint8_t)0x10) |
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| 325 | #define ADC_Channel_17 ((uint8_t)0x11) |
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| 326 | #define ADC_Channel_18 ((uint8_t)0x12) |
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| 327 | |||
| 328 | #define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)
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| 329 | #define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17)
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| 330 | #define ADC_Channel_Vbat ((uint8_t)ADC_Channel_18)
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| 331 | |||
| 332 | #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || \
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| 333 | ((CHANNEL) == ADC_Channel_1) || \ |
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| 334 | ((CHANNEL) == ADC_Channel_2) || \ |
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| 335 | ((CHANNEL) == ADC_Channel_3) || \ |
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| 336 | ((CHANNEL) == ADC_Channel_4) || \ |
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| 337 | ((CHANNEL) == ADC_Channel_5) || \ |
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| 338 | ((CHANNEL) == ADC_Channel_6) || \ |
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| 339 | ((CHANNEL) == ADC_Channel_7) || \ |
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| 340 | ((CHANNEL) == ADC_Channel_8) || \ |
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| 341 | ((CHANNEL) == ADC_Channel_9) || \ |
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| 342 | ((CHANNEL) == ADC_Channel_10) || \ |
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| 343 | ((CHANNEL) == ADC_Channel_11) || \ |
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| 344 | ((CHANNEL) == ADC_Channel_12) || \ |
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| 345 | ((CHANNEL) == ADC_Channel_13) || \ |
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| 346 | ((CHANNEL) == ADC_Channel_14) || \ |
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| 347 | ((CHANNEL) == ADC_Channel_15) || \ |
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| 348 | ((CHANNEL) == ADC_Channel_16) || \ |
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| 349 | ((CHANNEL) == ADC_Channel_17) || \ |
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| 350 | ((CHANNEL) == ADC_Channel_18)) |
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| 351 | /**
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| 352 | * @}
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| 353 | */
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| 354 | |||
| 355 | |||
| 356 | /** @defgroup ADC_sampling_times
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| 357 | * @{
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| 358 | */
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| 359 | #define ADC_SampleTime_3Cycles ((uint8_t)0x00) |
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| 360 | #define ADC_SampleTime_15Cycles ((uint8_t)0x01) |
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| 361 | #define ADC_SampleTime_28Cycles ((uint8_t)0x02) |
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| 362 | #define ADC_SampleTime_56Cycles ((uint8_t)0x03) |
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| 363 | #define ADC_SampleTime_84Cycles ((uint8_t)0x04) |
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| 364 | #define ADC_SampleTime_112Cycles ((uint8_t)0x05) |
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| 365 | #define ADC_SampleTime_144Cycles ((uint8_t)0x06) |
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| 366 | #define ADC_SampleTime_480Cycles ((uint8_t)0x07) |
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| 367 | #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_3Cycles) || \
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| 368 | ((TIME) == ADC_SampleTime_15Cycles) || \ |
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| 369 | ((TIME) == ADC_SampleTime_28Cycles) || \ |
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| 370 | ((TIME) == ADC_SampleTime_56Cycles) || \ |
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| 371 | ((TIME) == ADC_SampleTime_84Cycles) || \ |
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| 372 | ((TIME) == ADC_SampleTime_112Cycles) || \ |
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| 373 | ((TIME) == ADC_SampleTime_144Cycles) || \ |
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| 374 | ((TIME) == ADC_SampleTime_480Cycles)) |
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| 375 | /**
|
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| 376 | * @}
|
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| 377 | */
|
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| 378 | |||
| 379 | |||
| 380 | /** @defgroup ADC_external_trigger_edge_for_injected_channels_conversion
|
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| 381 | * @{
|
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| 382 | */
|
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| 383 | #define ADC_ExternalTrigInjecConvEdge_None ((uint32_t)0x00000000) |
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| 384 | #define ADC_ExternalTrigInjecConvEdge_Rising ((uint32_t)0x00100000) |
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| 385 | #define ADC_ExternalTrigInjecConvEdge_Falling ((uint32_t)0x00200000) |
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| 386 | #define ADC_ExternalTrigInjecConvEdge_RisingFalling ((uint32_t)0x00300000) |
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| 387 | #define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecConvEdge_None) || \
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| 388 | ((EDGE) == ADC_ExternalTrigInjecConvEdge_Rising) || \ |
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| 389 | ((EDGE) == ADC_ExternalTrigInjecConvEdge_Falling) || \ |
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| 390 | ((EDGE) == ADC_ExternalTrigInjecConvEdge_RisingFalling)) |
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| 391 | |||
| 392 | /**
|
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| 393 | * @}
|
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| 394 | */
|
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| 395 | |||
| 396 | |||
| 397 | /** @defgroup ADC_extrenal_trigger_sources_for_injected_channels_conversion
|
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| 398 | * @{
|
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| 399 | */
|
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| 400 | #define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00000000) |
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| 401 | #define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00010000) |
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| 402 | #define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00020000) |
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| 403 | #define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00030000) |
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| 404 | #define ADC_ExternalTrigInjecConv_T3_CC2 ((uint32_t)0x00040000) |
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| 405 | #define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00050000) |
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| 406 | #define ADC_ExternalTrigInjecConv_T4_CC1 ((uint32_t)0x00060000) |
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| 407 | #define ADC_ExternalTrigInjecConv_T4_CC2 ((uint32_t)0x00070000) |
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| 408 | #define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00080000) |
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| 409 | #define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00090000) |
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| 410 | #define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x000A0000) |
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| 411 | #define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x000B0000) |
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| 412 | #define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x000C0000) |
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| 413 | #define ADC_ExternalTrigInjecConv_T8_CC3 ((uint32_t)0x000D0000) |
||
| 414 | #define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x000E0000) |
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| 415 | #define ADC_ExternalTrigInjecConv_Ext_IT15 ((uint32_t)0x000F0000) |
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| 416 | #define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \
|
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| 417 | ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \ |
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| 418 | ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \ |
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| 419 | ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \ |
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| 420 | ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC2) || \ |
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| 421 | ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \ |
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| 422 | ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC1) || \ |
||
| 423 | ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC2) || \ |
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| 424 | ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \ |
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| 425 | ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \ |
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| 426 | ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4) || \ |
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| 427 | ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \ |
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| 428 | ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \ |
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| 429 | ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC3) || \ |
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| 430 | ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \ |
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| 431 | ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15)) |
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| 432 | /**
|
||
| 433 | * @}
|
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| 434 | */
|
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| 435 | |||
| 436 | |||
| 437 | /** @defgroup ADC_injected_channel_selection
|
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| 438 | * @{
|
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| 439 | */
|
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| 440 | #define ADC_InjectedChannel_1 ((uint8_t)0x14) |
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| 441 | #define ADC_InjectedChannel_2 ((uint8_t)0x18) |
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| 442 | #define ADC_InjectedChannel_3 ((uint8_t)0x1C) |
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| 443 | #define ADC_InjectedChannel_4 ((uint8_t)0x20) |
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| 444 | #define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
|
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| 445 | ((CHANNEL) == ADC_InjectedChannel_2) || \ |
||
| 446 | ((CHANNEL) == ADC_InjectedChannel_3) || \ |
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| 447 | ((CHANNEL) == ADC_InjectedChannel_4)) |
||
| 448 | /**
|
||
| 449 | * @}
|
||
| 450 | */
|
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| 451 | |||
| 452 | |||
| 453 | /** @defgroup ADC_analog_watchdog_selection
|
||
| 454 | * @{
|
||
| 455 | */
|
||
| 456 | #define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) |
||
| 457 | #define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) |
||
| 458 | #define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) |
||
| 459 | #define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) |
||
| 460 | #define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) |
||
| 461 | #define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) |
||
| 462 | #define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) |
||
| 463 | #define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
|
||
| 464 | ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \ |
||
| 465 | ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \ |
||
| 466 | ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \ |
||
| 467 | ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \ |
||
| 468 | ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \ |
||
| 469 | ((WATCHDOG) == ADC_AnalogWatchdog_None)) |
||
| 470 | /**
|
||
| 471 | * @}
|
||
| 472 | */
|
||
| 473 | |||
| 474 | |||
| 475 | /** @defgroup ADC_interrupts_definition
|
||
| 476 | * @{
|
||
| 477 | */
|
||
| 478 | #define ADC_IT_EOC ((uint16_t)0x0205) |
||
| 479 | #define ADC_IT_AWD ((uint16_t)0x0106) |
||
| 480 | #define ADC_IT_JEOC ((uint16_t)0x0407) |
||
| 481 | #define ADC_IT_OVR ((uint16_t)0x201A) |
||
| 482 | #define IS_ADC_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \
|
||
| 483 | ((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR)) |
||
| 484 | /**
|
||
| 485 | * @}
|
||
| 486 | */
|
||
| 487 | |||
| 488 | |||
| 489 | /** @defgroup ADC_flags_definition
|
||
| 490 | * @{
|
||
| 491 | */
|
||
| 492 | #define ADC_FLAG_AWD ((uint8_t)0x01) |
||
| 493 | #define ADC_FLAG_EOC ((uint8_t)0x02) |
||
| 494 | #define ADC_FLAG_JEOC ((uint8_t)0x04) |
||
| 495 | #define ADC_FLAG_JSTRT ((uint8_t)0x08) |
||
| 496 | #define ADC_FLAG_STRT ((uint8_t)0x10) |
||
| 497 | #define ADC_FLAG_OVR ((uint8_t)0x20) |
||
| 498 | |||
| 499 | #define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xC0) == 0x00) && ((FLAG) != 0x00)) |
||
| 500 | #define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || \
|
||
| 501 | ((FLAG) == ADC_FLAG_EOC) || \ |
||
| 502 | ((FLAG) == ADC_FLAG_JEOC) || \ |
||
| 503 | ((FLAG)== ADC_FLAG_JSTRT) || \ |
||
| 504 | ((FLAG) == ADC_FLAG_STRT) || \ |
||
| 505 | ((FLAG)== ADC_FLAG_OVR)) |
||
| 506 | /**
|
||
| 507 | * @}
|
||
| 508 | */
|
||
| 509 | |||
| 510 | |||
| 511 | /** @defgroup ADC_thresholds
|
||
| 512 | * @{
|
||
| 513 | */
|
||
| 514 | #define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF) |
||
| 515 | /**
|
||
| 516 | * @}
|
||
| 517 | */
|
||
| 518 | |||
| 519 | |||
| 520 | /** @defgroup ADC_injected_offset
|
||
| 521 | * @{
|
||
| 522 | */
|
||
| 523 | #define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF) |
||
| 524 | /**
|
||
| 525 | * @}
|
||
| 526 | */
|
||
| 527 | |||
| 528 | |||
| 529 | /** @defgroup ADC_injected_length
|
||
| 530 | * @{
|
||
| 531 | */
|
||
| 532 | #define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4)) |
||
| 533 | /**
|
||
| 534 | * @}
|
||
| 535 | */
|
||
| 536 | |||
| 537 | |||
| 538 | /** @defgroup ADC_injected_rank
|
||
| 539 | * @{
|
||
| 540 | */
|
||
| 541 | #define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4)) |
||
| 542 | /**
|
||
| 543 | * @}
|
||
| 544 | */
|
||
| 545 | |||
| 546 | |||
| 547 | /** @defgroup ADC_regular_length
|
||
| 548 | * @{
|
||
| 549 | */
|
||
| 550 | #define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10)) |
||
| 551 | /**
|
||
| 552 | * @}
|
||
| 553 | */
|
||
| 554 | |||
| 555 | |||
| 556 | /** @defgroup ADC_regular_rank
|
||
| 557 | * @{
|
||
| 558 | */
|
||
| 559 | #define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10)) |
||
| 560 | /**
|
||
| 561 | * @}
|
||
| 562 | */
|
||
| 563 | |||
| 564 | |||
| 565 | /** @defgroup ADC_regular_discontinuous_mode_number
|
||
| 566 | * @{
|
||
| 567 | */
|
||
| 568 | #define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8)) |
||
| 569 | /**
|
||
| 570 | * @}
|
||
| 571 | */
|
||
| 572 | |||
| 573 | |||
| 574 | /**
|
||
| 575 | * @}
|
||
| 576 | */
|
||
| 577 | |||
| 578 | /* Exported macro ------------------------------------------------------------*/
|
||
| 579 | /* Exported functions --------------------------------------------------------*/
|
||
| 580 | |||
| 581 | /* Function used to set the ADC configuration to the default reset state *****/
|
||
| 582 | void ADC_DeInit(void); |
||
| 583 | |||
| 584 | /* Initialization and Configuration functions *********************************/
|
||
| 585 | void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
|
||
| 586 | void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
|
||
| 587 | void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
|
||
| 588 | void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
|
||
| 589 | void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||
| 590 | |||
| 591 | /* Analog Watchdog configuration functions ************************************/
|
||
| 592 | void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
|
||
| 593 | void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold);
|
||
| 594 | void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
|
||
| 595 | |||
| 596 | /* Temperature Sensor, Vrefint and VBAT management functions ******************/
|
||
| 597 | void ADC_TempSensorVrefintCmd(FunctionalState NewState);
|
||
| 598 | void ADC_VBATCmd(FunctionalState NewState);
|
||
| 599 | |||
| 600 | /* Regular Channels Configuration functions ***********************************/
|
||
| 601 | void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
|
||
| 602 | void ADC_SoftwareStartConv(ADC_TypeDef* ADCx);
|
||
| 603 | FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx); |
||
| 604 | void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||
| 605 | void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||
| 606 | void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
|
||
| 607 | void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||
| 608 | uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx); |
||
| 609 | uint32_t ADC_GetMultiModeConversionValue(void);
|
||
| 610 | |||
| 611 | /* Regular Channels DMA Configuration functions *******************************/
|
||
| 612 | void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||
| 613 | void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||
| 614 | void ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState);
|
||
| 615 | |||
| 616 | /* Injected channels Configuration functions **********************************/
|
||
| 617 | void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
|
||
| 618 | void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);
|
||
| 619 | void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
|
||
| 620 | void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);
|
||
| 621 | void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge);
|
||
| 622 | void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx);
|
||
| 623 | FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx); |
||
| 624 | void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||
| 625 | void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||
| 626 | uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel); |
||
| 627 | |||
| 628 | /* Interrupts and flags management functions **********************************/
|
||
| 629 | void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);
|
||
| 630 | FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); |
||
| 631 | void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
|
||
| 632 | ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT); |
||
| 633 | void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);
|
||
| 634 | |||
| 635 | #ifdef __cplusplus
|
||
| 636 | } |
||
| 637 | #endif
|
||
| 638 | |||
| 639 | #endif /*__STM32F4xx_ADC_H */ |
||
| 640 | |||
| 641 | /**
|
||
| 642 | * @}
|
||
| 643 | */
|
||
| 644 | |||
| 645 | /**
|
||
| 646 | * @}
|
||
| 647 | */
|
||
| 648 | |||
| 649 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|