amiro-blt / Target / Modules / PowerManagement_1-1 / Boot / lib / stdperiphlib / STM32F4xx_StdPeriph_Driver / src / stm32f4xx_can.c @ 367c0652
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1 | 69661903 | Thomas Schöpping | /**
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2 | ******************************************************************************
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3 | * @file stm32f4xx_can.c
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4 | * @author MCD Application Team
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5 | * @version V1.1.0
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6 | * @date 11-January-2013
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7 | * @brief This file provides firmware functions to manage the following
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8 | * functionalities of the Controller area network (CAN) peripheral:
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9 | * + Initialization and Configuration
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10 | * + CAN Frames Transmission
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11 | * + CAN Frames Reception
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12 | * + Operation modes switch
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13 | * + Error management
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14 | * + Interrupts and flags
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15 | *
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16 | @verbatim
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17 | ===============================================================================
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18 | ##### How to use this driver #####
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19 | ===============================================================================
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20 | [..]
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21 | (#) Enable the CAN controller interface clock using
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22 | RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1, ENABLE); for CAN1
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23 | and RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN2, ENABLE); for CAN2
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24 | -@- In case you are using CAN2 only, you have to enable the CAN1 clock.
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25 |
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26 | (#) CAN pins configuration
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27 | (++) Enable the clock for the CAN GPIOs using the following function:
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28 | RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
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29 | (++) Connect the involved CAN pins to AF9 using the following function
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30 | GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_CANx);
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31 | (++) Configure these CAN pins in alternate function mode by calling
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32 | the function GPIO_Init();
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33 |
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34 | (#) Initialise and configure the CAN using CAN_Init() and
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35 | CAN_FilterInit() functions.
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36 |
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37 | (#) Transmit the desired CAN frame using CAN_Transmit() function.
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38 |
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39 | (#) Check the transmission of a CAN frame using CAN_TransmitStatus()
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40 | function.
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41 |
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42 | (#) Cancel the transmission of a CAN frame using CAN_CancelTransmit()
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43 | function.
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44 |
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45 | (#) Receive a CAN frame using CAN_Recieve() function.
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46 |
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47 | (#) Release the receive FIFOs using CAN_FIFORelease() function.
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48 |
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49 | (#) Return the number of pending received frames using
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50 | CAN_MessagePending() function.
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51 |
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52 | (#) To control CAN events you can use one of the following two methods:
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53 | (++) Check on CAN flags using the CAN_GetFlagStatus() function.
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54 | (++) Use CAN interrupts through the function CAN_ITConfig() at
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55 | initialization phase and CAN_GetITStatus() function into
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56 | interrupt routines to check if the event has occurred or not.
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57 | After checking on a flag you should clear it using CAN_ClearFlag()
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58 | function. And after checking on an interrupt event you should
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59 | clear it using CAN_ClearITPendingBit() function.
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60 |
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61 |
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62 | @endverbatim
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63 |
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64 | ******************************************************************************
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65 | * @attention
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66 | *
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67 | * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
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68 | *
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69 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
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70 | * You may not use this file except in compliance with the License.
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71 | * You may obtain a copy of the License at:
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72 | *
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73 | * http://www.st.com/software_license_agreement_liberty_v2
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74 | *
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75 | * Unless required by applicable law or agreed to in writing, software
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76 | * distributed under the License is distributed on an "AS IS" BASIS,
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77 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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78 | * See the License for the specific language governing permissions and
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79 | * limitations under the License.
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80 | *
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81 | ******************************************************************************
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82 | */
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83 | |||
84 | /* Includes ------------------------------------------------------------------*/
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85 | #include "stm32f4xx_can.h" |
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86 | #include "stm32f4xx_rcc.h" |
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87 | |||
88 | /** @addtogroup STM32F4xx_StdPeriph_Driver
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89 | * @{
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90 | */
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91 | |||
92 | /** @defgroup CAN
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93 | * @brief CAN driver modules
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94 | * @{
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95 | */
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96 | /* Private typedef -----------------------------------------------------------*/
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97 | /* Private define ------------------------------------------------------------*/
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98 | |||
99 | /* CAN Master Control Register bits */
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100 | #define MCR_DBF ((uint32_t)0x00010000) /* software master reset */ |
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101 | |||
102 | /* CAN Mailbox Transmit Request */
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103 | #define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */ |
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104 | |||
105 | /* CAN Filter Master Register bits */
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106 | #define FMR_FINIT ((uint32_t)0x00000001) /* Filter init mode */ |
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107 | |||
108 | /* Time out for INAK bit */
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109 | #define INAK_TIMEOUT ((uint32_t)0x0000FFFF) |
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110 | /* Time out for SLAK bit */
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111 | #define SLAK_TIMEOUT ((uint32_t)0x0000FFFF) |
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112 | |||
113 | /* Flags in TSR register */
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114 | #define CAN_FLAGS_TSR ((uint32_t)0x08000000) |
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115 | /* Flags in RF1R register */
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116 | #define CAN_FLAGS_RF1R ((uint32_t)0x04000000) |
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117 | /* Flags in RF0R register */
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118 | #define CAN_FLAGS_RF0R ((uint32_t)0x02000000) |
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119 | /* Flags in MSR register */
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120 | #define CAN_FLAGS_MSR ((uint32_t)0x01000000) |
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121 | /* Flags in ESR register */
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122 | #define CAN_FLAGS_ESR ((uint32_t)0x00F00000) |
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123 | |||
124 | /* Mailboxes definition */
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125 | #define CAN_TXMAILBOX_0 ((uint8_t)0x00) |
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126 | #define CAN_TXMAILBOX_1 ((uint8_t)0x01) |
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127 | #define CAN_TXMAILBOX_2 ((uint8_t)0x02) |
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128 | |||
129 | #define CAN_MODE_MASK ((uint32_t) 0x00000003) |
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130 | |||
131 | /* Private macro -------------------------------------------------------------*/
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132 | /* Private variables ---------------------------------------------------------*/
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133 | /* Private function prototypes -----------------------------------------------*/
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134 | /* Private functions ---------------------------------------------------------*/
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135 | static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit);
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136 | |||
137 | /** @defgroup CAN_Private_Functions
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138 | * @{
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139 | */
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140 | |||
141 | /** @defgroup CAN_Group1 Initialization and Configuration functions
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142 | * @brief Initialization and Configuration functions
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143 | *
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144 | @verbatim
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145 | ===============================================================================
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146 | ##### Initialization and Configuration functions #####
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147 | ===============================================================================
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148 | [..] This section provides functions allowing to
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149 | (+) Initialize the CAN peripherals : Prescaler, operating mode, the maximum
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150 | number of time quanta to perform resynchronization, the number of time
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151 | quanta in Bit Segment 1 and 2 and many other modes.
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152 | Refer to @ref CAN_InitTypeDef for more details.
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153 | (+) Configures the CAN reception filter.
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154 | (+) Select the start bank filter for slave CAN.
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155 | (+) Enables or disables the Debug Freeze mode for CAN
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156 | (+)Enables or disables the CAN Time Trigger Operation communication mode
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157 |
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158 | @endverbatim
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159 | * @{
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160 | */
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161 | |||
162 | /**
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163 | * @brief Deinitializes the CAN peripheral registers to their default reset values.
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164 | * @param CANx: where x can be 1 or 2 to select the CAN peripheral.
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165 | * @retval None.
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166 | */
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167 | void CAN_DeInit(CAN_TypeDef* CANx)
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168 | { |
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169 | /* Check the parameters */
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170 | assert_param(IS_CAN_ALL_PERIPH(CANx)); |
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171 | |||
172 | if (CANx == CAN1)
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173 | { |
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174 | /* Enable CAN1 reset state */
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175 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE); |
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176 | /* Release CAN1 from reset state */
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177 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE); |
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178 | } |
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179 | else
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180 | { |
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181 | /* Enable CAN2 reset state */
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182 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE); |
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183 | /* Release CAN2 from reset state */
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184 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE); |
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185 | } |
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186 | } |
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187 | |||
188 | /**
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189 | * @brief Initializes the CAN peripheral according to the specified
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190 | * parameters in the CAN_InitStruct.
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191 | * @param CANx: where x can be 1 or 2 to select the CAN peripheral.
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192 | * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that contains
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193 | * the configuration information for the CAN peripheral.
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194 | * @retval Constant indicates initialization succeed which will be
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195 | * CAN_InitStatus_Failed or CAN_InitStatus_Success.
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196 | */
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197 | uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct) |
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198 | { |
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199 | uint8_t InitStatus = CAN_InitStatus_Failed; |
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200 | uint32_t wait_ack = 0x00000000;
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201 | /* Check the parameters */
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202 | assert_param(IS_CAN_ALL_PERIPH(CANx)); |
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203 | assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM)); |
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204 | assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM)); |
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205 | assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM)); |
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206 | assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART)); |
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207 | assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM)); |
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208 | assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP)); |
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209 | assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode)); |
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210 | assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW)); |
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211 | assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1)); |
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212 | assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2)); |
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213 | assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler)); |
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214 | |||
215 | /* Exit from sleep mode */
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216 | CANx->MCR &= (~(uint32_t)CAN_MCR_SLEEP); |
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217 | |||
218 | /* Request initialisation */
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219 | CANx->MCR |= CAN_MCR_INRQ ; |
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220 | |||
221 | /* Wait the acknowledge */
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222 | while (((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))
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223 | { |
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224 | wait_ack++; |
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225 | } |
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226 | |||
227 | /* Check acknowledge */
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228 | if ((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
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229 | { |
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230 | InitStatus = CAN_InitStatus_Failed; |
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231 | } |
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232 | else
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233 | { |
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234 | /* Set the time triggered communication mode */
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235 | if (CAN_InitStruct->CAN_TTCM == ENABLE)
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236 | { |
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237 | CANx->MCR |= CAN_MCR_TTCM; |
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238 | } |
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239 | else
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240 | { |
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241 | CANx->MCR &= ~(uint32_t)CAN_MCR_TTCM; |
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242 | } |
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243 | |||
244 | /* Set the automatic bus-off management */
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245 | if (CAN_InitStruct->CAN_ABOM == ENABLE)
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246 | { |
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247 | CANx->MCR |= CAN_MCR_ABOM; |
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248 | } |
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249 | else
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250 | { |
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251 | CANx->MCR &= ~(uint32_t)CAN_MCR_ABOM; |
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252 | } |
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253 | |||
254 | /* Set the automatic wake-up mode */
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255 | if (CAN_InitStruct->CAN_AWUM == ENABLE)
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256 | { |
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257 | CANx->MCR |= CAN_MCR_AWUM; |
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258 | } |
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259 | else
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260 | { |
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261 | CANx->MCR &= ~(uint32_t)CAN_MCR_AWUM; |
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262 | } |
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263 | |||
264 | /* Set the no automatic retransmission */
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265 | if (CAN_InitStruct->CAN_NART == ENABLE)
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266 | { |
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267 | CANx->MCR |= CAN_MCR_NART; |
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268 | } |
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269 | else
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270 | { |
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271 | CANx->MCR &= ~(uint32_t)CAN_MCR_NART; |
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272 | } |
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273 | |||
274 | /* Set the receive FIFO locked mode */
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275 | if (CAN_InitStruct->CAN_RFLM == ENABLE)
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276 | { |
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277 | CANx->MCR |= CAN_MCR_RFLM; |
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278 | } |
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279 | else
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280 | { |
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281 | CANx->MCR &= ~(uint32_t)CAN_MCR_RFLM; |
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282 | } |
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283 | |||
284 | /* Set the transmit FIFO priority */
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285 | if (CAN_InitStruct->CAN_TXFP == ENABLE)
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286 | { |
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287 | CANx->MCR |= CAN_MCR_TXFP; |
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288 | } |
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289 | else
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290 | { |
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291 | CANx->MCR &= ~(uint32_t)CAN_MCR_TXFP; |
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292 | } |
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293 | |||
294 | /* Set the bit timing register */
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295 | CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | \
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296 | ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | \
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297 | ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | \
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298 | ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | \
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299 | ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1);
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300 | |||
301 | /* Request leave initialisation */
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302 | CANx->MCR &= ~(uint32_t)CAN_MCR_INRQ; |
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303 | |||
304 | /* Wait the acknowledge */
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305 | wait_ack = 0;
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306 | |||
307 | while (((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))
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308 | { |
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309 | wait_ack++; |
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310 | } |
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311 | |||
312 | /* ...and check acknowledged */
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313 | if ((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
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314 | { |
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315 | InitStatus = CAN_InitStatus_Failed; |
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316 | } |
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317 | else
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318 | { |
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319 | InitStatus = CAN_InitStatus_Success ; |
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320 | } |
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321 | } |
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322 | |||
323 | /* At this step, return the status of initialization */
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324 | return InitStatus;
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325 | } |
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326 | |||
327 | /**
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328 | * @brief Configures the CAN reception filter according to the specified
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329 | * parameters in the CAN_FilterInitStruct.
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330 | * @param CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef structure that
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331 | * contains the configuration information.
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332 | * @retval None
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333 | */
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334 | void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct)
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335 | { |
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336 | uint32_t filter_number_bit_pos = 0;
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337 | /* Check the parameters */
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338 | assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber)); |
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339 | assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode)); |
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340 | assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale)); |
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341 | assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment)); |
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342 | assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation)); |
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343 | |||
344 | filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber;
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345 | |||
346 | /* Initialisation mode for the filter */
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347 | CAN1->FMR |= FMR_FINIT; |
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348 | |||
349 | /* Filter Deactivation */
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350 | CAN1->FA1R &= ~(uint32_t)filter_number_bit_pos; |
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351 | |||
352 | /* Filter Scale */
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353 | if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit)
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354 | { |
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355 | /* 16-bit scale for the filter */
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356 | CAN1->FS1R &= ~(uint32_t)filter_number_bit_pos; |
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357 | |||
358 | /* First 16-bit identifier and First 16-bit mask */
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359 | /* Or First 16-bit identifier and Second 16-bit identifier */
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360 | CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = |
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361 | ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) | |
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362 | (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
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363 | |||
364 | /* Second 16-bit identifier and Second 16-bit mask */
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365 | /* Or Third 16-bit identifier and Fourth 16-bit identifier */
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366 | CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = |
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367 | ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | |
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368 | (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh);
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369 | } |
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370 | |||
371 | if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit)
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372 | { |
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373 | /* 32-bit scale for the filter */
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374 | CAN1->FS1R |= filter_number_bit_pos; |
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375 | /* 32-bit identifier or First 32-bit identifier */
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376 | CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = |
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377 | ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) | |
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378 | (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
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379 | /* 32-bit mask or Second 32-bit identifier */
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380 | CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = |
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381 | ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | |
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382 | (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow);
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383 | } |
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384 | |||
385 | /* Filter Mode */
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386 | if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask)
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387 | { |
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388 | /*Id/Mask mode for the filter*/
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389 | CAN1->FM1R &= ~(uint32_t)filter_number_bit_pos; |
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390 | } |
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391 | else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ |
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392 | { |
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393 | /*Identifier list mode for the filter*/
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394 | CAN1->FM1R |= (uint32_t)filter_number_bit_pos; |
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395 | } |
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396 | |||
397 | /* Filter FIFO assignment */
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398 | if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0)
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399 | { |
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400 | /* FIFO 0 assignation for the filter */
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401 | CAN1->FFA1R &= ~(uint32_t)filter_number_bit_pos; |
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402 | } |
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403 | |||
404 | if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1)
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405 | { |
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406 | /* FIFO 1 assignation for the filter */
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407 | CAN1->FFA1R |= (uint32_t)filter_number_bit_pos; |
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408 | } |
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409 | |||
410 | /* Filter activation */
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411 | if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE)
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412 | { |
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413 | CAN1->FA1R |= filter_number_bit_pos; |
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414 | } |
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415 | |||
416 | /* Leave the initialisation mode for the filter */
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417 | CAN1->FMR &= ~FMR_FINIT; |
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418 | } |
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419 | |||
420 | /**
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421 | * @brief Fills each CAN_InitStruct member with its default value.
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422 | * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure which ill be initialized.
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423 | * @retval None
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424 | */
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425 | void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct)
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426 | { |
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427 | /* Reset CAN init structure parameters values */
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428 | |||
429 | /* Initialize the time triggered communication mode */
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430 | CAN_InitStruct->CAN_TTCM = DISABLE; |
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431 | |||
432 | /* Initialize the automatic bus-off management */
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433 | CAN_InitStruct->CAN_ABOM = DISABLE; |
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434 | |||
435 | /* Initialize the automatic wake-up mode */
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436 | CAN_InitStruct->CAN_AWUM = DISABLE; |
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437 | |||
438 | /* Initialize the no automatic retransmission */
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439 | CAN_InitStruct->CAN_NART = DISABLE; |
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440 | |||
441 | /* Initialize the receive FIFO locked mode */
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442 | CAN_InitStruct->CAN_RFLM = DISABLE; |
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443 | |||
444 | /* Initialize the transmit FIFO priority */
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445 | CAN_InitStruct->CAN_TXFP = DISABLE; |
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446 | |||
447 | /* Initialize the CAN_Mode member */
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448 | CAN_InitStruct->CAN_Mode = CAN_Mode_Normal; |
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449 | |||
450 | /* Initialize the CAN_SJW member */
|
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451 | CAN_InitStruct->CAN_SJW = CAN_SJW_1tq; |
||
452 | |||
453 | /* Initialize the CAN_BS1 member */
|
||
454 | CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq; |
||
455 | |||
456 | /* Initialize the CAN_BS2 member */
|
||
457 | CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq; |
||
458 | |||
459 | /* Initialize the CAN_Prescaler member */
|
||
460 | CAN_InitStruct->CAN_Prescaler = 1;
|
||
461 | } |
||
462 | |||
463 | /**
|
||
464 | * @brief Select the start bank filter for slave CAN.
|
||
465 | * @param CAN_BankNumber: Select the start slave bank filter from 1..27.
|
||
466 | * @retval None
|
||
467 | */
|
||
468 | void CAN_SlaveStartBank(uint8_t CAN_BankNumber)
|
||
469 | { |
||
470 | /* Check the parameters */
|
||
471 | assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber)); |
||
472 | |||
473 | /* Enter Initialisation mode for the filter */
|
||
474 | CAN1->FMR |= FMR_FINIT; |
||
475 | |||
476 | /* Select the start slave bank */
|
||
477 | CAN1->FMR &= (uint32_t)0xFFFFC0F1 ;
|
||
478 | CAN1->FMR |= (uint32_t)(CAN_BankNumber)<<8;
|
||
479 | |||
480 | /* Leave Initialisation mode for the filter */
|
||
481 | CAN1->FMR &= ~FMR_FINIT; |
||
482 | } |
||
483 | |||
484 | /**
|
||
485 | * @brief Enables or disables the DBG Freeze for CAN.
|
||
486 | * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
|
||
487 | * @param NewState: new state of the CAN peripheral.
|
||
488 | * This parameter can be: ENABLE (CAN reception/transmission is frozen
|
||
489 | * during debug. Reception FIFOs can still be accessed/controlled normally)
|
||
490 | * or DISABLE (CAN is working during debug).
|
||
491 | * @retval None
|
||
492 | */
|
||
493 | void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState)
|
||
494 | { |
||
495 | /* Check the parameters */
|
||
496 | assert_param(IS_CAN_ALL_PERIPH(CANx)); |
||
497 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
||
498 | |||
499 | if (NewState != DISABLE)
|
||
500 | { |
||
501 | /* Enable Debug Freeze */
|
||
502 | CANx->MCR |= MCR_DBF; |
||
503 | } |
||
504 | else
|
||
505 | { |
||
506 | /* Disable Debug Freeze */
|
||
507 | CANx->MCR &= ~MCR_DBF; |
||
508 | } |
||
509 | } |
||
510 | |||
511 | |||
512 | /**
|
||
513 | * @brief Enables or disables the CAN Time TriggerOperation communication mode.
|
||
514 | * @note DLC must be programmed as 8 in order Time Stamp (2 bytes) to be
|
||
515 | * sent over the CAN bus.
|
||
516 | * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
|
||
517 | * @param NewState: Mode new state. This parameter can be: ENABLE or DISABLE.
|
||
518 | * When enabled, Time stamp (TIME[15:0]) value is sent in the last two
|
||
519 | * data bytes of the 8-byte message: TIME[7:0] in data byte 6 and TIME[15:8]
|
||
520 | * in data byte 7.
|
||
521 | * @retval None
|
||
522 | */
|
||
523 | void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState)
|
||
524 | { |
||
525 | /* Check the parameters */
|
||
526 | assert_param(IS_CAN_ALL_PERIPH(CANx)); |
||
527 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
||
528 | if (NewState != DISABLE)
|
||
529 | { |
||
530 | /* Enable the TTCM mode */
|
||
531 | CANx->MCR |= CAN_MCR_TTCM; |
||
532 | |||
533 | /* Set TGT bits */
|
||
534 | CANx->sTxMailBox[0].TDTR |= ((uint32_t)CAN_TDT0R_TGT);
|
||
535 | CANx->sTxMailBox[1].TDTR |= ((uint32_t)CAN_TDT1R_TGT);
|
||
536 | CANx->sTxMailBox[2].TDTR |= ((uint32_t)CAN_TDT2R_TGT);
|
||
537 | } |
||
538 | else
|
||
539 | { |
||
540 | /* Disable the TTCM mode */
|
||
541 | CANx->MCR &= (uint32_t)(~(uint32_t)CAN_MCR_TTCM); |
||
542 | |||
543 | /* Reset TGT bits */
|
||
544 | CANx->sTxMailBox[0].TDTR &= ((uint32_t)~CAN_TDT0R_TGT);
|
||
545 | CANx->sTxMailBox[1].TDTR &= ((uint32_t)~CAN_TDT1R_TGT);
|
||
546 | CANx->sTxMailBox[2].TDTR &= ((uint32_t)~CAN_TDT2R_TGT);
|
||
547 | } |
||
548 | } |
||
549 | /**
|
||
550 | * @}
|
||
551 | */
|
||
552 | |||
553 | |||
554 | /** @defgroup CAN_Group2 CAN Frames Transmission functions
|
||
555 | * @brief CAN Frames Transmission functions
|
||
556 | *
|
||
557 | @verbatim
|
||
558 | ===============================================================================
|
||
559 | ##### CAN Frames Transmission functions #####
|
||
560 | ===============================================================================
|
||
561 | [..] This section provides functions allowing to
|
||
562 | (+) Initiate and transmit a CAN frame message (if there is an empty mailbox).
|
||
563 | (+) Check the transmission status of a CAN Frame
|
||
564 | (+) Cancel a transmit request
|
||
565 |
|
||
566 | @endverbatim
|
||
567 | * @{
|
||
568 | */
|
||
569 | |||
570 | /**
|
||
571 | * @brief Initiates and transmits a CAN frame message.
|
||
572 | * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
|
||
573 | * @param TxMessage: pointer to a structure which contains CAN Id, CAN DLC and CAN data.
|
||
574 | * @retval The number of the mailbox that is used for transmission or
|
||
575 | * CAN_TxStatus_NoMailBox if there is no empty mailbox.
|
||
576 | */
|
||
577 | uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage) |
||
578 | { |
||
579 | uint8_t transmit_mailbox = 0;
|
||
580 | /* Check the parameters */
|
||
581 | assert_param(IS_CAN_ALL_PERIPH(CANx)); |
||
582 | assert_param(IS_CAN_IDTYPE(TxMessage->IDE)); |
||
583 | assert_param(IS_CAN_RTR(TxMessage->RTR)); |
||
584 | assert_param(IS_CAN_DLC(TxMessage->DLC)); |
||
585 | |||
586 | /* Select one empty transmit mailbox */
|
||
587 | if ((CANx->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
|
||
588 | { |
||
589 | transmit_mailbox = 0;
|
||
590 | } |
||
591 | else if ((CANx->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) |
||
592 | { |
||
593 | transmit_mailbox = 1;
|
||
594 | } |
||
595 | else if ((CANx->TSR&CAN_TSR_TME2) == CAN_TSR_TME2) |
||
596 | { |
||
597 | transmit_mailbox = 2;
|
||
598 | } |
||
599 | else
|
||
600 | { |
||
601 | transmit_mailbox = CAN_TxStatus_NoMailBox; |
||
602 | } |
||
603 | |||
604 | if (transmit_mailbox != CAN_TxStatus_NoMailBox)
|
||
605 | { |
||
606 | /* Set up the Id */
|
||
607 | CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ; |
||
608 | if (TxMessage->IDE == CAN_Id_Standard)
|
||
609 | { |
||
610 | assert_param(IS_CAN_STDID(TxMessage->StdId)); |
||
611 | CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | \
|
||
612 | TxMessage->RTR); |
||
613 | } |
||
614 | else
|
||
615 | { |
||
616 | assert_param(IS_CAN_EXTID(TxMessage->ExtId)); |
||
617 | CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId << 3) | \
|
||
618 | TxMessage->IDE | \ |
||
619 | TxMessage->RTR); |
||
620 | } |
||
621 | |||
622 | /* Set up the DLC */
|
||
623 | TxMessage->DLC &= (uint8_t)0x0000000F;
|
||
624 | CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0;
|
||
625 | CANx->sTxMailBox[transmit_mailbox].TDTR |= TxMessage->DLC; |
||
626 | |||
627 | /* Set up the data field */
|
||
628 | CANx->sTxMailBox[transmit_mailbox].TDLR = (((uint32_t)TxMessage->Data[3] << 24) | |
||
629 | ((uint32_t)TxMessage->Data[2] << 16) | |
||
630 | ((uint32_t)TxMessage->Data[1] << 8) | |
||
631 | ((uint32_t)TxMessage->Data[0]));
|
||
632 | CANx->sTxMailBox[transmit_mailbox].TDHR = (((uint32_t)TxMessage->Data[7] << 24) | |
||
633 | ((uint32_t)TxMessage->Data[6] << 16) | |
||
634 | ((uint32_t)TxMessage->Data[5] << 8) | |
||
635 | ((uint32_t)TxMessage->Data[4]));
|
||
636 | /* Request transmission */
|
||
637 | CANx->sTxMailBox[transmit_mailbox].TIR |= TMIDxR_TXRQ; |
||
638 | } |
||
639 | return transmit_mailbox;
|
||
640 | } |
||
641 | |||
642 | /**
|
||
643 | * @brief Checks the transmission status of a CAN Frame.
|
||
644 | * @param CANx: where x can be 1 or 2 to select the CAN peripheral.
|
||
645 | * @param TransmitMailbox: the number of the mailbox that is used for transmission.
|
||
646 | * @retval CAN_TxStatus_Ok if the CAN driver transmits the message,
|
||
647 | * CAN_TxStatus_Failed in an other case.
|
||
648 | */
|
||
649 | uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox) |
||
650 | { |
||
651 | uint32_t state = 0;
|
||
652 | |||
653 | /* Check the parameters */
|
||
654 | assert_param(IS_CAN_ALL_PERIPH(CANx)); |
||
655 | assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox)); |
||
656 | |||
657 | switch (TransmitMailbox)
|
||
658 | { |
||
659 | case (CAN_TXMAILBOX_0):
|
||
660 | state = CANx->TSR & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0); |
||
661 | break;
|
||
662 | case (CAN_TXMAILBOX_1):
|
||
663 | state = CANx->TSR & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1); |
||
664 | break;
|
||
665 | case (CAN_TXMAILBOX_2):
|
||
666 | state = CANx->TSR & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2); |
||
667 | break;
|
||
668 | default:
|
||
669 | state = CAN_TxStatus_Failed; |
||
670 | break;
|
||
671 | } |
||
672 | switch (state)
|
||
673 | { |
||
674 | /* transmit pending */
|
||
675 | case (0x0): state = CAN_TxStatus_Pending; |
||
676 | break;
|
||
677 | /* transmit failed */
|
||
678 | case (CAN_TSR_RQCP0 | CAN_TSR_TME0): state = CAN_TxStatus_Failed;
|
||
679 | break;
|
||
680 | case (CAN_TSR_RQCP1 | CAN_TSR_TME1): state = CAN_TxStatus_Failed;
|
||
681 | break;
|
||
682 | case (CAN_TSR_RQCP2 | CAN_TSR_TME2): state = CAN_TxStatus_Failed;
|
||
683 | break;
|
||
684 | /* transmit succeeded */
|
||
685 | case (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0):state = CAN_TxStatus_Ok;
|
||
686 | break;
|
||
687 | case (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1):state = CAN_TxStatus_Ok;
|
||
688 | break;
|
||
689 | case (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2):state = CAN_TxStatus_Ok;
|
||
690 | break;
|
||
691 | default: state = CAN_TxStatus_Failed;
|
||
692 | break;
|
||
693 | } |
||
694 | return (uint8_t) state;
|
||
695 | } |
||
696 | |||
697 | /**
|
||
698 | * @brief Cancels a transmit request.
|
||
699 | * @param CANx: where x can be 1 or 2 to select the CAN peripheral.
|
||
700 | * @param Mailbox: Mailbox number.
|
||
701 | * @retval None
|
||
702 | */
|
||
703 | void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox)
|
||
704 | { |
||
705 | /* Check the parameters */
|
||
706 | assert_param(IS_CAN_ALL_PERIPH(CANx)); |
||
707 | assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox)); |
||
708 | /* abort transmission */
|
||
709 | switch (Mailbox)
|
||
710 | { |
||
711 | case (CAN_TXMAILBOX_0): CANx->TSR |= CAN_TSR_ABRQ0;
|
||
712 | break;
|
||
713 | case (CAN_TXMAILBOX_1): CANx->TSR |= CAN_TSR_ABRQ1;
|
||
714 | break;
|
||
715 | case (CAN_TXMAILBOX_2): CANx->TSR |= CAN_TSR_ABRQ2;
|
||
716 | break;
|
||
717 | default:
|
||
718 | break;
|
||
719 | } |
||
720 | } |
||
721 | /**
|
||
722 | * @}
|
||
723 | */
|
||
724 | |||
725 | |||
726 | /** @defgroup CAN_Group3 CAN Frames Reception functions
|
||
727 | * @brief CAN Frames Reception functions
|
||
728 | *
|
||
729 | @verbatim
|
||
730 | ===============================================================================
|
||
731 | ##### CAN Frames Reception functions #####
|
||
732 | ===============================================================================
|
||
733 | [..] This section provides functions allowing to
|
||
734 | (+) Receive a correct CAN frame
|
||
735 | (+) Release a specified receive FIFO (2 FIFOs are available)
|
||
736 | (+) Return the number of the pending received CAN frames
|
||
737 |
|
||
738 | @endverbatim
|
||
739 | * @{
|
||
740 | */
|
||
741 | |||
742 | /**
|
||
743 | * @brief Receives a correct CAN frame.
|
||
744 | * @param CANx: where x can be 1 or 2 to select the CAN peripheral.
|
||
745 | * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
|
||
746 | * @param RxMessage: pointer to a structure receive frame which contains CAN Id,
|
||
747 | * CAN DLC, CAN data and FMI number.
|
||
748 | * @retval None
|
||
749 | */
|
||
750 | void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage)
|
||
751 | { |
||
752 | /* Check the parameters */
|
||
753 | assert_param(IS_CAN_ALL_PERIPH(CANx)); |
||
754 | assert_param(IS_CAN_FIFO(FIFONumber)); |
||
755 | /* Get the Id */
|
||
756 | RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR;
|
||
757 | if (RxMessage->IDE == CAN_Id_Standard)
|
||
758 | { |
||
759 | RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21); |
||
760 | } |
||
761 | else
|
||
762 | { |
||
763 | RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3); |
||
764 | } |
||
765 | |||
766 | RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR;
|
||
767 | /* Get the DLC */
|
||
768 | RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR;
|
||
769 | /* Get the FMI */
|
||
770 | RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8); |
||
771 | /* Get the data field */
|
||
772 | RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR; |
||
773 | RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8); |
||
774 | RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16); |
||
775 | RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24); |
||
776 | RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR; |
||
777 | RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8); |
||
778 | RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16); |
||
779 | RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24); |
||
780 | /* Release the FIFO */
|
||
781 | /* Release FIFO0 */
|
||
782 | if (FIFONumber == CAN_FIFO0)
|
||
783 | { |
||
784 | CANx->RF0R |= CAN_RF0R_RFOM0; |
||
785 | } |
||
786 | /* Release FIFO1 */
|
||
787 | else /* FIFONumber == CAN_FIFO1 */ |
||
788 | { |
||
789 | CANx->RF1R |= CAN_RF1R_RFOM1; |
||
790 | } |
||
791 | } |
||
792 | |||
793 | /**
|
||
794 | * @brief Releases the specified receive FIFO.
|
||
795 | * @param CANx: where x can be 1 or 2 to select the CAN peripheral.
|
||
796 | * @param FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1.
|
||
797 | * @retval None
|
||
798 | */
|
||
799 | void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber)
|
||
800 | { |
||
801 | /* Check the parameters */
|
||
802 | assert_param(IS_CAN_ALL_PERIPH(CANx)); |
||
803 | assert_param(IS_CAN_FIFO(FIFONumber)); |
||
804 | /* Release FIFO0 */
|
||
805 | if (FIFONumber == CAN_FIFO0)
|
||
806 | { |
||
807 | CANx->RF0R |= CAN_RF0R_RFOM0; |
||
808 | } |
||
809 | /* Release FIFO1 */
|
||
810 | else /* FIFONumber == CAN_FIFO1 */ |
||
811 | { |
||
812 | CANx->RF1R |= CAN_RF1R_RFOM1; |
||
813 | } |
||
814 | } |
||
815 | |||
816 | /**
|
||
817 | * @brief Returns the number of pending received messages.
|
||
818 | * @param CANx: where x can be 1 or 2 to select the CAN peripheral.
|
||
819 | * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
|
||
820 | * @retval NbMessage : which is the number of pending message.
|
||
821 | */
|
||
822 | uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber) |
||
823 | { |
||
824 | uint8_t message_pending=0;
|
||
825 | /* Check the parameters */
|
||
826 | assert_param(IS_CAN_ALL_PERIPH(CANx)); |
||
827 | assert_param(IS_CAN_FIFO(FIFONumber)); |
||
828 | if (FIFONumber == CAN_FIFO0)
|
||
829 | { |
||
830 | message_pending = (uint8_t)(CANx->RF0R&(uint32_t)0x03);
|
||
831 | } |
||
832 | else if (FIFONumber == CAN_FIFO1) |
||
833 | { |
||
834 | message_pending = (uint8_t)(CANx->RF1R&(uint32_t)0x03);
|
||
835 | } |
||
836 | else
|
||
837 | { |
||
838 | message_pending = 0;
|
||
839 | } |
||
840 | return message_pending;
|
||
841 | } |
||
842 | /**
|
||
843 | * @}
|
||
844 | */
|
||
845 | |||
846 | |||
847 | /** @defgroup CAN_Group4 CAN Operation modes functions
|
||
848 | * @brief CAN Operation modes functions
|
||
849 | *
|
||
850 | @verbatim
|
||
851 | ===============================================================================
|
||
852 | ##### CAN Operation modes functions #####
|
||
853 | ===============================================================================
|
||
854 | [..] This section provides functions allowing to select the CAN Operation modes
|
||
855 | (+) sleep mode
|
||
856 | (+) normal mode
|
||
857 | (+) initialization mode
|
||
858 |
|
||
859 | @endverbatim
|
||
860 | * @{
|
||
861 | */
|
||
862 | |||
863 | |||
864 | /**
|
||
865 | * @brief Selects the CAN Operation mode.
|
||
866 | * @param CAN_OperatingMode: CAN Operating Mode.
|
||
867 | * This parameter can be one of @ref CAN_OperatingMode_TypeDef enumeration.
|
||
868 | * @retval status of the requested mode which can be
|
||
869 | * - CAN_ModeStatus_Failed: CAN failed entering the specific mode
|
||
870 | * - CAN_ModeStatus_Success: CAN Succeed entering the specific mode
|
||
871 | */
|
||
872 | uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode) |
||
873 | { |
||
874 | uint8_t status = CAN_ModeStatus_Failed; |
||
875 | |||
876 | /* Timeout for INAK or also for SLAK bits*/
|
||
877 | uint32_t timeout = INAK_TIMEOUT; |
||
878 | |||
879 | /* Check the parameters */
|
||
880 | assert_param(IS_CAN_ALL_PERIPH(CANx)); |
||
881 | assert_param(IS_CAN_OPERATING_MODE(CAN_OperatingMode)); |
||
882 | |||
883 | if (CAN_OperatingMode == CAN_OperatingMode_Initialization)
|
||
884 | { |
||
885 | /* Request initialisation */
|
||
886 | CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_SLEEP)) | CAN_MCR_INRQ); |
||
887 | |||
888 | /* Wait the acknowledge */
|
||
889 | while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) && (timeout != 0)) |
||
890 | { |
||
891 | timeout--; |
||
892 | } |
||
893 | if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK)
|
||
894 | { |
||
895 | status = CAN_ModeStatus_Failed; |
||
896 | } |
||
897 | else
|
||
898 | { |
||
899 | status = CAN_ModeStatus_Success; |
||
900 | } |
||
901 | } |
||
902 | else if (CAN_OperatingMode == CAN_OperatingMode_Normal) |
||
903 | { |
||
904 | /* Request leave initialisation and sleep mode and enter Normal mode */
|
||
905 | CANx->MCR &= (uint32_t)(~(CAN_MCR_SLEEP|CAN_MCR_INRQ)); |
||
906 | |||
907 | /* Wait the acknowledge */
|
||
908 | while (((CANx->MSR & CAN_MODE_MASK) != 0) && (timeout!=0)) |
||
909 | { |
||
910 | timeout--; |
||
911 | } |
||
912 | if ((CANx->MSR & CAN_MODE_MASK) != 0) |
||
913 | { |
||
914 | status = CAN_ModeStatus_Failed; |
||
915 | } |
||
916 | else
|
||
917 | { |
||
918 | status = CAN_ModeStatus_Success; |
||
919 | } |
||
920 | } |
||
921 | else if (CAN_OperatingMode == CAN_OperatingMode_Sleep) |
||
922 | { |
||
923 | /* Request Sleep mode */
|
||
924 | CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); |
||
925 | |||
926 | /* Wait the acknowledge */
|
||
927 | while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) && (timeout!=0)) |
||
928 | { |
||
929 | timeout--; |
||
930 | } |
||
931 | if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK)
|
||
932 | { |
||
933 | status = CAN_ModeStatus_Failed; |
||
934 | } |
||
935 | else
|
||
936 | { |
||
937 | status = CAN_ModeStatus_Success; |
||
938 | } |
||
939 | } |
||
940 | else
|
||
941 | { |
||
942 | status = CAN_ModeStatus_Failed; |
||
943 | } |
||
944 | |||
945 | return (uint8_t) status;
|
||
946 | } |
||
947 | |||
948 | /**
|
||
949 | * @brief Enters the Sleep (low power) mode.
|
||
950 | * @param CANx: where x can be 1 or 2 to select the CAN peripheral.
|
||
951 | * @retval CAN_Sleep_Ok if sleep entered, CAN_Sleep_Failed otherwise.
|
||
952 | */
|
||
953 | uint8_t CAN_Sleep(CAN_TypeDef* CANx) |
||
954 | { |
||
955 | uint8_t sleepstatus = CAN_Sleep_Failed; |
||
956 | |||
957 | /* Check the parameters */
|
||
958 | assert_param(IS_CAN_ALL_PERIPH(CANx)); |
||
959 | |||
960 | /* Request Sleep mode */
|
||
961 | CANx->MCR = (((CANx->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); |
||
962 | |||
963 | /* Sleep mode status */
|
||
964 | if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK)
|
||
965 | { |
||
966 | /* Sleep mode not entered */
|
||
967 | sleepstatus = CAN_Sleep_Ok; |
||
968 | } |
||
969 | /* return sleep mode status */
|
||
970 | return (uint8_t)sleepstatus;
|
||
971 | } |
||
972 | |||
973 | /**
|
||
974 | * @brief Wakes up the CAN peripheral from sleep mode .
|
||
975 | * @param CANx: where x can be 1 or 2 to select the CAN peripheral.
|
||
976 | * @retval CAN_WakeUp_Ok if sleep mode left, CAN_WakeUp_Failed otherwise.
|
||
977 | */
|
||
978 | uint8_t CAN_WakeUp(CAN_TypeDef* CANx) |
||
979 | { |
||
980 | uint32_t wait_slak = SLAK_TIMEOUT; |
||
981 | uint8_t wakeupstatus = CAN_WakeUp_Failed; |
||
982 | |||
983 | /* Check the parameters */
|
||
984 | assert_param(IS_CAN_ALL_PERIPH(CANx)); |
||
985 | |||
986 | /* Wake up request */
|
||
987 | CANx->MCR &= ~(uint32_t)CAN_MCR_SLEEP; |
||
988 | |||
989 | /* Sleep mode status */
|
||
990 | while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00)) |
||
991 | { |
||
992 | wait_slak--; |
||
993 | } |
||
994 | if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK)
|
||
995 | { |
||
996 | /* wake up done : Sleep mode exited */
|
||
997 | wakeupstatus = CAN_WakeUp_Ok; |
||
998 | } |
||
999 | /* return wakeup status */
|
||
1000 | return (uint8_t)wakeupstatus;
|
||
1001 | } |
||
1002 | /**
|
||
1003 | * @}
|
||
1004 | */
|
||
1005 | |||
1006 | |||
1007 | /** @defgroup CAN_Group5 CAN Bus Error management functions
|
||
1008 | * @brief CAN Bus Error management functions
|
||
1009 | *
|
||
1010 | @verbatim
|
||
1011 | ===============================================================================
|
||
1012 | ##### CAN Bus Error management functions #####
|
||
1013 | ===============================================================================
|
||
1014 | [..] This section provides functions allowing to
|
||
1015 | (+) Return the CANx's last error code (LEC)
|
||
1016 | (+) Return the CANx Receive Error Counter (REC)
|
||
1017 | (+) Return the LSB of the 9-bit CANx Transmit Error Counter(TEC).
|
||
1018 |
|
||
1019 | -@- If TEC is greater than 255, The CAN is in bus-off state.
|
||
1020 | -@- if REC or TEC are greater than 96, an Error warning flag occurs.
|
||
1021 | -@- if REC or TEC are greater than 127, an Error Passive Flag occurs.
|
||
1022 |
|
||
1023 | @endverbatim
|
||
1024 | * @{
|
||
1025 | */
|
||
1026 | |||
1027 | /**
|
||
1028 | * @brief Returns the CANx's last error code (LEC).
|
||
1029 | * @param CANx: where x can be 1 or 2 to select the CAN peripheral.
|
||
1030 | * @retval Error code:
|
||
1031 | * - CAN_ERRORCODE_NoErr: No Error
|
||
1032 | * - CAN_ERRORCODE_StuffErr: Stuff Error
|
||
1033 | * - CAN_ERRORCODE_FormErr: Form Error
|
||
1034 | * - CAN_ERRORCODE_ACKErr : Acknowledgment Error
|
||
1035 | * - CAN_ERRORCODE_BitRecessiveErr: Bit Recessive Error
|
||
1036 | * - CAN_ERRORCODE_BitDominantErr: Bit Dominant Error
|
||
1037 | * - CAN_ERRORCODE_CRCErr: CRC Error
|
||
1038 | * - CAN_ERRORCODE_SoftwareSetErr: Software Set Error
|
||
1039 | */
|
||
1040 | uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx) |
||
1041 | { |
||
1042 | uint8_t errorcode=0;
|
||
1043 | |||
1044 | /* Check the parameters */
|
||
1045 | assert_param(IS_CAN_ALL_PERIPH(CANx)); |
||
1046 | |||
1047 | /* Get the error code*/
|
||
1048 | errorcode = (((uint8_t)CANx->ESR) & (uint8_t)CAN_ESR_LEC); |
||
1049 | |||
1050 | /* Return the error code*/
|
||
1051 | return errorcode;
|
||
1052 | } |
||
1053 | |||
1054 | /**
|
||
1055 | * @brief Returns the CANx Receive Error Counter (REC).
|
||
1056 | * @note In case of an error during reception, this counter is incremented
|
||
1057 | * by 1 or by 8 depending on the error condition as defined by the CAN
|
||
1058 | * standard. After every successful reception, the counter is
|
||
1059 | * decremented by 1 or reset to 120 if its value was higher than 128.
|
||
1060 | * When the counter value exceeds 127, the CAN controller enters the
|
||
1061 | * error passive state.
|
||
1062 | * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
|
||
1063 | * @retval CAN Receive Error Counter.
|
||
1064 | */
|
||
1065 | uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx) |
||
1066 | { |
||
1067 | uint8_t counter=0;
|
||
1068 | |||
1069 | /* Check the parameters */
|
||
1070 | assert_param(IS_CAN_ALL_PERIPH(CANx)); |
||
1071 | |||
1072 | /* Get the Receive Error Counter*/
|
||
1073 | counter = (uint8_t)((CANx->ESR & CAN_ESR_REC)>> 24);
|
||
1074 | |||
1075 | /* Return the Receive Error Counter*/
|
||
1076 | return counter;
|
||
1077 | } |
||
1078 | |||
1079 | |||
1080 | /**
|
||
1081 | * @brief Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC).
|
||
1082 | * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
|
||
1083 | * @retval LSB of the 9-bit CAN Transmit Error Counter.
|
||
1084 | */
|
||
1085 | uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx) |
||
1086 | { |
||
1087 | uint8_t counter=0;
|
||
1088 | |||
1089 | /* Check the parameters */
|
||
1090 | assert_param(IS_CAN_ALL_PERIPH(CANx)); |
||
1091 | |||
1092 | /* Get the LSB of the 9-bit CANx Transmit Error Counter(TEC) */
|
||
1093 | counter = (uint8_t)((CANx->ESR & CAN_ESR_TEC)>> 16);
|
||
1094 | |||
1095 | /* Return the LSB of the 9-bit CANx Transmit Error Counter(TEC) */
|
||
1096 | return counter;
|
||
1097 | } |
||
1098 | /**
|
||
1099 | * @}
|
||
1100 | */
|
||
1101 | |||
1102 | /** @defgroup CAN_Group6 Interrupts and flags management functions
|
||
1103 | * @brief Interrupts and flags management functions
|
||
1104 | *
|
||
1105 | @verbatim
|
||
1106 | ===============================================================================
|
||
1107 | ##### Interrupts and flags management functions #####
|
||
1108 | ===============================================================================
|
||
1109 | |||
1110 | [..] This section provides functions allowing to configure the CAN Interrupts
|
||
1111 | and to get the status and clear flags and Interrupts pending bits.
|
||
1112 |
|
||
1113 | The CAN provides 14 Interrupts sources and 15 Flags:
|
||
1114 | |||
1115 |
|
||
1116 | *** Flags ***
|
||
1117 | =============
|
||
1118 | [..] The 15 flags can be divided on 4 groups:
|
||
1119 | |||
1120 | (+) Transmit Flags
|
||
1121 | (++) CAN_FLAG_RQCP0,
|
||
1122 | (++) CAN_FLAG_RQCP1,
|
||
1123 | (++) CAN_FLAG_RQCP2 : Request completed MailBoxes 0, 1 and 2 Flags
|
||
1124 | Set when when the last request (transmit or abort)
|
||
1125 | has been performed.
|
||
1126 | |||
1127 | (+) Receive Flags
|
||
1128 | |||
1129 | |||
1130 | (++) CAN_FLAG_FMP0,
|
||
1131 | (++) CAN_FLAG_FMP1 : FIFO 0 and 1 Message Pending Flags
|
||
1132 | set to signal that messages are pending in the receive
|
||
1133 | FIFO.
|
||
1134 | These Flags are cleared only by hardware.
|
||
1135 | |||
1136 | (++) CAN_FLAG_FF0,
|
||
1137 | (++) CAN_FLAG_FF1 : FIFO 0 and 1 Full Flags
|
||
1138 | set when three messages are stored in the selected
|
||
1139 | FIFO.
|
||
1140 | |||
1141 | (++) CAN_FLAG_FOV0
|
||
1142 | (++) CAN_FLAG_FOV1 : FIFO 0 and 1 Overrun Flags
|
||
1143 | set when a new message has been received and passed
|
||
1144 | the filter while the FIFO was full.
|
||
1145 | |||
1146 | (+) Operating Mode Flags
|
||
1147 | |||
1148 | (++) CAN_FLAG_WKU : Wake up Flag
|
||
1149 | set to signal that a SOF bit has been detected while
|
||
1150 | the CAN hardware was in Sleep mode.
|
||
1151 |
|
||
1152 | (++) CAN_FLAG_SLAK : Sleep acknowledge Flag
|
||
1153 | Set to signal that the CAN has entered Sleep Mode.
|
||
1154 |
|
||
1155 | (+) Error Flags
|
||
1156 | |||
1157 | (++) CAN_FLAG_EWG : Error Warning Flag
|
||
1158 | Set when the warning limit has been reached (Receive
|
||
1159 | Error Counter or Transmit Error Counter greater than 96).
|
||
1160 | This Flag is cleared only by hardware.
|
||
1161 |
|
||
1162 | (++) CAN_FLAG_EPV : Error Passive Flag
|
||
1163 | Set when the Error Passive limit has been reached
|
||
1164 | (Receive Error Counter or Transmit Error Counter
|
||
1165 | greater than 127).
|
||
1166 | This Flag is cleared only by hardware.
|
||
1167 |
|
||
1168 | (++) CAN_FLAG_BOF : Bus-Off Flag
|
||
1169 | set when CAN enters the bus-off state. The bus-off
|
||
1170 | state is entered on TEC overflow, greater than 255.
|
||
1171 | This Flag is cleared only by hardware.
|
||
1172 |
|
||
1173 | (++) CAN_FLAG_LEC : Last error code Flag
|
||
1174 | set If a message has been transferred (reception or
|
||
1175 | transmission) with error, and the error code is hold.
|
||
1176 |
|
||
1177 | *** Interrupts ***
|
||
1178 | ==================
|
||
1179 | [..] The 14 interrupts can be divided on 4 groups:
|
||
1180 |
|
||
1181 | (+) Transmit interrupt
|
||
1182 |
|
||
1183 | (++) CAN_IT_TME : Transmit mailbox empty Interrupt
|
||
1184 | if enabled, this interrupt source is pending when
|
||
1185 | no transmit request are pending for Tx mailboxes.
|
||
1186 | |||
1187 | (+) Receive Interrupts
|
||
1188 |
|
||
1189 | (++) CAN_IT_FMP0,
|
||
1190 | (++) CAN_IT_FMP1 : FIFO 0 and FIFO1 message pending Interrupts
|
||
1191 | if enabled, these interrupt sources are pending
|
||
1192 | when messages are pending in the receive FIFO.
|
||
1193 | The corresponding interrupt pending bits are cleared
|
||
1194 | only by hardware.
|
||
1195 |
|
||
1196 | (++) CAN_IT_FF0,
|
||
1197 | (++) CAN_IT_FF1 : FIFO 0 and FIFO1 full Interrupts
|
||
1198 | if enabled, these interrupt sources are pending
|
||
1199 | when three messages are stored in the selected FIFO.
|
||
1200 |
|
||
1201 | (++) CAN_IT_FOV0,
|
||
1202 | (++) CAN_IT_FOV1 : FIFO 0 and FIFO1 overrun Interrupts
|
||
1203 | if enabled, these interrupt sources are pending
|
||
1204 | when a new message has been received and passed
|
||
1205 | the filter while the FIFO was full.
|
||
1206 | |||
1207 | (+) Operating Mode Interrupts
|
||
1208 |
|
||
1209 | (++) CAN_IT_WKU : Wake-up Interrupt
|
||
1210 | if enabled, this interrupt source is pending when
|
||
1211 | a SOF bit has been detected while the CAN hardware
|
||
1212 | was in Sleep mode.
|
||
1213 |
|
||
1214 | (++) CAN_IT_SLK : Sleep acknowledge Interrupt
|
||
1215 | if enabled, this interrupt source is pending when
|
||
1216 | the CAN has entered Sleep Mode.
|
||
1217 | |||
1218 | (+) Error Interrupts
|
||
1219 |
|
||
1220 | (++) CAN_IT_EWG : Error warning Interrupt
|
||
1221 | if enabled, this interrupt source is pending when
|
||
1222 | the warning limit has been reached (Receive Error
|
||
1223 | Counter or Transmit Error Counter=96).
|
||
1224 |
|
||
1225 | (++) CAN_IT_EPV : Error passive Interrupt
|
||
1226 | if enabled, this interrupt source is pending when
|
||
1227 | the Error Passive limit has been reached (Receive
|
||
1228 | Error Counter or Transmit Error Counter>127).
|
||
1229 |
|
||
1230 | (++) CAN_IT_BOF : Bus-off Interrupt
|
||
1231 | if enabled, this interrupt source is pending when
|
||
1232 | CAN enters the bus-off state. The bus-off state is
|
||
1233 | entered on TEC overflow, greater than 255.
|
||
1234 | This Flag is cleared only by hardware.
|
||
1235 |
|
||
1236 | (++) CAN_IT_LEC : Last error code Interrupt
|
||
1237 | if enabled, this interrupt source is pending when
|
||
1238 | a message has been transferred (reception or
|
||
1239 | transmission) with error, and the error code is hold.
|
||
1240 |
|
||
1241 | (++) CAN_IT_ERR : Error Interrupt
|
||
1242 | if enabled, this interrupt source is pending when
|
||
1243 | an error condition is pending.
|
||
1244 |
|
||
1245 | [..] Managing the CAN controller events :
|
||
1246 |
|
||
1247 | The user should identify which mode will be used in his application to
|
||
1248 | manage the CAN controller events: Polling mode or Interrupt mode.
|
||
1249 |
|
||
1250 | (#) In the Polling Mode it is advised to use the following functions:
|
||
1251 | (++) CAN_GetFlagStatus() : to check if flags events occur.
|
||
1252 | (++) CAN_ClearFlag() : to clear the flags events.
|
||
1253 |
|
||
1254 | |||
1255 |
|
||
1256 | (#) In the Interrupt Mode it is advised to use the following functions:
|
||
1257 | (++) CAN_ITConfig() : to enable or disable the interrupt source.
|
||
1258 | (++) CAN_GetITStatus() : to check if Interrupt occurs.
|
||
1259 | (++) CAN_ClearITPendingBit() : to clear the Interrupt pending Bit
|
||
1260 | (corresponding Flag).
|
||
1261 | -@@- This function has no impact on CAN_IT_FMP0 and CAN_IT_FMP1 Interrupts
|
||
1262 | pending bits since there are cleared only by hardware.
|
||
1263 |
|
||
1264 | @endverbatim
|
||
1265 | * @{
|
||
1266 | */
|
||
1267 | /**
|
||
1268 | * @brief Enables or disables the specified CANx interrupts.
|
||
1269 | * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
|
||
1270 | * @param CAN_IT: specifies the CAN interrupt sources to be enabled or disabled.
|
||
1271 | * This parameter can be:
|
||
1272 | * @arg CAN_IT_TME: Transmit mailbox empty Interrupt
|
||
1273 | * @arg CAN_IT_FMP0: FIFO 0 message pending Interrupt
|
||
1274 | * @arg CAN_IT_FF0: FIFO 0 full Interrupt
|
||
1275 | * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt
|
||
1276 | * @arg CAN_IT_FMP1: FIFO 1 message pending Interrupt
|
||
1277 | * @arg CAN_IT_FF1: FIFO 1 full Interrupt
|
||
1278 | * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt
|
||
1279 | * @arg CAN_IT_WKU: Wake-up Interrupt
|
||
1280 | * @arg CAN_IT_SLK: Sleep acknowledge Interrupt
|
||
1281 | * @arg CAN_IT_EWG: Error warning Interrupt
|
||
1282 | * @arg CAN_IT_EPV: Error passive Interrupt
|
||
1283 | * @arg CAN_IT_BOF: Bus-off Interrupt
|
||
1284 | * @arg CAN_IT_LEC: Last error code Interrupt
|
||
1285 | * @arg CAN_IT_ERR: Error Interrupt
|
||
1286 | * @param NewState: new state of the CAN interrupts.
|
||
1287 | * This parameter can be: ENABLE or DISABLE.
|
||
1288 | * @retval None
|
||
1289 | */
|
||
1290 | void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState)
|
||
1291 | { |
||
1292 | /* Check the parameters */
|
||
1293 | assert_param(IS_CAN_ALL_PERIPH(CANx)); |
||
1294 | assert_param(IS_CAN_IT(CAN_IT)); |
||
1295 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
||
1296 | |||
1297 | if (NewState != DISABLE)
|
||
1298 | { |
||
1299 | /* Enable the selected CANx interrupt */
|
||
1300 | CANx->IER |= CAN_IT; |
||
1301 | } |
||
1302 | else
|
||
1303 | { |
||
1304 | /* Disable the selected CANx interrupt */
|
||
1305 | CANx->IER &= ~CAN_IT; |
||
1306 | } |
||
1307 | } |
||
1308 | /**
|
||
1309 | * @brief Checks whether the specified CAN flag is set or not.
|
||
1310 | * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
|
||
1311 | * @param CAN_FLAG: specifies the flag to check.
|
||
1312 | * This parameter can be one of the following values:
|
||
1313 | * @arg CAN_FLAG_RQCP0: Request MailBox0 Flag
|
||
1314 | * @arg CAN_FLAG_RQCP1: Request MailBox1 Flag
|
||
1315 | * @arg CAN_FLAG_RQCP2: Request MailBox2 Flag
|
||
1316 | * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
|
||
1317 | * @arg CAN_FLAG_FF0: FIFO 0 Full Flag
|
||
1318 | * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
|
||
1319 | * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
|
||
1320 | * @arg CAN_FLAG_FF1: FIFO 1 Full Flag
|
||
1321 | * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
|
||
1322 | * @arg CAN_FLAG_WKU: Wake up Flag
|
||
1323 | * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
|
||
1324 | * @arg CAN_FLAG_EWG: Error Warning Flag
|
||
1325 | * @arg CAN_FLAG_EPV: Error Passive Flag
|
||
1326 | * @arg CAN_FLAG_BOF: Bus-Off Flag
|
||
1327 | * @arg CAN_FLAG_LEC: Last error code Flag
|
||
1328 | * @retval The new state of CAN_FLAG (SET or RESET).
|
||
1329 | */
|
||
1330 | FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG) |
||
1331 | { |
||
1332 | FlagStatus bitstatus = RESET; |
||
1333 | |||
1334 | /* Check the parameters */
|
||
1335 | assert_param(IS_CAN_ALL_PERIPH(CANx)); |
||
1336 | assert_param(IS_CAN_GET_FLAG(CAN_FLAG)); |
||
1337 | |||
1338 | |||
1339 | if((CAN_FLAG & CAN_FLAGS_ESR) != (uint32_t)RESET)
|
||
1340 | { |
||
1341 | /* Check the status of the specified CAN flag */
|
||
1342 | if ((CANx->ESR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) |
||
1343 | { |
||
1344 | /* CAN_FLAG is set */
|
||
1345 | bitstatus = SET; |
||
1346 | } |
||
1347 | else
|
||
1348 | { |
||
1349 | /* CAN_FLAG is reset */
|
||
1350 | bitstatus = RESET; |
||
1351 | } |
||
1352 | } |
||
1353 | else if((CAN_FLAG & CAN_FLAGS_MSR) != (uint32_t)RESET) |
||
1354 | { |
||
1355 | /* Check the status of the specified CAN flag */
|
||
1356 | if ((CANx->MSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) |
||
1357 | { |
||
1358 | /* CAN_FLAG is set */
|
||
1359 | bitstatus = SET; |
||
1360 | } |
||
1361 | else
|
||
1362 | { |
||
1363 | /* CAN_FLAG is reset */
|
||
1364 | bitstatus = RESET; |
||
1365 | } |
||
1366 | } |
||
1367 | else if((CAN_FLAG & CAN_FLAGS_TSR) != (uint32_t)RESET) |
||
1368 | { |
||
1369 | /* Check the status of the specified CAN flag */
|
||
1370 | if ((CANx->TSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) |
||
1371 | { |
||
1372 | /* CAN_FLAG is set */
|
||
1373 | bitstatus = SET; |
||
1374 | } |
||
1375 | else
|
||
1376 | { |
||
1377 | /* CAN_FLAG is reset */
|
||
1378 | bitstatus = RESET; |
||
1379 | } |
||
1380 | } |
||
1381 | else if((CAN_FLAG & CAN_FLAGS_RF0R) != (uint32_t)RESET) |
||
1382 | { |
||
1383 | /* Check the status of the specified CAN flag */
|
||
1384 | if ((CANx->RF0R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) |
||
1385 | { |
||
1386 | /* CAN_FLAG is set */
|
||
1387 | bitstatus = SET; |
||
1388 | } |
||
1389 | else
|
||
1390 | { |
||
1391 | /* CAN_FLAG is reset */
|
||
1392 | bitstatus = RESET; |
||
1393 | } |
||
1394 | } |
||
1395 | else /* If(CAN_FLAG & CAN_FLAGS_RF1R != (uint32_t)RESET) */ |
||
1396 | { |
||
1397 | /* Check the status of the specified CAN flag */
|
||
1398 | if ((uint32_t)(CANx->RF1R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) |
||
1399 | { |
||
1400 | /* CAN_FLAG is set */
|
||
1401 | bitstatus = SET; |
||
1402 | } |
||
1403 | else
|
||
1404 | { |
||
1405 | /* CAN_FLAG is reset */
|
||
1406 | bitstatus = RESET; |
||
1407 | } |
||
1408 | } |
||
1409 | /* Return the CAN_FLAG status */
|
||
1410 | return bitstatus;
|
||
1411 | } |
||
1412 | |||
1413 | /**
|
||
1414 | * @brief Clears the CAN's pending flags.
|
||
1415 | * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
|
||
1416 | * @param CAN_FLAG: specifies the flag to clear.
|
||
1417 | * This parameter can be one of the following values:
|
||
1418 | * @arg CAN_FLAG_RQCP0: Request MailBox0 Flag
|
||
1419 | * @arg CAN_FLAG_RQCP1: Request MailBox1 Flag
|
||
1420 | * @arg CAN_FLAG_RQCP2: Request MailBox2 Flag
|
||
1421 | * @arg CAN_FLAG_FF0: FIFO 0 Full Flag
|
||
1422 | * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
|
||
1423 | * @arg CAN_FLAG_FF1: FIFO 1 Full Flag
|
||
1424 | * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
|
||
1425 | * @arg CAN_FLAG_WKU: Wake up Flag
|
||
1426 | * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
|
||
1427 | * @arg CAN_FLAG_LEC: Last error code Flag
|
||
1428 | * @retval None
|
||
1429 | */
|
||
1430 | void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
|
||
1431 | { |
||
1432 | uint32_t flagtmp=0;
|
||
1433 | /* Check the parameters */
|
||
1434 | assert_param(IS_CAN_ALL_PERIPH(CANx)); |
||
1435 | assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG)); |
||
1436 | |||
1437 | if (CAN_FLAG == CAN_FLAG_LEC) /* ESR register */ |
||
1438 | { |
||
1439 | /* Clear the selected CAN flags */
|
||
1440 | CANx->ESR = (uint32_t)RESET; |
||
1441 | } |
||
1442 | else /* MSR or TSR or RF0R or RF1R */ |
||
1443 | { |
||
1444 | flagtmp = CAN_FLAG & 0x000FFFFF;
|
||
1445 | |||
1446 | if ((CAN_FLAG & CAN_FLAGS_RF0R)!=(uint32_t)RESET)
|
||
1447 | { |
||
1448 | /* Receive Flags */
|
||
1449 | CANx->RF0R = (uint32_t)(flagtmp); |
||
1450 | } |
||
1451 | else if ((CAN_FLAG & CAN_FLAGS_RF1R)!=(uint32_t)RESET) |
||
1452 | { |
||
1453 | /* Receive Flags */
|
||
1454 | CANx->RF1R = (uint32_t)(flagtmp); |
||
1455 | } |
||
1456 | else if ((CAN_FLAG & CAN_FLAGS_TSR)!=(uint32_t)RESET) |
||
1457 | { |
||
1458 | /* Transmit Flags */
|
||
1459 | CANx->TSR = (uint32_t)(flagtmp); |
||
1460 | } |
||
1461 | else /* If((CAN_FLAG & CAN_FLAGS_MSR)!=(uint32_t)RESET) */ |
||
1462 | { |
||
1463 | /* Operating mode Flags */
|
||
1464 | CANx->MSR = (uint32_t)(flagtmp); |
||
1465 | } |
||
1466 | } |
||
1467 | } |
||
1468 | |||
1469 | /**
|
||
1470 | * @brief Checks whether the specified CANx interrupt has occurred or not.
|
||
1471 | * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
|
||
1472 | * @param CAN_IT: specifies the CAN interrupt source to check.
|
||
1473 | * This parameter can be one of the following values:
|
||
1474 | * @arg CAN_IT_TME: Transmit mailbox empty Interrupt
|
||
1475 | * @arg CAN_IT_FMP0: FIFO 0 message pending Interrupt
|
||
1476 | * @arg CAN_IT_FF0: FIFO 0 full Interrupt
|
||
1477 | * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt
|
||
1478 | * @arg CAN_IT_FMP1: FIFO 1 message pending Interrupt
|
||
1479 | * @arg CAN_IT_FF1: FIFO 1 full Interrupt
|
||
1480 | * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt
|
||
1481 | * @arg CAN_IT_WKU: Wake-up Interrupt
|
||
1482 | * @arg CAN_IT_SLK: Sleep acknowledge Interrupt
|
||
1483 | * @arg CAN_IT_EWG: Error warning Interrupt
|
||
1484 | * @arg CAN_IT_EPV: Error passive Interrupt
|
||
1485 | * @arg CAN_IT_BOF: Bus-off Interrupt
|
||
1486 | * @arg CAN_IT_LEC: Last error code Interrupt
|
||
1487 | * @arg CAN_IT_ERR: Error Interrupt
|
||
1488 | * @retval The current state of CAN_IT (SET or RESET).
|
||
1489 | */
|
||
1490 | ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT) |
||
1491 | { |
||
1492 | ITStatus itstatus = RESET; |
||
1493 | /* Check the parameters */
|
||
1494 | assert_param(IS_CAN_ALL_PERIPH(CANx)); |
||
1495 | assert_param(IS_CAN_IT(CAN_IT)); |
||
1496 | |||
1497 | /* check the interrupt enable bit */
|
||
1498 | if((CANx->IER & CAN_IT) != RESET)
|
||
1499 | { |
||
1500 | /* in case the Interrupt is enabled, .... */
|
||
1501 | switch (CAN_IT)
|
||
1502 | { |
||
1503 | case CAN_IT_TME:
|
||
1504 | /* Check CAN_TSR_RQCPx bits */
|
||
1505 | itstatus = CheckITStatus(CANx->TSR, CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2); |
||
1506 | break;
|
||
1507 | case CAN_IT_FMP0:
|
||
1508 | /* Check CAN_RF0R_FMP0 bit */
|
||
1509 | itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FMP0); |
||
1510 | break;
|
||
1511 | case CAN_IT_FF0:
|
||
1512 | /* Check CAN_RF0R_FULL0 bit */
|
||
1513 | itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FULL0); |
||
1514 | break;
|
||
1515 | case CAN_IT_FOV0:
|
||
1516 | /* Check CAN_RF0R_FOVR0 bit */
|
||
1517 | itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FOVR0); |
||
1518 | break;
|
||
1519 | case CAN_IT_FMP1:
|
||
1520 | /* Check CAN_RF1R_FMP1 bit */
|
||
1521 | itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FMP1); |
||
1522 | break;
|
||
1523 | case CAN_IT_FF1:
|
||
1524 | /* Check CAN_RF1R_FULL1 bit */
|
||
1525 | itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FULL1); |
||
1526 | break;
|
||
1527 | case CAN_IT_FOV1:
|
||
1528 | /* Check CAN_RF1R_FOVR1 bit */
|
||
1529 | itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FOVR1); |
||
1530 | break;
|
||
1531 | case CAN_IT_WKU:
|
||
1532 | /* Check CAN_MSR_WKUI bit */
|
||
1533 | itstatus = CheckITStatus(CANx->MSR, CAN_MSR_WKUI); |
||
1534 | break;
|
||
1535 | case CAN_IT_SLK:
|
||
1536 | /* Check CAN_MSR_SLAKI bit */
|
||
1537 | itstatus = CheckITStatus(CANx->MSR, CAN_MSR_SLAKI); |
||
1538 | break;
|
||
1539 | case CAN_IT_EWG:
|
||
1540 | /* Check CAN_ESR_EWGF bit */
|
||
1541 | itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF); |
||
1542 | break;
|
||
1543 | case CAN_IT_EPV:
|
||
1544 | /* Check CAN_ESR_EPVF bit */
|
||
1545 | itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EPVF); |
||
1546 | break;
|
||
1547 | case CAN_IT_BOF:
|
||
1548 | /* Check CAN_ESR_BOFF bit */
|
||
1549 | itstatus = CheckITStatus(CANx->ESR, CAN_ESR_BOFF); |
||
1550 | break;
|
||
1551 | case CAN_IT_LEC:
|
||
1552 | /* Check CAN_ESR_LEC bit */
|
||
1553 | itstatus = CheckITStatus(CANx->ESR, CAN_ESR_LEC); |
||
1554 | break;
|
||
1555 | case CAN_IT_ERR:
|
||
1556 | /* Check CAN_MSR_ERRI bit */
|
||
1557 | itstatus = CheckITStatus(CANx->MSR, CAN_MSR_ERRI); |
||
1558 | break;
|
||
1559 | default:
|
||
1560 | /* in case of error, return RESET */
|
||
1561 | itstatus = RESET; |
||
1562 | break;
|
||
1563 | } |
||
1564 | } |
||
1565 | else
|
||
1566 | { |
||
1567 | /* in case the Interrupt is not enabled, return RESET */
|
||
1568 | itstatus = RESET; |
||
1569 | } |
||
1570 | |||
1571 | /* Return the CAN_IT status */
|
||
1572 | return itstatus;
|
||
1573 | } |
||
1574 | |||
1575 | /**
|
||
1576 | * @brief Clears the CANx's interrupt pending bits.
|
||
1577 | * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
|
||
1578 | * @param CAN_IT: specifies the interrupt pending bit to clear.
|
||
1579 | * This parameter can be one of the following values:
|
||
1580 | * @arg CAN_IT_TME: Transmit mailbox empty Interrupt
|
||
1581 | * @arg CAN_IT_FF0: FIFO 0 full Interrupt
|
||
1582 | * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt
|
||
1583 | * @arg CAN_IT_FF1: FIFO 1 full Interrupt
|
||
1584 | * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt
|
||
1585 | * @arg CAN_IT_WKU: Wake-up Interrupt
|
||
1586 | * @arg CAN_IT_SLK: Sleep acknowledge Interrupt
|
||
1587 | * @arg CAN_IT_EWG: Error warning Interrupt
|
||
1588 | * @arg CAN_IT_EPV: Error passive Interrupt
|
||
1589 | * @arg CAN_IT_BOF: Bus-off Interrupt
|
||
1590 | * @arg CAN_IT_LEC: Last error code Interrupt
|
||
1591 | * @arg CAN_IT_ERR: Error Interrupt
|
||
1592 | * @retval None
|
||
1593 | */
|
||
1594 | void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT)
|
||
1595 | { |
||
1596 | /* Check the parameters */
|
||
1597 | assert_param(IS_CAN_ALL_PERIPH(CANx)); |
||
1598 | assert_param(IS_CAN_CLEAR_IT(CAN_IT)); |
||
1599 | |||
1600 | switch (CAN_IT)
|
||
1601 | { |
||
1602 | case CAN_IT_TME:
|
||
1603 | /* Clear CAN_TSR_RQCPx (rc_w1)*/
|
||
1604 | CANx->TSR = CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2; |
||
1605 | break;
|
||
1606 | case CAN_IT_FF0:
|
||
1607 | /* Clear CAN_RF0R_FULL0 (rc_w1)*/
|
||
1608 | CANx->RF0R = CAN_RF0R_FULL0; |
||
1609 | break;
|
||
1610 | case CAN_IT_FOV0:
|
||
1611 | /* Clear CAN_RF0R_FOVR0 (rc_w1)*/
|
||
1612 | CANx->RF0R = CAN_RF0R_FOVR0; |
||
1613 | break;
|
||
1614 | case CAN_IT_FF1:
|
||
1615 | /* Clear CAN_RF1R_FULL1 (rc_w1)*/
|
||
1616 | CANx->RF1R = CAN_RF1R_FULL1; |
||
1617 | break;
|
||
1618 | case CAN_IT_FOV1:
|
||
1619 | /* Clear CAN_RF1R_FOVR1 (rc_w1)*/
|
||
1620 | CANx->RF1R = CAN_RF1R_FOVR1; |
||
1621 | break;
|
||
1622 | case CAN_IT_WKU:
|
||
1623 | /* Clear CAN_MSR_WKUI (rc_w1)*/
|
||
1624 | CANx->MSR = CAN_MSR_WKUI; |
||
1625 | break;
|
||
1626 | case CAN_IT_SLK:
|
||
1627 | /* Clear CAN_MSR_SLAKI (rc_w1)*/
|
||
1628 | CANx->MSR = CAN_MSR_SLAKI; |
||
1629 | break;
|
||
1630 | case CAN_IT_EWG:
|
||
1631 | /* Clear CAN_MSR_ERRI (rc_w1) */
|
||
1632 | CANx->MSR = CAN_MSR_ERRI; |
||
1633 | /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/
|
||
1634 | break;
|
||
1635 | case CAN_IT_EPV:
|
||
1636 | /* Clear CAN_MSR_ERRI (rc_w1) */
|
||
1637 | CANx->MSR = CAN_MSR_ERRI; |
||
1638 | /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/
|
||
1639 | break;
|
||
1640 | case CAN_IT_BOF:
|
||
1641 | /* Clear CAN_MSR_ERRI (rc_w1) */
|
||
1642 | CANx->MSR = CAN_MSR_ERRI; |
||
1643 | /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/
|
||
1644 | break;
|
||
1645 | case CAN_IT_LEC:
|
||
1646 | /* Clear LEC bits */
|
||
1647 | CANx->ESR = RESET; |
||
1648 | /* Clear CAN_MSR_ERRI (rc_w1) */
|
||
1649 | CANx->MSR = CAN_MSR_ERRI; |
||
1650 | break;
|
||
1651 | case CAN_IT_ERR:
|
||
1652 | /*Clear LEC bits */
|
||
1653 | CANx->ESR = RESET; |
||
1654 | /* Clear CAN_MSR_ERRI (rc_w1) */
|
||
1655 | CANx->MSR = CAN_MSR_ERRI; |
||
1656 | /* @note BOFF, EPVF and EWGF Flags are cleared by hardware depending on the CAN Bus status*/
|
||
1657 | break;
|
||
1658 | default:
|
||
1659 | break;
|
||
1660 | } |
||
1661 | } |
||
1662 | /**
|
||
1663 | * @}
|
||
1664 | */
|
||
1665 | |||
1666 | /**
|
||
1667 | * @brief Checks whether the CAN interrupt has occurred or not.
|
||
1668 | * @param CAN_Reg: specifies the CAN interrupt register to check.
|
||
1669 | * @param It_Bit: specifies the interrupt source bit to check.
|
||
1670 | * @retval The new state of the CAN Interrupt (SET or RESET).
|
||
1671 | */
|
||
1672 | static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit)
|
||
1673 | { |
||
1674 | ITStatus pendingbitstatus = RESET; |
||
1675 | |||
1676 | if ((CAN_Reg & It_Bit) != (uint32_t)RESET)
|
||
1677 | { |
||
1678 | /* CAN_IT is set */
|
||
1679 | pendingbitstatus = SET; |
||
1680 | } |
||
1681 | else
|
||
1682 | { |
||
1683 | /* CAN_IT is reset */
|
||
1684 | pendingbitstatus = RESET; |
||
1685 | } |
||
1686 | return pendingbitstatus;
|
||
1687 | } |
||
1688 | |||
1689 | /**
|
||
1690 | * @}
|
||
1691 | */
|
||
1692 | |||
1693 | /**
|
||
1694 | * @}
|
||
1695 | */
|
||
1696 | |||
1697 | /**
|
||
1698 | * @}
|
||
1699 | */
|
||
1700 | |||
1701 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|