amiro-blt / Target / Modules / PowerManagement_1-1 / Boot / lib / stdperiphlib / STM32F4xx_StdPeriph_Driver / src / stm32f4xx_iwdg.c @ 367c0652
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1 | 69661903 | Thomas Schöpping | /**
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2 | ******************************************************************************
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3 | * @file stm32f4xx_iwdg.c
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4 | * @author MCD Application Team
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5 | * @version V1.1.0
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6 | * @date 11-January-2013
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7 | * @brief This file provides firmware functions to manage the following
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8 | * functionalities of the Independent watchdog (IWDG) peripheral:
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9 | * + Prescaler and Counter configuration
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10 | * + IWDG activation
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11 | * + Flag management
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12 | *
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13 | @verbatim
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14 | ===============================================================================
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15 | ##### IWDG features #####
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16 | ===============================================================================
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17 | [..]
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18 | The IWDG can be started by either software or hardware (configurable
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19 | through option byte).
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20 |
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21 | The IWDG is clocked by its own dedicated low-speed clock (LSI) and
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22 | thus stays active even if the main clock fails.
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23 | Once the IWDG is started, the LSI is forced ON and cannot be disabled
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24 | (LSI cannot be disabled too), and the counter starts counting down from
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25 | the reset value of 0xFFF. When it reaches the end of count value (0x000)
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26 | a system reset is generated.
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27 | The IWDG counter should be reloaded at regular intervals to prevent
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28 | an MCU reset.
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29 |
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30 | The IWDG is implemented in the VDD voltage domain that is still functional
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31 | in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
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32 |
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33 | IWDGRST flag in RCC_CSR register can be used to inform when a IWDG
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34 | reset occurs.
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35 |
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36 | Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
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37 | The IWDG timeout may vary due to LSI frequency dispersion. STM32F4xx
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38 | devices provide the capability to measure the LSI frequency (LSI clock
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39 | connected internally to TIM5 CH4 input capture). The measured value
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40 | can be used to have an IWDG timeout with an acceptable accuracy.
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41 | For more information, please refer to the STM32F4xx Reference manual
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42 |
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43 | ##### How to use this driver #####
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44 | ===============================================================================
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45 | [..]
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46 | (#) Enable write access to IWDG_PR and IWDG_RLR registers using
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47 | IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function
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48 |
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49 | (#) Configure the IWDG prescaler using IWDG_SetPrescaler() function
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50 |
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51 | (#) Configure the IWDG counter value using IWDG_SetReload() function.
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52 | This value will be loaded in the IWDG counter each time the counter
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53 | is reloaded, then the IWDG will start counting down from this value.
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54 |
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55 | (#) Start the IWDG using IWDG_Enable() function, when the IWDG is used
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56 | in software mode (no need to enable the LSI, it will be enabled
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57 | by hardware)
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58 |
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59 | (#) Then the application program must reload the IWDG counter at regular
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60 | intervals during normal operation to prevent an MCU reset, using
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61 | IWDG_ReloadCounter() function.
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62 |
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63 | @endverbatim
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64 | ******************************************************************************
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65 | * @attention
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66 | *
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67 | * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
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68 | *
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69 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
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70 | * You may not use this file except in compliance with the License.
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71 | * You may obtain a copy of the License at:
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72 | *
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73 | * http://www.st.com/software_license_agreement_liberty_v2
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74 | *
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75 | * Unless required by applicable law or agreed to in writing, software
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76 | * distributed under the License is distributed on an "AS IS" BASIS,
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77 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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78 | * See the License for the specific language governing permissions and
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79 | * limitations under the License.
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80 | *
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81 | ******************************************************************************
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82 | */
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83 | |||
84 | /* Includes ------------------------------------------------------------------*/
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85 | #include "stm32f4xx_iwdg.h" |
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86 | |||
87 | /** @addtogroup STM32F4xx_StdPeriph_Driver
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88 | * @{
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89 | */
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90 | |||
91 | /** @defgroup IWDG
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92 | * @brief IWDG driver modules
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93 | * @{
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94 | */
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95 | |||
96 | /* Private typedef -----------------------------------------------------------*/
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97 | /* Private define ------------------------------------------------------------*/
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98 | |||
99 | /* KR register bit mask */
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100 | #define KR_KEY_RELOAD ((uint16_t)0xAAAA) |
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101 | #define KR_KEY_ENABLE ((uint16_t)0xCCCC) |
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102 | |||
103 | /* Private macro -------------------------------------------------------------*/
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104 | /* Private variables ---------------------------------------------------------*/
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105 | /* Private function prototypes -----------------------------------------------*/
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106 | /* Private functions ---------------------------------------------------------*/
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107 | |||
108 | /** @defgroup IWDG_Private_Functions
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109 | * @{
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110 | */
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111 | |||
112 | /** @defgroup IWDG_Group1 Prescaler and Counter configuration functions
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113 | * @brief Prescaler and Counter configuration functions
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114 | *
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115 | @verbatim
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116 | ===============================================================================
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117 | ##### Prescaler and Counter configuration functions #####
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118 | ===============================================================================
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119 | |||
120 | @endverbatim
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121 | * @{
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122 | */
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123 | |||
124 | /**
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125 | * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers.
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126 | * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.
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127 | * This parameter can be one of the following values:
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128 | * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
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129 | * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
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130 | * @retval None
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131 | */
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132 | void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
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133 | { |
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134 | /* Check the parameters */
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135 | assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess)); |
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136 | IWDG->KR = IWDG_WriteAccess; |
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137 | } |
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138 | |||
139 | /**
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140 | * @brief Sets IWDG Prescaler value.
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141 | * @param IWDG_Prescaler: specifies the IWDG Prescaler value.
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142 | * This parameter can be one of the following values:
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143 | * @arg IWDG_Prescaler_4: IWDG prescaler set to 4
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144 | * @arg IWDG_Prescaler_8: IWDG prescaler set to 8
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145 | * @arg IWDG_Prescaler_16: IWDG prescaler set to 16
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146 | * @arg IWDG_Prescaler_32: IWDG prescaler set to 32
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147 | * @arg IWDG_Prescaler_64: IWDG prescaler set to 64
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148 | * @arg IWDG_Prescaler_128: IWDG prescaler set to 128
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149 | * @arg IWDG_Prescaler_256: IWDG prescaler set to 256
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150 | * @retval None
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151 | */
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152 | void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
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153 | { |
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154 | /* Check the parameters */
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155 | assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler)); |
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156 | IWDG->PR = IWDG_Prescaler; |
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157 | } |
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158 | |||
159 | /**
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160 | * @brief Sets IWDG Reload value.
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161 | * @param Reload: specifies the IWDG Reload value.
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162 | * This parameter must be a number between 0 and 0x0FFF.
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163 | * @retval None
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164 | */
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165 | void IWDG_SetReload(uint16_t Reload)
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166 | { |
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167 | /* Check the parameters */
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168 | assert_param(IS_IWDG_RELOAD(Reload)); |
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169 | IWDG->RLR = Reload; |
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170 | } |
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171 | |||
172 | /**
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173 | * @brief Reloads IWDG counter with value defined in the reload register
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174 | * (write access to IWDG_PR and IWDG_RLR registers disabled).
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175 | * @param None
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176 | * @retval None
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177 | */
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178 | void IWDG_ReloadCounter(void) |
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179 | { |
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180 | IWDG->KR = KR_KEY_RELOAD; |
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181 | } |
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182 | |||
183 | /**
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184 | * @}
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185 | */
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186 | |||
187 | /** @defgroup IWDG_Group2 IWDG activation function
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188 | * @brief IWDG activation function
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189 | *
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190 | @verbatim
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191 | ===============================================================================
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192 | ##### IWDG activation function #####
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193 | ===============================================================================
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194 | |||
195 | @endverbatim
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196 | * @{
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197 | */
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198 | |||
199 | /**
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200 | * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
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201 | * @param None
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202 | * @retval None
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203 | */
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204 | void IWDG_Enable(void) |
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205 | { |
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206 | IWDG->KR = KR_KEY_ENABLE; |
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207 | } |
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208 | |||
209 | /**
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210 | * @}
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211 | */
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212 | |||
213 | /** @defgroup IWDG_Group3 Flag management function
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214 | * @brief Flag management function
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215 | *
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216 | @verbatim
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217 | ===============================================================================
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218 | ##### Flag management function #####
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219 | ===============================================================================
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220 | |||
221 | @endverbatim
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222 | * @{
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223 | */
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224 | |||
225 | /**
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226 | * @brief Checks whether the specified IWDG flag is set or not.
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227 | * @param IWDG_FLAG: specifies the flag to check.
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228 | * This parameter can be one of the following values:
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229 | * @arg IWDG_FLAG_PVU: Prescaler Value Update on going
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230 | * @arg IWDG_FLAG_RVU: Reload Value Update on going
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231 | * @retval The new state of IWDG_FLAG (SET or RESET).
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232 | */
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233 | FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) |
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234 | { |
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235 | FlagStatus bitstatus = RESET; |
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236 | /* Check the parameters */
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237 | assert_param(IS_IWDG_FLAG(IWDG_FLAG)); |
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238 | if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)
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239 | { |
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240 | bitstatus = SET; |
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241 | } |
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242 | else
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243 | { |
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244 | bitstatus = RESET; |
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245 | } |
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246 | /* Return the flag status */
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247 | return bitstatus;
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248 | } |
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249 | |||
250 | /**
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251 | * @}
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252 | */
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253 | |||
254 | /**
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255 | * @}
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256 | */
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257 | |||
258 | /**
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259 | * @}
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260 | */
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261 | |||
262 | /**
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263 | * @}
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264 | */
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265 | |||
266 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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