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1 69661903 Thomas Schöpping
/**
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  ******************************************************************************
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  * @file    stm32f4xx_rcc.c
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  * @author  MCD Application Team
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  * @version V1.1.0
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  * @date    11-January-2013
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  * @brief   This file provides firmware functions to manage the following 
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  *          functionalities of the Reset and clock control (RCC) peripheral:
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  *           + Internal/external clocks, PLL, CSS and MCO configuration
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  *           + System, AHB and APB busses clocks configuration
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  *           + Peripheral clocks configuration
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  *           + Interrupts and flags management
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  *
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 @verbatim                
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 ===============================================================================
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                      ##### RCC specific features #####
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 ===============================================================================
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    [..]  
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      After reset the device is running from Internal High Speed oscillator 
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      (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache 
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      and I-Cache are disabled, and all peripherals are off except internal
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      SRAM, Flash and JTAG.
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      (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
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          all peripherals mapped on these busses are running at HSI speed.
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      (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
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      (+) All GPIOs are in input floating state, except the JTAG pins which
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          are assigned to be used for debug purpose.
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    [..]          
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      Once the device started from reset, the user application has to:        
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      (+) Configure the clock source to be used to drive the System clock
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          (if the application needs higher frequency/performance)
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      (+) Configure the System clock frequency and Flash settings  
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      (+) Configure the AHB and APB busses prescalers
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      (+) Enable the clock for the peripheral(s) to be used
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      (+) Configure the clock source(s) for peripherals which clocks are not
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          derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)                                
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 @endverbatim    
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  ******************************************************************************
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  * @attention
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  *
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  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
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  *
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  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
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  * You may not use this file except in compliance with the License.
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  * You may obtain a copy of the License at:
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  *
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  *        http://www.st.com/software_license_agreement_liberty_v2
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  *
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  * Unless required by applicable law or agreed to in writing, software 
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  * distributed under the License is distributed on an "AS IS" BASIS, 
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  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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  * See the License for the specific language governing permissions and
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  * limitations under the License.
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  *
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  ******************************************************************************
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  */
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58
/* Includes ------------------------------------------------------------------*/
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#include "stm32f4xx_rcc.h"
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61
/** @addtogroup STM32F4xx_StdPeriph_Driver
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  * @{
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  */
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65
/** @defgroup RCC 
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  * @brief RCC driver modules
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  * @{
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  */ 
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70
/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/* ------------ RCC registers bit address in the alias region ----------- */
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#define RCC_OFFSET                (RCC_BASE - PERIPH_BASE)
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/* --- CR Register ---*/
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/* Alias word address of HSION bit */
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#define CR_OFFSET                 (RCC_OFFSET + 0x00)
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#define HSION_BitNumber           0x00
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#define CR_HSION_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
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/* Alias word address of CSSON bit */
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#define CSSON_BitNumber           0x13
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#define CR_CSSON_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
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/* Alias word address of PLLON bit */
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#define PLLON_BitNumber           0x18
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#define CR_PLLON_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
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/* Alias word address of PLLI2SON bit */
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#define PLLI2SON_BitNumber        0x1A
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#define CR_PLLI2SON_BB            (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4))
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/* --- CFGR Register ---*/
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/* Alias word address of I2SSRC bit */
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#define CFGR_OFFSET               (RCC_OFFSET + 0x08)
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#define I2SSRC_BitNumber          0x17
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#define CFGR_I2SSRC_BB            (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4))
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95
/* --- BDCR Register ---*/
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/* Alias word address of RTCEN bit */
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#define BDCR_OFFSET               (RCC_OFFSET + 0x70)
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#define RTCEN_BitNumber           0x0F
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#define BDCR_RTCEN_BB             (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
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/* Alias word address of BDRST bit */
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#define BDRST_BitNumber           0x10
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#define BDCR_BDRST_BB             (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
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104
/* --- CSR Register ---*/
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/* Alias word address of LSION bit */
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#define CSR_OFFSET                (RCC_OFFSET + 0x74)
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#define LSION_BitNumber           0x00
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#define CSR_LSION_BB              (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
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/* --- DCKCFGR Register ---*/
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/* Alias word address of TIMPRE bit */
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#define DCKCFGR_OFFSET            (RCC_OFFSET + 0x8C)
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#define TIMPRE_BitNumber          0x18
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#define DCKCFGR_TIMPRE_BB         (PERIPH_BB_BASE + (DCKCFGR_OFFSET * 32) + (TIMPRE_BitNumber * 4))
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/* ---------------------- RCC registers bit mask ------------------------ */
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/* CFGR register bit mask */
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#define CFGR_MCO2_RESET_MASK      ((uint32_t)0x07FFFFFF)
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#define CFGR_MCO1_RESET_MASK      ((uint32_t)0xF89FFFFF)
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120
/* RCC Flag Mask */
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#define FLAG_MASK                 ((uint8_t)0x1F)
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/* CR register byte 3 (Bits[23:16]) base address */
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#define CR_BYTE3_ADDRESS          ((uint32_t)0x40023802)
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/* CIR register byte 2 (Bits[15:8]) base address */
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#define CIR_BYTE2_ADDRESS         ((uint32_t)(RCC_BASE + 0x0C + 0x01))
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/* CIR register byte 3 (Bits[23:16]) base address */
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#define CIR_BYTE3_ADDRESS         ((uint32_t)(RCC_BASE + 0x0C + 0x02))
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/* BDCR register base address */
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#define BDCR_ADDRESS              (PERIPH_BASE + BDCR_OFFSET)
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135
/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
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139
/* Private function prototypes -----------------------------------------------*/
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/* Private functions ---------------------------------------------------------*/
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142
/** @defgroup RCC_Private_Functions
143
  * @{
144
  */ 
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146
/** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions
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 *  @brief   Internal and external clocks, PLL, CSS and MCO configuration functions 
148
 *
149
@verbatim   
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 ===================================================================================
151
 ##### Internal and  external clocks, PLL, CSS and MCO configuration functions #####
152
 ===================================================================================  
153
    [..]
154
      This section provide functions allowing to configure the internal/external clocks,
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      PLLs, CSS and MCO pins.
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      (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
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          the PLL as System clock source.
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      (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
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          clock source.
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      (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
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          through the PLL as System clock source. Can be used also as RTC clock source.
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      (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.   
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      (#) PLL (clocked by HSI or HSE), featuring two different output clocks:
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        (++) The first output is used to generate the high speed system clock (up to 168 MHz)
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        (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
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             the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
172

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      (#) PLLI2S (clocked by HSI or HSE), used to generate an accurate clock to achieve 
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          high-quality audio performance on the I2S interface.
175
  
176
      (#) CSS (Clock security system), once enable and if a HSE clock failure occurs 
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         (HSE used directly or through PLL as System clock source), the System clock
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         is automatically switched to HSI and an interrupt is generated if enabled. 
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         The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt) 
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         exception vector.   
181

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      (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
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          clock (through a configurable prescaler) on PA8 pin.
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      (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
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          clock (through a configurable prescaler) on PC9 pin.
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 @endverbatim
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  * @{
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  */
190
191
/**
192
  * @brief  Resets the RCC clock configuration to the default reset state.
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  * @note   The default reset state of the clock configuration is given below:
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  *            - HSI ON and used as system clock source
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  *            - HSE, PLL and PLLI2S OFF
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  *            - AHB, APB1 and APB2 prescaler set to 1.
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  *            - CSS, MCO1 and MCO2 OFF
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  *            - All interrupts disabled
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  * @note   This function doesn't modify the configuration of the
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  *            - Peripheral clocks  
201
  *            - LSI, LSE and RTC clocks 
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  * @param  None
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  * @retval None
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  */
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void RCC_DeInit(void)
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{
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  /* Set HSION bit */
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  RCC->CR |= (uint32_t)0x00000001;
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210
  /* Reset CFGR register */
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  RCC->CFGR = 0x00000000;
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  /* Reset HSEON, CSSON, PLLON and PLLI2S bits */
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  RCC->CR &= (uint32_t)0xFAF6FFFF;
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  /* Reset PLLCFGR register */
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  RCC->PLLCFGR = 0x24003010;
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  /* Reset PLLI2SCFGR register */
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  RCC->PLLI2SCFGR = 0x20003000;
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  /* Reset HSEBYP bit */
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  RCC->CR &= (uint32_t)0xFFFBFFFF;
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  /* Disable all interrupts */
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  RCC->CIR = 0x00000000;
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228
#ifdef STM32F427X 
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  /* Disable Timers clock prescalers selection */
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  RCC->DCKCFGR = 0x00000000;
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#endif /* STM32F427X */ 
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233
}
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235
/**
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  * @brief  Configures the External High Speed oscillator (HSE).
237
  * @note   After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
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  *         software should wait on HSERDY flag to be set indicating that HSE clock
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  *         is stable and can be used to clock the PLL and/or system clock.
240
  * @note   HSE state can not be changed if it is used directly or through the
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  *         PLL as system clock. In this case, you have to select another source
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  *         of the system clock then change the HSE state (ex. disable it).
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  * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.  
244
  * @note   This function reset the CSSON bit, so if the Clock security system(CSS)
245
  *         was previously enabled you have to enable it again after calling this
246
  *         function.    
247
  * @param  RCC_HSE: specifies the new state of the HSE.
248
  *          This parameter can be one of the following values:
249
  *            @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
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  *                              6 HSE oscillator clock cycles.
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  *            @arg RCC_HSE_ON: turn ON the HSE oscillator
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  *            @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
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  * @retval None
254
  */
255
void RCC_HSEConfig(uint8_t RCC_HSE)
256
{
257
  /* Check the parameters */
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  assert_param(IS_RCC_HSE(RCC_HSE));
259
260
  /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
261
  *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE_OFF;
262
263
  /* Set the new HSE configuration -------------------------------------------*/
264
  *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE;
265
}
266
267
/**
268
  * @brief  Waits for HSE start-up.
269
  * @note   This functions waits on HSERDY flag to be set and return SUCCESS if 
270
  *         this flag is set, otherwise returns ERROR if the timeout is reached 
271
  *         and this flag is not set. The timeout value is defined by the constant
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  *         HSE_STARTUP_TIMEOUT in stm32f4xx.h file. You can tailor it depending
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  *         on the HSE crystal used in your application. 
274
  * @param  None
275
  * @retval An ErrorStatus enumeration value:
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  *          - SUCCESS: HSE oscillator is stable and ready to use
277
  *          - ERROR: HSE oscillator not yet ready
278
  */
279
ErrorStatus RCC_WaitForHSEStartUp(void)
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{
281
  __IO uint32_t startupcounter = 0;
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  ErrorStatus status = ERROR;
283
  FlagStatus hsestatus = RESET;
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  /* Wait till HSE is ready and if Time out is reached exit */
285
  do
286
  {
287
    hsestatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
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    startupcounter++;
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  } while((startupcounter != HSE_STARTUP_TIMEOUT) && (hsestatus == RESET));
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291
  if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
292
  {
293
    status = SUCCESS;
294
  }
295
  else
296
  {
297
    status = ERROR;
298
  }
299
  return (status);
300
}
301
302
/**
303
  * @brief  Adjusts the Internal High Speed oscillator (HSI) calibration value.
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  * @note   The calibration is used to compensate for the variations in voltage
305
  *         and temperature that influence the frequency of the internal HSI RC.
306
  * @param  HSICalibrationValue: specifies the calibration trimming value.
307
  *         This parameter must be a number between 0 and 0x1F.
308
  * @retval None
309
  */
310
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
311
{
312
  uint32_t tmpreg = 0;
313
  /* Check the parameters */
314
  assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));
315
316
  tmpreg = RCC->CR;
317
318
  /* Clear HSITRIM[4:0] bits */
319
  tmpreg &= ~RCC_CR_HSITRIM;
320
321
  /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
322
  tmpreg |= (uint32_t)HSICalibrationValue << 3;
323
324
  /* Store the new value */
325
  RCC->CR = tmpreg;
326
}
327
328
/**
329
  * @brief  Enables or disables the Internal High Speed oscillator (HSI).
330
  * @note   The HSI is stopped by hardware when entering STOP and STANDBY modes.
331
  *         It is used (enabled by hardware) as system clock source after startup
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  *         from Reset, wakeup from STOP and STANDBY mode, or in case of failure
333
  *         of the HSE used directly or indirectly as system clock (if the Clock
334
  *         Security System CSS is enabled).             
335
  * @note   HSI can not be stopped if it is used as system clock source. In this case,
336
  *         you have to select another source of the system clock then stop the HSI.  
337
  * @note   After enabling the HSI, the application software should wait on HSIRDY
338
  *         flag to be set indicating that HSI clock is stable and can be used as
339
  *         system clock source.  
340
  * @param  NewState: new state of the HSI.
341
  *          This parameter can be: ENABLE or DISABLE.
342
  * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
343
  *         clock cycles.  
344
  * @retval None
345
  */
346
void RCC_HSICmd(FunctionalState NewState)
347
{
348
  /* Check the parameters */
349
  assert_param(IS_FUNCTIONAL_STATE(NewState));
350
351
  *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;
352
}
353
354
/**
355
  * @brief  Configures the External Low Speed oscillator (LSE).
356
  * @note   As the LSE is in the Backup domain and write access is denied to
357
  *         this domain after reset, you have to enable write access using 
358
  *         PWR_BackupAccessCmd(ENABLE) function before to configure the LSE
359
  *         (to be done once after reset).  
360
  * @note   After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application
361
  *         software should wait on LSERDY flag to be set indicating that LSE clock
362
  *         is stable and can be used to clock the RTC.
363
  * @param  RCC_LSE: specifies the new state of the LSE.
364
  *          This parameter can be one of the following values:
365
  *            @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
366
  *                              6 LSE oscillator clock cycles.
367
  *            @arg RCC_LSE_ON: turn ON the LSE oscillator
368
  *            @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock
369
  * @retval None
370
  */
371
void RCC_LSEConfig(uint8_t RCC_LSE)
372
{
373
  /* Check the parameters */
374
  assert_param(IS_RCC_LSE(RCC_LSE));
375
376
  /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
377
  /* Reset LSEON bit */
378
  *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
379
380
  /* Reset LSEBYP bit */
381
  *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
382
383
  /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */
384
  switch (RCC_LSE)
385
  {
386
    case RCC_LSE_ON:
387
      /* Set LSEON bit */
388
      *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON;
389
      break;
390
    case RCC_LSE_Bypass:
391
      /* Set LSEBYP and LSEON bits */
392
      *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;
393
      break;
394
    default:
395
      break;
396
  }
397
}
398
399
/**
400
  * @brief  Enables or disables the Internal Low Speed oscillator (LSI).
401
  * @note   After enabling the LSI, the application software should wait on 
402
  *         LSIRDY flag to be set indicating that LSI clock is stable and can
403
  *         be used to clock the IWDG and/or the RTC.
404
  * @note   LSI can not be disabled if the IWDG is running.  
405
  * @param  NewState: new state of the LSI.
406
  *          This parameter can be: ENABLE or DISABLE.
407
  * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
408
  *         clock cycles. 
409
  * @retval None
410
  */
411
void RCC_LSICmd(FunctionalState NewState)
412
{
413
  /* Check the parameters */
414
  assert_param(IS_FUNCTIONAL_STATE(NewState));
415
416
  *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;
417
}
418
419
/**
420
  * @brief  Configures the main PLL clock source, multiplication and division factors.
421
  * @note   This function must be used only when the main PLL is disabled.
422
  *  
423
  * @param  RCC_PLLSource: specifies the PLL entry clock source.
424
  *          This parameter can be one of the following values:
425
  *            @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock entry
426
  *            @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock entry
427
  * @note   This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.  
428
  *  
429
  * @param  PLLM: specifies the division factor for PLL VCO input clock
430
  *          This parameter must be a number between 0 and 63.
431
  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
432
  *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
433
  *         of 2 MHz to limit PLL jitter.
434
  *  
435
  * @param  PLLN: specifies the multiplication factor for PLL VCO output clock
436
  *          This parameter must be a number between 192 and 432.
437
  * @note   You have to set the PLLN parameter correctly to ensure that the VCO
438
  *         output frequency is between 192 and 432 MHz.
439
  *   
440
  * @param  PLLP: specifies the division factor for main system clock (SYSCLK)
441
  *          This parameter must be a number in the range {2, 4, 6, or 8}.
442
  * @note   You have to set the PLLP parameter correctly to not exceed 168 MHz on
443
  *         the System clock frequency.
444
  *  
445
  * @param  PLLQ: specifies the division factor for OTG FS, SDIO and RNG clocks
446
  *          This parameter must be a number between 4 and 15.
447
  * @note   If the USB OTG FS is used in your application, you have to set the
448
  *         PLLQ parameter correctly to have 48 MHz clock for the USB. However,
449
  *         the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
450
  *         correctly.
451
  *   
452
  * @retval None
453
  */
454
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ)
455
{
456
  /* Check the parameters */
457
  assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
458
  assert_param(IS_RCC_PLLM_VALUE(PLLM));
459
  assert_param(IS_RCC_PLLN_VALUE(PLLN));
460
  assert_param(IS_RCC_PLLP_VALUE(PLLP));
461
  assert_param(IS_RCC_PLLQ_VALUE(PLLQ));
462
463
  RCC->PLLCFGR = PLLM | (PLLN << 6) | (((PLLP >> 1) -1) << 16) | (RCC_PLLSource) |
464
                 (PLLQ << 24);
465
}
466
467
/**
468
  * @brief  Enables or disables the main PLL.
469
  * @note   After enabling the main PLL, the application software should wait on 
470
  *         PLLRDY flag to be set indicating that PLL clock is stable and can
471
  *         be used as system clock source.
472
  * @note   The main PLL can not be disabled if it is used as system clock source
473
  * @note   The main PLL is disabled by hardware when entering STOP and STANDBY modes.
474
  * @param  NewState: new state of the main PLL. This parameter can be: ENABLE or DISABLE.
475
  * @retval None
476
  */
477
void RCC_PLLCmd(FunctionalState NewState)
478
{
479
  /* Check the parameters */
480
  assert_param(IS_FUNCTIONAL_STATE(NewState));
481
  *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;
482
}
483
484
/**
485
  * @brief  Configures the PLLI2S clock multiplication and division factors.
486
  *  
487
  * @note   This function must be used only when the PLLI2S is disabled.
488
  * @note   PLLI2S clock source is common with the main PLL (configured in 
489
  *         RCC_PLLConfig function )  
490
  *             
491
  * @param  PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock
492
  *          This parameter must be a number between 192 and 432.
493
  * @note   You have to set the PLLI2SN parameter correctly to ensure that the VCO 
494
  *         output frequency is between 192 and 432 MHz.
495
  *    
496
  * @param  PLLI2SR: specifies the division factor for I2S clock
497
  *          This parameter must be a number between 2 and 7.
498
  * @note   You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
499
  *         on the I2S clock frequency.
500
  *   
501
  * @retval None
502
  */
503
void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR)
504
{
505
  /* Check the parameters */
506
  assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN));
507
  assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SR));
508
509
  RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SR << 28);
510
}
511
512
/**
513
  * @brief  Enables or disables the PLLI2S. 
514
  * @note   The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.  
515
  * @param  NewState: new state of the PLLI2S. This parameter can be: ENABLE or DISABLE.
516
  * @retval None
517
  */
518
void RCC_PLLI2SCmd(FunctionalState NewState)
519
{
520
  /* Check the parameters */
521
  assert_param(IS_FUNCTIONAL_STATE(NewState));
522
  *(__IO uint32_t *) CR_PLLI2SON_BB = (uint32_t)NewState;
523
}
524
525
/**
526
  * @brief  Enables or disables the Clock Security System.
527
  * @note   If a failure is detected on the HSE oscillator clock, this oscillator
528
  *         is automatically disabled and an interrupt is generated to inform the
529
  *         software about the failure (Clock Security System Interrupt, CSSI),
530
  *         allowing the MCU to perform rescue operations. The CSSI is linked to 
531
  *         the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.  
532
  * @param  NewState: new state of the Clock Security System.
533
  *         This parameter can be: ENABLE or DISABLE.
534
  * @retval None
535
  */
536
void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
537
{
538
  /* Check the parameters */
539
  assert_param(IS_FUNCTIONAL_STATE(NewState));
540
  *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;
541
}
542
543
/**
544
  * @brief  Selects the clock source to output on MCO1 pin(PA8).
545
  * @note   PA8 should be configured in alternate function mode.
546
  * @param  RCC_MCO1Source: specifies the clock source to output.
547
  *          This parameter can be one of the following values:
548
  *            @arg RCC_MCO1Source_HSI: HSI clock selected as MCO1 source
549
  *            @arg RCC_MCO1Source_LSE: LSE clock selected as MCO1 source
550
  *            @arg RCC_MCO1Source_HSE: HSE clock selected as MCO1 source
551
  *            @arg RCC_MCO1Source_PLLCLK: main PLL clock selected as MCO1 source
552
  * @param  RCC_MCO1Div: specifies the MCO1 prescaler.
553
  *          This parameter can be one of the following values:
554
  *            @arg RCC_MCO1Div_1: no division applied to MCO1 clock
555
  *            @arg RCC_MCO1Div_2: division by 2 applied to MCO1 clock
556
  *            @arg RCC_MCO1Div_3: division by 3 applied to MCO1 clock
557
  *            @arg RCC_MCO1Div_4: division by 4 applied to MCO1 clock
558
  *            @arg RCC_MCO1Div_5: division by 5 applied to MCO1 clock
559
  * @retval None
560
  */
561
void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div)
562
{
563
  uint32_t tmpreg = 0;
564
  
565
  /* Check the parameters */
566
  assert_param(IS_RCC_MCO1SOURCE(RCC_MCO1Source));
567
  assert_param(IS_RCC_MCO1DIV(RCC_MCO1Div));  
568
569
  tmpreg = RCC->CFGR;
570
571
  /* Clear MCO1[1:0] and MCO1PRE[2:0] bits */
572
  tmpreg &= CFGR_MCO1_RESET_MASK;
573
574
  /* Select MCO1 clock source and prescaler */
575
  tmpreg |= RCC_MCO1Source | RCC_MCO1Div;
576
577
  /* Store the new value */
578
  RCC->CFGR = tmpreg;  
579
}
580
581
/**
582
  * @brief  Selects the clock source to output on MCO2 pin(PC9).
583
  * @note   PC9 should be configured in alternate function mode.
584
  * @param  RCC_MCO2Source: specifies the clock source to output.
585
  *          This parameter can be one of the following values:
586
  *            @arg RCC_MCO2Source_SYSCLK: System clock (SYSCLK) selected as MCO2 source
587
  *            @arg RCC_MCO2Source_PLLI2SCLK: PLLI2S clock selected as MCO2 source
588
  *            @arg RCC_MCO2Source_HSE: HSE clock selected as MCO2 source
589
  *            @arg RCC_MCO2Source_PLLCLK: main PLL clock selected as MCO2 source
590
  * @param  RCC_MCO2Div: specifies the MCO2 prescaler.
591
  *          This parameter can be one of the following values:
592
  *            @arg RCC_MCO2Div_1: no division applied to MCO2 clock
593
  *            @arg RCC_MCO2Div_2: division by 2 applied to MCO2 clock
594
  *            @arg RCC_MCO2Div_3: division by 3 applied to MCO2 clock
595
  *            @arg RCC_MCO2Div_4: division by 4 applied to MCO2 clock
596
  *            @arg RCC_MCO2Div_5: division by 5 applied to MCO2 clock
597
  * @retval None
598
  */
599
void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div)
600
{
601
  uint32_t tmpreg = 0;
602
  
603
  /* Check the parameters */
604
  assert_param(IS_RCC_MCO2SOURCE(RCC_MCO2Source));
605
  assert_param(IS_RCC_MCO2DIV(RCC_MCO2Div));
606
  
607
  tmpreg = RCC->CFGR;
608
  
609
  /* Clear MCO2 and MCO2PRE[2:0] bits */
610
  tmpreg &= CFGR_MCO2_RESET_MASK;
611
612
  /* Select MCO2 clock source and prescaler */
613
  tmpreg |= RCC_MCO2Source | RCC_MCO2Div;
614
615
  /* Store the new value */
616
  RCC->CFGR = tmpreg;  
617
}
618
619
/**
620
  * @}
621
  */
622
623
/** @defgroup RCC_Group2 System AHB and APB busses clocks configuration functions
624
 *  @brief   System, AHB and APB busses clocks configuration functions
625
 *
626
@verbatim   
627
 ===============================================================================
628
      ##### System, AHB and APB busses clocks configuration functions #####
629
 ===============================================================================  
630
    [..]
631
      This section provide functions allowing to configure the System, AHB, APB1 and 
632
      APB2 busses clocks.
633
  
634
      (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
635
          HSE and PLL.
636
          The AHB clock (HCLK) is derived from System clock through configurable 
637
          prescaler and used to clock the CPU, memory and peripherals mapped 
638
          on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived 
639
          from AHB clock through configurable prescalers and used to clock 
640
          the peripherals mapped on these busses. You can use 
641
          "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks.  
642

643
      -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
644
        (+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or
645
             from an external clock mapped on the I2S_CKIN pin. 
646
             You have to use RCC_I2SCLKConfig() function to configure this clock. 
647
        (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
648
             divided by 2 to 31. You have to use RCC_RTCCLKConfig() and RCC_RTCCLKCmd()
649
             functions to configure this clock. 
650
        (+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz
651
             to work correctly, while the SDIO require a frequency equal or lower than
652
             to 48. This clock is derived of the main PLL through PLLQ divider.
653
        (+@) IWDG clock which is always the LSI clock.
654
       
655
      (#) The maximum frequency of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz 
656
          and PCLK1 42 MHz. Depending on the device voltage range, the maximum 
657
          frequency should be adapted accordingly:
658
 +-------------------------------------------------------------------------------------+     
659
 | Latency       |                HCLK clock frequency (MHz)                           |
660
 |               |---------------------------------------------------------------------|     
661
 |               | voltage range  | voltage range  | voltage range   | voltage range   |
662
 |               | 2.7 V - 3.6 V  | 2.4 V - 2.7 V  | 2.1 V - 2.4 V   | 1.8 V - 2.1 V   |
663
 |---------------|----------------|----------------|-----------------|-----------------|              
664
 |0WS(1CPU cycle)|0 < HCLK <= 30  |0 < HCLK <= 24  |0 < HCLK <= 18   |0 < HCLK <= 16   |
665
 |---------------|----------------|----------------|-----------------|-----------------|   
666
 |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |18 < HCLK <= 36  |16 < HCLK <= 32  | 
667
 |---------------|----------------|----------------|-----------------|-----------------|   
668
 |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54  |32 < HCLK <= 48  |
669
 |---------------|----------------|----------------|-----------------|-----------------| 
670
 |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |54 < HCLK <= 72  |48 < HCLK <= 64  |
671
 |---------------|----------------|----------------|-----------------|-----------------| 
672
 |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|72 < HCLK <= 90  |64 < HCLK <= 80  |
673
 |---------------|----------------|----------------|-----------------|-----------------| 
674
 |5WS(6CPU cycle)|120< HCLK <= 168|120< HCLK <= 144|90 < HCLK <= 108 |80 < HCLK <= 96  | 
675
 |---------------|----------------|----------------|-----------------|-----------------| 
676
 |6WS(7CPU cycle)|      NA        |144< HCLK <= 168|108 < HCLK <= 120|96 < HCLK <= 112 | 
677
 |---------------|----------------|----------------|-----------------|-----------------| 
678
 |7WS(8CPU cycle)|      NA        |      NA        |120 < HCLK <= 138|112 < HCLK <= 120| 
679
 +-------------------------------------------------------------------------------------+    
680
      -@- When VOS bits (in PWR_CR register) is reset to 0 , the maximum value of HCLK is 144 MHz.
681
          You can use PWR_MainRegulatorModeConfig() function to set or reset this bit.
682

683
@endverbatim
684
  * @{
685
  */
686
687
/**
688
  * @brief  Configures the system clock (SYSCLK).
689
  * @note   The HSI is used (enabled by hardware) as system clock source after
690
  *         startup from Reset, wake-up from STOP and STANDBY mode, or in case
691
  *         of failure of the HSE used directly or indirectly as system clock
692
  *         (if the Clock Security System CSS is enabled).
693
  * @note   A switch from one clock source to another occurs only if the target
694
  *         clock source is ready (clock stable after startup delay or PLL locked). 
695
  *         If a clock source which is not yet ready is selected, the switch will
696
  *         occur when the clock source will be ready. 
697
  *         You can use RCC_GetSYSCLKSource() function to know which clock is
698
  *         currently used as system clock source. 
699
  * @param  RCC_SYSCLKSource: specifies the clock source used as system clock.
700
  *          This parameter can be one of the following values:
701
  *            @arg RCC_SYSCLKSource_HSI:    HSI selected as system clock source
702
  *            @arg RCC_SYSCLKSource_HSE:    HSE selected as system clock source
703
  *            @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source
704
  * @retval None
705
  */
706
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
707
{
708
  uint32_t tmpreg = 0;
709
710
  /* Check the parameters */
711
  assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
712
713
  tmpreg = RCC->CFGR;
714
715
  /* Clear SW[1:0] bits */
716
  tmpreg &= ~RCC_CFGR_SW;
717
718
  /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
719
  tmpreg |= RCC_SYSCLKSource;
720
721
  /* Store the new value */
722
  RCC->CFGR = tmpreg;
723
}
724
725
/**
726
  * @brief  Returns the clock source used as system clock.
727
  * @param  None
728
  * @retval The clock source used as system clock. The returned value can be one
729
  *         of the following:
730
  *              - 0x00: HSI used as system clock
731
  *              - 0x04: HSE used as system clock
732
  *              - 0x08: PLL used as system clock
733
  */
734
uint8_t RCC_GetSYSCLKSource(void)
735
{
736
  return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS));
737
}
738
739
/**
740
  * @brief  Configures the AHB clock (HCLK).
741
  * @note   Depending on the device voltage range, the software has to set correctly
742
  *         these bits to ensure that HCLK not exceed the maximum allowed frequency
743
  *         (for more details refer to section above
744
  *           "CPU, AHB and APB busses clocks configuration functions")
745
  * @param  RCC_SYSCLK: defines the AHB clock divider. This clock is derived from 
746
  *         the system clock (SYSCLK).
747
  *          This parameter can be one of the following values:
748
  *            @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK
749
  *            @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
750
  *            @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
751
  *            @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
752
  *            @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
753
  *            @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
754
  *            @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
755
  *            @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
756
  *            @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
757
  * @retval None
758
  */
759
void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
760
{
761
  uint32_t tmpreg = 0;
762
  
763
  /* Check the parameters */
764
  assert_param(IS_RCC_HCLK(RCC_SYSCLK));
765
766
  tmpreg = RCC->CFGR;
767
768
  /* Clear HPRE[3:0] bits */
769
  tmpreg &= ~RCC_CFGR_HPRE;
770
771
  /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
772
  tmpreg |= RCC_SYSCLK;
773
774
  /* Store the new value */
775
  RCC->CFGR = tmpreg;
776
}
777
778
779
/**
780
  * @brief  Configures the Low Speed APB clock (PCLK1).
781
  * @param  RCC_HCLK: defines the APB1 clock divider. This clock is derived from 
782
  *         the AHB clock (HCLK).
783
  *          This parameter can be one of the following values:
784
  *            @arg RCC_HCLK_Div1:  APB1 clock = HCLK
785
  *            @arg RCC_HCLK_Div2:  APB1 clock = HCLK/2
786
  *            @arg RCC_HCLK_Div4:  APB1 clock = HCLK/4
787
  *            @arg RCC_HCLK_Div8:  APB1 clock = HCLK/8
788
  *            @arg RCC_HCLK_Div16: APB1 clock = HCLK/16
789
  * @retval None
790
  */
791
void RCC_PCLK1Config(uint32_t RCC_HCLK)
792
{
793
  uint32_t tmpreg = 0;
794
795
  /* Check the parameters */
796
  assert_param(IS_RCC_PCLK(RCC_HCLK));
797
798
  tmpreg = RCC->CFGR;
799
800
  /* Clear PPRE1[2:0] bits */
801
  tmpreg &= ~RCC_CFGR_PPRE1;
802
803
  /* Set PPRE1[2:0] bits according to RCC_HCLK value */
804
  tmpreg |= RCC_HCLK;
805
806
  /* Store the new value */
807
  RCC->CFGR = tmpreg;
808
}
809
810
/**
811
  * @brief  Configures the High Speed APB clock (PCLK2).
812
  * @param  RCC_HCLK: defines the APB2 clock divider. This clock is derived from 
813
  *         the AHB clock (HCLK).
814
  *          This parameter can be one of the following values:
815
  *            @arg RCC_HCLK_Div1:  APB2 clock = HCLK
816
  *            @arg RCC_HCLK_Div2:  APB2 clock = HCLK/2
817
  *            @arg RCC_HCLK_Div4:  APB2 clock = HCLK/4
818
  *            @arg RCC_HCLK_Div8:  APB2 clock = HCLK/8
819
  *            @arg RCC_HCLK_Div16: APB2 clock = HCLK/16
820
  * @retval None
821
  */
822
void RCC_PCLK2Config(uint32_t RCC_HCLK)
823
{
824
  uint32_t tmpreg = 0;
825
826
  /* Check the parameters */
827
  assert_param(IS_RCC_PCLK(RCC_HCLK));
828
829
  tmpreg = RCC->CFGR;
830
831
  /* Clear PPRE2[2:0] bits */
832
  tmpreg &= ~RCC_CFGR_PPRE2;
833
834
  /* Set PPRE2[2:0] bits according to RCC_HCLK value */
835
  tmpreg |= RCC_HCLK << 3;
836
837
  /* Store the new value */
838
  RCC->CFGR = tmpreg;
839
}
840
841
/**
842
  * @brief  Returns the frequencies of different on chip clocks; SYSCLK, HCLK, 
843
  *         PCLK1 and PCLK2.       
844
  * 
845
  * @note   The system frequency computed by this function is not the real 
846
  *         frequency in the chip. It is calculated based on the predefined 
847
  *         constant and the selected clock source:
848
  * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
849
  * @note     If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
850
  * @note     If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) 
851
  *           or HSI_VALUE(*) multiplied/divided by the PLL factors.         
852
  * @note     (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value
853
  *               16 MHz) but the real value may vary depending on the variations
854
  *               in voltage and temperature.
855
  * @note     (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value
856
  *                25 MHz), user has to ensure that HSE_VALUE is same as the real
857
  *                frequency of the crystal used. Otherwise, this function may
858
  *                have wrong result.
859
  *                
860
  * @note   The result of this function could be not correct when using fractional
861
  *         value for HSE crystal.
862
  *   
863
  * @param  RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold
864
  *          the clocks frequencies.
865
  *     
866
  * @note   This function can be used by the user application to compute the 
867
  *         baudrate for the communication peripherals or configure other parameters.
868
  * @note   Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
869
  *         must be called to update the structure's field. Otherwise, any
870
  *         configuration based on this function will be incorrect.
871
  *    
872
  * @retval None
873
  */
874
void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
875
{
876
  uint32_t tmp = 0, presc = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
877
878
  /* Get SYSCLK source -------------------------------------------------------*/
879
  tmp = RCC->CFGR & RCC_CFGR_SWS;
880
881
  switch (tmp)
882
  {
883
    case 0x00:  /* HSI used as system clock source */
884
      RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
885
      break;
886
    case 0x04:  /* HSE used as system clock  source */
887
      RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
888
      break;
889
    case 0x08:  /* PLL used as system clock  source */
890
891
      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
892
         SYSCLK = PLL_VCO / PLLP
893
         */    
894
      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
895
      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
896
      
897
      if (pllsource != 0)
898
      {
899
        /* HSE used as PLL clock source */
900
        pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
901
      }
902
      else
903
      {
904
        /* HSI used as PLL clock source */
905
        pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);      
906
      }
907
908
      pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
909
      RCC_Clocks->SYSCLK_Frequency = pllvco/pllp;
910
      break;
911
    default:
912
      RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
913
      break;
914
  }
915
  /* Compute HCLK, PCLK1 and PCLK2 clocks frequencies ------------------------*/
916
917
  /* Get HCLK prescaler */
918
  tmp = RCC->CFGR & RCC_CFGR_HPRE;
919
  tmp = tmp >> 4;
920
  presc = APBAHBPrescTable[tmp];
921
  /* HCLK clock frequency */
922
  RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
923
924
  /* Get PCLK1 prescaler */
925
  tmp = RCC->CFGR & RCC_CFGR_PPRE1;
926
  tmp = tmp >> 10;
927
  presc = APBAHBPrescTable[tmp];
928
  /* PCLK1 clock frequency */
929
  RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
930
931
  /* Get PCLK2 prescaler */
932
  tmp = RCC->CFGR & RCC_CFGR_PPRE2;
933
  tmp = tmp >> 13;
934
  presc = APBAHBPrescTable[tmp];
935
  /* PCLK2 clock frequency */
936
  RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
937
}
938
939
/**
940
  * @}
941
  */
942
943
/** @defgroup RCC_Group3 Peripheral clocks configuration functions
944
 *  @brief   Peripheral clocks configuration functions 
945
 *
946
@verbatim   
947
 ===============================================================================
948
              ##### Peripheral clocks configuration functions #####
949
 ===============================================================================  
950
    [..] This section provide functions allowing to configure the Peripheral clocks. 
951
  
952
      (#) The RTC clock which is derived from the LSI, LSE or HSE clock divided 
953
          by 2 to 31.
954
     
955
      (#) After restart from Reset or wakeup from STANDBY, all peripherals are off
956
          except internal SRAM, Flash and JTAG. Before to start using a peripheral 
957
          you have to enable its interface clock. You can do this using 
958
          RCC_AHBPeriphClockCmd(), RCC_APB2PeriphClockCmd() and RCC_APB1PeriphClockCmd() functions.
959

960
      (#) To reset the peripherals configuration (to the default state after device reset)
961
          you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and 
962
          RCC_APB1PeriphResetCmd() functions.
963
     
964
      (#) To further reduce power consumption in SLEEP mode the peripheral clocks 
965
          can be disabled prior to executing the WFI or WFE instructions. 
966
          You can do this using RCC_AHBPeriphClockLPModeCmd(), 
967
          RCC_APB2PeriphClockLPModeCmd() and RCC_APB1PeriphClockLPModeCmd() functions.  
968

969
@endverbatim
970
  * @{
971
  */
972
973
/**
974
  * @brief  Configures the RTC clock (RTCCLK).
975
  * @note   As the RTC clock configuration bits are in the Backup domain and write
976
  *         access is denied to this domain after reset, you have to enable write
977
  *         access using PWR_BackupAccessCmd(ENABLE) function before to configure
978
  *         the RTC clock source (to be done once after reset).    
979
  * @note   Once the RTC clock is configured it can't be changed unless the  
980
  *         Backup domain is reset using RCC_BackupResetCmd() function, or by
981
  *         a Power On Reset (POR).
982
  *    
983
  * @param  RCC_RTCCLKSource: specifies the RTC clock source.
984
  *          This parameter can be one of the following values:
985
  *            @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
986
  *            @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
987
  *            @arg RCC_RTCCLKSource_HSE_Divx: HSE clock divided by x selected
988
  *                                            as RTC clock, where x:[2,31]
989
  *  
990
  * @note   If the LSE or LSI is used as RTC clock source, the RTC continues to
991
  *         work in STOP and STANDBY modes, and can be used as wakeup source.
992
  *         However, when the HSE clock is used as RTC clock source, the RTC
993
  *         cannot be used in STOP and STANDBY modes.    
994
  * @note   The maximum input clock frequency for RTC is 1MHz (when using HSE as
995
  *         RTC clock source).
996
  *  
997
  * @retval None
998
  */
999
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
1000
{
1001
  uint32_t tmpreg = 0;
1002
1003
  /* Check the parameters */
1004
  assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
1005
1006
  if ((RCC_RTCCLKSource & 0x00000300) == 0x00000300)
1007
  { /* If HSE is selected as RTC clock source, configure HSE division factor for RTC clock */
1008
    tmpreg = RCC->CFGR;
1009
1010
    /* Clear RTCPRE[4:0] bits */
1011
    tmpreg &= ~RCC_CFGR_RTCPRE;
1012
1013
    /* Configure HSE division factor for RTC clock */
1014
    tmpreg |= (RCC_RTCCLKSource & 0xFFFFCFF);
1015
1016
    /* Store the new value */
1017
    RCC->CFGR = tmpreg;
1018
  }
1019
    
1020
  /* Select the RTC clock source */
1021
  RCC->BDCR |= (RCC_RTCCLKSource & 0x00000FFF);
1022
}
1023
1024
/**
1025
  * @brief  Enables or disables the RTC clock.
1026
  * @note   This function must be used only after the RTC clock source was selected
1027
  *         using the RCC_RTCCLKConfig function.
1028
  * @param  NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE.
1029
  * @retval None
1030
  */
1031
void RCC_RTCCLKCmd(FunctionalState NewState)
1032
{
1033
  /* Check the parameters */
1034
  assert_param(IS_FUNCTIONAL_STATE(NewState));
1035
1036
  *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState;
1037
}
1038
1039
/**
1040
  * @brief  Forces or releases the Backup domain reset.
1041
  * @note   This function resets the RTC peripheral (including the backup registers)
1042
  *         and the RTC clock source selection in RCC_CSR register.
1043
  * @note   The BKPSRAM is not affected by this reset.    
1044
  * @param  NewState: new state of the Backup domain reset.
1045
  *          This parameter can be: ENABLE or DISABLE.
1046
  * @retval None
1047
  */
1048
void RCC_BackupResetCmd(FunctionalState NewState)
1049
{
1050
  /* Check the parameters */
1051
  assert_param(IS_FUNCTIONAL_STATE(NewState));
1052
  *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState;
1053
}
1054
1055
/**
1056
  * @brief  Configures the I2S clock source (I2SCLK).
1057
  * @note   This function must be called before enabling the I2S APB clock.
1058
  * @param  RCC_I2SCLKSource: specifies the I2S clock source.
1059
  *          This parameter can be one of the following values:
1060
  *            @arg RCC_I2S2CLKSource_PLLI2S: PLLI2S clock used as I2S clock source
1061
  *            @arg RCC_I2S2CLKSource_Ext: External clock mapped on the I2S_CKIN pin
1062
  *                                        used as I2S clock source
1063
  * @retval None
1064
  */
1065
void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource)
1066
{
1067
  /* Check the parameters */
1068
  assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource));
1069
1070
  *(__IO uint32_t *) CFGR_I2SSRC_BB = RCC_I2SCLKSource;
1071
}
1072
1073
/**
1074
  * @brief  Configures the Timers clocks prescalers selection.
1075
  * 
1076
  * @note   This feature is only available with STM32F427x/437x Devices.  
1077
  * @param  RCC_TIMCLKPrescaler : specifies the Timers clocks prescalers selection
1078
  *         This parameter can be one of the following values:
1079
  *            @arg RCC_TIMPrescDesactivated: The Timers kernels clocks prescaler is 
1080
  *                 equal to HPRE if PPREx is corresponding to division by 1 or 2, 
1081
  *                 else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to 
1082
  *                 division by 4 or more.
1083
  *                   
1084
  *            @arg RCC_TIMPrescActivated: The Timers kernels clocks prescaler is 
1085
  *                 equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, 
1086
  *                 else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding 
1087
  *                 to division by 8 or more.
1088
  * @retval None
1089
  */
1090
void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler)
1091
{
1092
  /* Check the parameters */
1093
  assert_param(IS_RCC_TIMCLK_PRESCALER(RCC_TIMCLKPrescaler));
1094
1095
  *(__IO uint32_t *) DCKCFGR_TIMPRE_BB = RCC_TIMCLKPrescaler;
1096
  
1097
}
1098
1099
/**
1100
  * @brief  Enables or disables the AHB1 peripheral clock.
1101
  * @note   After reset, the peripheral clock (used for registers read/write access)
1102
  *         is disabled and the application software has to enable this clock before 
1103
  *         using it.   
1104
  * @param  RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock.
1105
  *          This parameter can be any combination of the following values:
1106
  *            @arg RCC_AHB1Periph_GPIOA:       GPIOA clock
1107
  *            @arg RCC_AHB1Periph_GPIOB:       GPIOB clock 
1108
  *            @arg RCC_AHB1Periph_GPIOC:       GPIOC clock
1109
  *            @arg RCC_AHB1Periph_GPIOD:       GPIOD clock
1110
  *            @arg RCC_AHB1Periph_GPIOE:       GPIOE clock
1111
  *            @arg RCC_AHB1Periph_GPIOF:       GPIOF clock
1112
  *            @arg RCC_AHB1Periph_GPIOG:       GPIOG clock
1113
  *            @arg RCC_AHB1Periph_GPIOG:       GPIOG clock
1114
  *            @arg RCC_AHB1Periph_GPIOI:       GPIOI clock 
1115
  *            @arg RCC_AHB1Periph_CRC:         CRC clock
1116
  *            @arg RCC_AHB1Periph_BKPSRAM:     BKPSRAM interface clock
1117
  *            @arg RCC_AHB1Periph_CCMDATARAMEN CCM data RAM interface clock
1118
  *            @arg RCC_AHB1Periph_DMA1:        DMA1 clock
1119
  *            @arg RCC_AHB1Periph_DMA2:        DMA2 clock 
1120
  *            @arg RCC_AHB1Periph_ETH_MAC:     Ethernet MAC clock
1121
  *            @arg RCC_AHB1Periph_ETH_MAC_Tx:  Ethernet Transmission clock
1122
  *            @arg RCC_AHB1Periph_ETH_MAC_Rx:  Ethernet Reception clock
1123
  *            @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock
1124
  *            @arg RCC_AHB1Periph_OTG_HS:      USB OTG HS clock
1125
  *            @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock
1126
  * @param  NewState: new state of the specified peripheral clock.
1127
  *          This parameter can be: ENABLE or DISABLE.
1128
  * @retval None
1129
  */
1130
void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
1131
{
1132
  /* Check the parameters */
1133
  assert_param(IS_RCC_AHB1_CLOCK_PERIPH(RCC_AHB1Periph));
1134
1135
  assert_param(IS_FUNCTIONAL_STATE(NewState));
1136
  if (NewState != DISABLE)
1137
  {
1138
    RCC->AHB1ENR |= RCC_AHB1Periph;
1139
  }
1140
  else
1141
  {
1142
    RCC->AHB1ENR &= ~RCC_AHB1Periph;
1143
  }
1144
}
1145
1146
/**
1147
  * @brief  Enables or disables the AHB2 peripheral clock.
1148
  * @note   After reset, the peripheral clock (used for registers read/write access)
1149
  *         is disabled and the application software has to enable this clock before 
1150
  *         using it. 
1151
  * @param  RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock.
1152
  *          This parameter can be any combination of the following values:
1153
  *            @arg RCC_AHB2Periph_DCMI:   DCMI clock
1154
  *            @arg RCC_AHB2Periph_CRYP:   CRYP clock
1155
  *            @arg RCC_AHB2Periph_HASH:   HASH clock
1156
  *            @arg RCC_AHB2Periph_RNG:    RNG clock
1157
  *            @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock
1158
  * @param  NewState: new state of the specified peripheral clock.
1159
  *          This parameter can be: ENABLE or DISABLE.
1160
  * @retval None
1161
  */
1162
void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
1163
{
1164
  /* Check the parameters */
1165
  assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
1166
  assert_param(IS_FUNCTIONAL_STATE(NewState));
1167
1168
  if (NewState != DISABLE)
1169
  {
1170
    RCC->AHB2ENR |= RCC_AHB2Periph;
1171
  }
1172
  else
1173
  {
1174
    RCC->AHB2ENR &= ~RCC_AHB2Periph;
1175
  }
1176
}
1177
1178
/**
1179
  * @brief  Enables or disables the AHB3 peripheral clock.
1180
  * @note   After reset, the peripheral clock (used for registers read/write access)
1181
  *         is disabled and the application software has to enable this clock before 
1182
  *         using it. 
1183
  * @param  RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock.
1184
  *          This parameter must be: RCC_AHB3Periph_FSMC
1185
  *                                  
1186
  * @param  NewState: new state of the specified peripheral clock.
1187
  *          This parameter can be: ENABLE or DISABLE.
1188
  * @retval None
1189
  */
1190
void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
1191
{
1192
  /* Check the parameters */
1193
  assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));  
1194
  assert_param(IS_FUNCTIONAL_STATE(NewState));
1195
1196
  if (NewState != DISABLE)
1197
  {
1198
    RCC->AHB3ENR |= RCC_AHB3Periph;
1199
  }
1200
  else
1201
  {
1202
    RCC->AHB3ENR &= ~RCC_AHB3Periph;
1203
  }
1204
}
1205
1206
/**
1207
  * @brief  Enables or disables the Low Speed APB (APB1) peripheral clock.
1208
  * @note   After reset, the peripheral clock (used for registers read/write access)
1209
  *         is disabled and the application software has to enable this clock before 
1210
  *         using it. 
1211
  * @param  RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
1212
  *          This parameter can be any combination of the following values:
1213
  *            @arg RCC_APB1Periph_TIM2:   TIM2 clock
1214
  *            @arg RCC_APB1Periph_TIM3:   TIM3 clock
1215
  *            @arg RCC_APB1Periph_TIM4:   TIM4 clock
1216
  *            @arg RCC_APB1Periph_TIM5:   TIM5 clock
1217
  *            @arg RCC_APB1Periph_TIM6:   TIM6 clock
1218
  *            @arg RCC_APB1Periph_TIM7:   TIM7 clock
1219
  *            @arg RCC_APB1Periph_TIM12:  TIM12 clock
1220
  *            @arg RCC_APB1Periph_TIM13:  TIM13 clock
1221
  *            @arg RCC_APB1Periph_TIM14:  TIM14 clock
1222
  *            @arg RCC_APB1Periph_WWDG:   WWDG clock
1223
  *            @arg RCC_APB1Periph_SPI2:   SPI2 clock
1224
  *            @arg RCC_APB1Periph_SPI3:   SPI3 clock
1225
  *            @arg RCC_APB1Periph_USART2: USART2 clock
1226
  *            @arg RCC_APB1Periph_USART3: USART3 clock
1227
  *            @arg RCC_APB1Periph_UART4:  UART4 clock
1228
  *            @arg RCC_APB1Periph_UART5:  UART5 clock
1229
  *            @arg RCC_APB1Periph_I2C1:   I2C1 clock
1230
  *            @arg RCC_APB1Periph_I2C2:   I2C2 clock
1231
  *            @arg RCC_APB1Periph_I2C3:   I2C3 clock
1232
  *            @arg RCC_APB1Periph_CAN1:   CAN1 clock
1233
  *            @arg RCC_APB1Periph_CAN2:   CAN2 clock
1234
  *            @arg RCC_APB1Periph_PWR:    PWR clock
1235
  *            @arg RCC_APB1Periph_DAC:    DAC clock
1236
  *            @arg RCC_APB1Periph_UART7:  UART7 clock
1237
  *            @arg RCC_APB1Periph_UART8:  UART8 clock
1238
  * @param  NewState: new state of the specified peripheral clock.
1239
  *          This parameter can be: ENABLE or DISABLE.
1240
  * @retval None
1241
  */
1242
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
1243
{
1244
  /* Check the parameters */
1245
  assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));  
1246
  assert_param(IS_FUNCTIONAL_STATE(NewState));
1247
1248
  if (NewState != DISABLE)
1249
  {
1250
    RCC->APB1ENR |= RCC_APB1Periph;
1251
  }
1252
  else
1253
  {
1254
    RCC->APB1ENR &= ~RCC_APB1Periph;
1255
  }
1256
}
1257
1258
/**
1259
  * @brief  Enables or disables the High Speed APB (APB2) peripheral clock.
1260
  * @note   After reset, the peripheral clock (used for registers read/write access)
1261
  *         is disabled and the application software has to enable this clock before 
1262
  *         using it.
1263
  * @param  RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
1264
  *          This parameter can be any combination of the following values:
1265
  *            @arg RCC_APB2Periph_TIM1:   TIM1 clock
1266
  *            @arg RCC_APB2Periph_TIM8:   TIM8 clock
1267
  *            @arg RCC_APB2Periph_USART1: USART1 clock
1268
  *            @arg RCC_APB2Periph_USART6: USART6 clock
1269
  *            @arg RCC_APB2Periph_ADC1:   ADC1 clock
1270
  *            @arg RCC_APB2Periph_ADC2:   ADC2 clock
1271
  *            @arg RCC_APB2Periph_ADC3:   ADC3 clock
1272
  *            @arg RCC_APB2Periph_SDIO:   SDIO clock
1273
  *            @arg RCC_APB2Periph_SPI1:   SPI1 clock
1274
  *            @arg RCC_APB2Periph_SPI4:   SPI4 clock
1275
  *            @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
1276
  *            @arg RCC_APB2Periph_TIM9:   TIM9 clock
1277
  *            @arg RCC_APB2Periph_TIM10:  TIM10 clock
1278
  *            @arg RCC_APB2Periph_TIM11:  TIM11 clock
1279
  *            @arg RCC_APB2Periph_SPI5:   SPI5 clock
1280
  *            @arg RCC_APB2Periph_SPI6:   SPI6 clock
1281
  * @param  NewState: new state of the specified peripheral clock.
1282
  *          This parameter can be: ENABLE or DISABLE.
1283
  * @retval None
1284
  */
1285
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
1286
{
1287
  /* Check the parameters */
1288
  assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
1289
  assert_param(IS_FUNCTIONAL_STATE(NewState));
1290
1291
  if (NewState != DISABLE)
1292
  {
1293
    RCC->APB2ENR |= RCC_APB2Periph;
1294
  }
1295
  else
1296
  {
1297
    RCC->APB2ENR &= ~RCC_APB2Periph;
1298
  }
1299
}
1300
1301
/**
1302
  * @brief  Forces or releases AHB1 peripheral reset.
1303
  * @param  RCC_AHB1Periph: specifies the AHB1 peripheral to reset.
1304
  *          This parameter can be any combination of the following values:
1305
  *            @arg RCC_AHB1Periph_GPIOA:   GPIOA clock
1306
  *            @arg RCC_AHB1Periph_GPIOB:   GPIOB clock 
1307
  *            @arg RCC_AHB1Periph_GPIOC:   GPIOC clock
1308
  *            @arg RCC_AHB1Periph_GPIOD:   GPIOD clock
1309
  *            @arg RCC_AHB1Periph_GPIOE:   GPIOE clock
1310
  *            @arg RCC_AHB1Periph_GPIOF:   GPIOF clock
1311
  *            @arg RCC_AHB1Periph_GPIOG:   GPIOG clock
1312
  *            @arg RCC_AHB1Periph_GPIOG:   GPIOG clock
1313
  *            @arg RCC_AHB1Periph_GPIOI:   GPIOI clock  
1314
  *            @arg RCC_AHB1Periph_CRC:     CRC clock
1315
  *            @arg RCC_AHB1Periph_DMA1:    DMA1 clock
1316
  *            @arg RCC_AHB1Periph_DMA2:    DMA2 clock 
1317
  *            @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
1318
  *            @arg RCC_AHB1Periph_OTG_HS:  USB OTG HS clock
1319
  *                  
1320
  * @param  NewState: new state of the specified peripheral reset.
1321
  *          This parameter can be: ENABLE or DISABLE.
1322
  * @retval None
1323
  */
1324
void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
1325
{
1326
  /* Check the parameters */
1327
  assert_param(IS_RCC_AHB1_RESET_PERIPH(RCC_AHB1Periph));
1328
  assert_param(IS_FUNCTIONAL_STATE(NewState));
1329
1330
  if (NewState != DISABLE)
1331
  {
1332
    RCC->AHB1RSTR |= RCC_AHB1Periph;
1333
  }
1334
  else
1335
  {
1336
    RCC->AHB1RSTR &= ~RCC_AHB1Periph;
1337
  }
1338
}
1339
1340
/**
1341
  * @brief  Forces or releases AHB2 peripheral reset.
1342
  * @param  RCC_AHB2Periph: specifies the AHB2 peripheral to reset.
1343
  *          This parameter can be any combination of the following values:
1344
  *            @arg RCC_AHB2Periph_DCMI:   DCMI clock
1345
  *            @arg RCC_AHB2Periph_CRYP:   CRYP clock
1346
  *            @arg RCC_AHB2Periph_HASH:   HASH clock
1347
  *            @arg RCC_AHB2Periph_RNG:    RNG clock
1348
  *            @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock
1349
  * @param  NewState: new state of the specified peripheral reset.
1350
  *          This parameter can be: ENABLE or DISABLE.
1351
  * @retval None
1352
  */
1353
void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
1354
{
1355
  /* Check the parameters */
1356
  assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
1357
  assert_param(IS_FUNCTIONAL_STATE(NewState));
1358
1359
  if (NewState != DISABLE)
1360
  {
1361
    RCC->AHB2RSTR |= RCC_AHB2Periph;
1362
  }
1363
  else
1364
  {
1365
    RCC->AHB2RSTR &= ~RCC_AHB2Periph;
1366
  }
1367
}
1368
1369
/**
1370
  * @brief  Forces or releases AHB3 peripheral reset.
1371
  * @param  RCC_AHB3Periph: specifies the AHB3 peripheral to reset.
1372
  *          This parameter must be: RCC_AHB3Periph_FSMC
1373
  *                                   
1374
  * @param  NewState: new state of the specified peripheral reset.
1375
  *          This parameter can be: ENABLE or DISABLE.
1376
  * @retval None
1377
  */
1378
void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
1379
{
1380
  /* Check the parameters */
1381
  assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));
1382
  assert_param(IS_FUNCTIONAL_STATE(NewState));
1383
1384
  if (NewState != DISABLE)
1385
  {
1386
    RCC->AHB3RSTR |= RCC_AHB3Periph;
1387
  }
1388
  else
1389
  {
1390
    RCC->AHB3RSTR &= ~RCC_AHB3Periph;
1391
  }
1392
}
1393
1394
/**
1395
  * @brief  Forces or releases Low Speed APB (APB1) peripheral reset.
1396
  * @param  RCC_APB1Periph: specifies the APB1 peripheral to reset.
1397
  *          This parameter can be any combination of the following values:
1398
  *            @arg RCC_APB1Periph_TIM2:   TIM2 clock
1399
  *            @arg RCC_APB1Periph_TIM3:   TIM3 clock
1400
  *            @arg RCC_APB1Periph_TIM4:   TIM4 clock
1401
  *            @arg RCC_APB1Periph_TIM5:   TIM5 clock
1402
  *            @arg RCC_APB1Periph_TIM6:   TIM6 clock
1403
  *            @arg RCC_APB1Periph_TIM7:   TIM7 clock
1404
  *            @arg RCC_APB1Periph_TIM12:  TIM12 clock
1405
  *            @arg RCC_APB1Periph_TIM13:  TIM13 clock
1406
  *            @arg RCC_APB1Periph_TIM14:  TIM14 clock
1407
  *            @arg RCC_APB1Periph_WWDG:   WWDG clock
1408
  *            @arg RCC_APB1Periph_SPI2:   SPI2 clock
1409
  *            @arg RCC_APB1Periph_SPI3:   SPI3 clock
1410
  *            @arg RCC_APB1Periph_USART2: USART2 clock
1411
  *            @arg RCC_APB1Periph_USART3: USART3 clock
1412
  *            @arg RCC_APB1Periph_UART4:  UART4 clock
1413
  *            @arg RCC_APB1Periph_UART5:  UART5 clock
1414
  *            @arg RCC_APB1Periph_I2C1:   I2C1 clock
1415
  *            @arg RCC_APB1Periph_I2C2:   I2C2 clock
1416
  *            @arg RCC_APB1Periph_I2C3:   I2C3 clock
1417
  *            @arg RCC_APB1Periph_CAN1:   CAN1 clock
1418
  *            @arg RCC_APB1Periph_CAN2:   CAN2 clock
1419
  *            @arg RCC_APB1Periph_PWR:    PWR clock
1420
  *            @arg RCC_APB1Periph_DAC:    DAC clock
1421
  *            @arg RCC_APB1Periph_UART7:  UART7 clock
1422
  *            @arg RCC_APB1Periph_UART8:  UART8 clock  
1423
  * @param  NewState: new state of the specified peripheral reset.
1424
  *          This parameter can be: ENABLE or DISABLE.
1425
  * @retval None
1426
  */
1427
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
1428
{
1429
  /* Check the parameters */
1430
  assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
1431
  assert_param(IS_FUNCTIONAL_STATE(NewState));
1432
  if (NewState != DISABLE)
1433
  {
1434
    RCC->APB1RSTR |= RCC_APB1Periph;
1435
  }
1436
  else
1437
  {
1438
    RCC->APB1RSTR &= ~RCC_APB1Periph;
1439
  }
1440
}
1441
1442
/**
1443
  * @brief  Forces or releases High Speed APB (APB2) peripheral reset.
1444
  * @param  RCC_APB2Periph: specifies the APB2 peripheral to reset.
1445
  *          This parameter can be any combination of the following values:
1446
  *            @arg RCC_APB2Periph_TIM1:   TIM1 clock
1447
  *            @arg RCC_APB2Periph_TIM8:   TIM8 clock
1448
  *            @arg RCC_APB2Periph_USART1: USART1 clock
1449
  *            @arg RCC_APB2Periph_USART6: USART6 clock
1450
  *            @arg RCC_APB2Periph_ADC1:   ADC1 clock
1451
  *            @arg RCC_APB2Periph_ADC2:   ADC2 clock
1452
  *            @arg RCC_APB2Periph_ADC3:   ADC3 clock
1453
  *            @arg RCC_APB2Periph_SDIO:   SDIO clock
1454
  *            @arg RCC_APB2Periph_SPI1:   SPI1 clock
1455
  *            @arg RCC_APB2Periph_SPI4:   SPI4 clock  
1456
  *            @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
1457
  *            @arg RCC_APB2Periph_TIM9:   TIM9 clock
1458
  *            @arg RCC_APB2Periph_TIM10:  TIM10 clock
1459
  *            @arg RCC_APB2Periph_TIM11:  TIM11 clock
1460
  *            @arg RCC_APB2Periph_SPI5:   SPI5 clock
1461
  *            @arg RCC_APB2Periph_SPI6:   SPI6 clock 
1462
  * @param  NewState: new state of the specified peripheral reset.
1463
  *          This parameter can be: ENABLE or DISABLE.
1464
  * @retval None
1465
  */
1466
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
1467
{
1468
  /* Check the parameters */
1469
  assert_param(IS_RCC_APB2_RESET_PERIPH(RCC_APB2Periph));
1470
  assert_param(IS_FUNCTIONAL_STATE(NewState));
1471
  if (NewState != DISABLE)
1472
  {
1473
    RCC->APB2RSTR |= RCC_APB2Periph;
1474
  }
1475
  else
1476
  {
1477
    RCC->APB2RSTR &= ~RCC_APB2Periph;
1478
  }
1479
}
1480
1481
/**
1482
  * @brief  Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode.
1483
  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
1484
  *         power consumption.
1485
  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
1486
  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
1487
  * @param  RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock.
1488
  *          This parameter can be any combination of the following values:
1489
  *            @arg RCC_AHB1Periph_GPIOA:       GPIOA clock
1490
  *            @arg RCC_AHB1Periph_GPIOB:       GPIOB clock 
1491
  *            @arg RCC_AHB1Periph_GPIOC:       GPIOC clock
1492
  *            @arg RCC_AHB1Periph_GPIOD:       GPIOD clock
1493
  *            @arg RCC_AHB1Periph_GPIOE:       GPIOE clock
1494
  *            @arg RCC_AHB1Periph_GPIOF:       GPIOF clock
1495
  *            @arg RCC_AHB1Periph_GPIOG:       GPIOG clock
1496
  *            @arg RCC_AHB1Periph_GPIOG:       GPIOG clock
1497
  *            @arg RCC_AHB1Periph_GPIOI:       GPIOI clock 
1498
  *            @arg RCC_AHB1Periph_CRC:         CRC clock
1499
  *            @arg RCC_AHB1Periph_BKPSRAM:     BKPSRAM interface clock
1500
  *            @arg RCC_AHB1Periph_DMA1:        DMA1 clock
1501
  *            @arg RCC_AHB1Periph_DMA2:        DMA2 clock
1502
  *            @arg RCC_AHB1Periph_ETH_MAC:     Ethernet MAC clock
1503
  *            @arg RCC_AHB1Periph_ETH_MAC_Tx:  Ethernet Transmission clock
1504
  *            @arg RCC_AHB1Periph_ETH_MAC_Rx:  Ethernet Reception clock
1505
  *            @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock
1506
  *            @arg RCC_AHB1Periph_OTG_HS:      USB OTG HS clock
1507
  *            @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock
1508
  * @param  NewState: new state of the specified peripheral clock.
1509
  *          This parameter can be: ENABLE or DISABLE.
1510
  * @retval None
1511
  */
1512
void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
1513
{
1514
  /* Check the parameters */
1515
  assert_param(IS_RCC_AHB1_LPMODE_PERIPH(RCC_AHB1Periph));
1516
  assert_param(IS_FUNCTIONAL_STATE(NewState));
1517
  if (NewState != DISABLE)
1518
  {
1519
    RCC->AHB1LPENR |= RCC_AHB1Periph;
1520
  }
1521
  else
1522
  {
1523
    RCC->AHB1LPENR &= ~RCC_AHB1Periph;
1524
  }
1525
}
1526
1527
/**
1528
  * @brief  Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode.
1529
  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
1530
  *           power consumption.
1531
  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
1532
  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
1533
  * @param  RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock.
1534
  *          This parameter can be any combination of the following values:
1535
  *            @arg RCC_AHB2Periph_DCMI:   DCMI clock
1536
  *            @arg RCC_AHB2Periph_CRYP:   CRYP clock
1537
  *            @arg RCC_AHB2Periph_HASH:   HASH clock
1538
  *            @arg RCC_AHB2Periph_RNG:    RNG clock
1539
  *            @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock  
1540
  * @param  NewState: new state of the specified peripheral clock.
1541
  *          This parameter can be: ENABLE or DISABLE.
1542
  * @retval None
1543
  */
1544
void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
1545
{
1546
  /* Check the parameters */
1547
  assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
1548
  assert_param(IS_FUNCTIONAL_STATE(NewState));
1549
  if (NewState != DISABLE)
1550
  {
1551
    RCC->AHB2LPENR |= RCC_AHB2Periph;
1552
  }
1553
  else
1554
  {
1555
    RCC->AHB2LPENR &= ~RCC_AHB2Periph;
1556
  }
1557
}
1558
1559
/**
1560
  * @brief  Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode.
1561
  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
1562
  *         power consumption.
1563
  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
1564
  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
1565
  * @param  RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock.
1566
  *          This parameter must be: RCC_AHB3Periph_FSMC
1567
  *                                  
1568
  * @param  NewState: new state of the specified peripheral clock.
1569
  *          This parameter can be: ENABLE or DISABLE.
1570
  * @retval None
1571
  */
1572
void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
1573
{
1574
  /* Check the parameters */
1575
  assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));
1576
  assert_param(IS_FUNCTIONAL_STATE(NewState));
1577
  if (NewState != DISABLE)
1578
  {
1579
    RCC->AHB3LPENR |= RCC_AHB3Periph;
1580
  }
1581
  else
1582
  {
1583
    RCC->AHB3LPENR &= ~RCC_AHB3Periph;
1584
  }
1585
}
1586
1587
/**
1588
  * @brief  Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode.
1589
  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
1590
  *         power consumption.
1591
  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
1592
  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
1593
  * @param  RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
1594
  *          This parameter can be any combination of the following values:
1595
  *            @arg RCC_APB1Periph_TIM2:   TIM2 clock
1596
  *            @arg RCC_APB1Periph_TIM3:   TIM3 clock
1597
  *            @arg RCC_APB1Periph_TIM4:   TIM4 clock
1598
  *            @arg RCC_APB1Periph_TIM5:   TIM5 clock
1599
  *            @arg RCC_APB1Periph_TIM6:   TIM6 clock
1600
  *            @arg RCC_APB1Periph_TIM7:   TIM7 clock
1601
  *            @arg RCC_APB1Periph_TIM12:  TIM12 clock
1602
  *            @arg RCC_APB1Periph_TIM13:  TIM13 clock
1603
  *            @arg RCC_APB1Periph_TIM14:  TIM14 clock
1604
  *            @arg RCC_APB1Periph_WWDG:   WWDG clock
1605
  *            @arg RCC_APB1Periph_SPI2:   SPI2 clock
1606
  *            @arg RCC_APB1Periph_SPI3:   SPI3 clock
1607
  *            @arg RCC_APB1Periph_USART2: USART2 clock
1608
  *            @arg RCC_APB1Periph_USART3: USART3 clock
1609
  *            @arg RCC_APB1Periph_UART4:  UART4 clock
1610
  *            @arg RCC_APB1Periph_UART5:  UART5 clock
1611
  *            @arg RCC_APB1Periph_I2C1:   I2C1 clock
1612
  *            @arg RCC_APB1Periph_I2C2:   I2C2 clock
1613
  *            @arg RCC_APB1Periph_I2C3:   I2C3 clock
1614
  *            @arg RCC_APB1Periph_CAN1:   CAN1 clock
1615
  *            @arg RCC_APB1Periph_CAN2:   CAN2 clock
1616
  *            @arg RCC_APB1Periph_PWR:    PWR clock
1617
  *            @arg RCC_APB1Periph_DAC:    DAC clock
1618
  *            @arg RCC_APB1Periph_UART7:  UART7 clock
1619
  *            @arg RCC_APB1Periph_UART8:  UART8 clock
1620
  * @param  NewState: new state of the specified peripheral clock.
1621
  *          This parameter can be: ENABLE or DISABLE.
1622
  * @retval None
1623
  */
1624
void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
1625
{
1626
  /* Check the parameters */
1627
  assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
1628
  assert_param(IS_FUNCTIONAL_STATE(NewState));
1629
  if (NewState != DISABLE)
1630
  {
1631
    RCC->APB1LPENR |= RCC_APB1Periph;
1632
  }
1633
  else
1634
  {
1635
    RCC->APB1LPENR &= ~RCC_APB1Periph;
1636
  }
1637
}
1638
1639
/**
1640
  * @brief  Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode.
1641
  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
1642
  *         power consumption.
1643
  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
1644
  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
1645
  * @param  RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
1646
  *          This parameter can be any combination of the following values:
1647
  *            @arg RCC_APB2Periph_TIM1:   TIM1 clock
1648
  *            @arg RCC_APB2Periph_TIM8:   TIM8 clock
1649
  *            @arg RCC_APB2Periph_USART1: USART1 clock
1650
  *            @arg RCC_APB2Periph_USART6: USART6 clock
1651
  *            @arg RCC_APB2Periph_ADC1:   ADC1 clock
1652
  *            @arg RCC_APB2Periph_ADC2:   ADC2 clock
1653
  *            @arg RCC_APB2Periph_ADC3:   ADC3 clock
1654
  *            @arg RCC_APB2Periph_SDIO:   SDIO clock
1655
  *            @arg RCC_APB2Periph_SPI1:   SPI1 clock
1656
  *            @arg RCC_APB2Periph_SPI4:   SPI4 clock
1657
  *            @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
1658
  *            @arg RCC_APB2Periph_TIM9:   TIM9 clock
1659
  *            @arg RCC_APB2Periph_TIM10:  TIM10 clock
1660
  *            @arg RCC_APB2Periph_TIM11:  TIM11 clock
1661
  *            @arg RCC_APB2Periph_SPI5:   SPI5 clock
1662
  *            @arg RCC_APB2Periph_SPI6:   SPI6 clock  
1663
  * @param  NewState: new state of the specified peripheral clock.
1664
  *          This parameter can be: ENABLE or DISABLE.
1665
  * @retval None
1666
  */
1667
void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
1668
{
1669
  /* Check the parameters */
1670
  assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
1671
  assert_param(IS_FUNCTIONAL_STATE(NewState));
1672
  if (NewState != DISABLE)
1673
  {
1674
    RCC->APB2LPENR |= RCC_APB2Periph;
1675
  }
1676
  else
1677
  {
1678
    RCC->APB2LPENR &= ~RCC_APB2Periph;
1679
  }
1680
}
1681
1682
/**
1683
  * @}
1684
  */
1685
1686
/** @defgroup RCC_Group4 Interrupts and flags management functions
1687
 *  @brief   Interrupts and flags management functions 
1688
 *
1689
@verbatim   
1690
 ===============================================================================
1691
                ##### Interrupts and flags management functions #####
1692
 ===============================================================================  
1693

1694
@endverbatim
1695
  * @{
1696
  */
1697
1698
/**
1699
  * @brief  Enables or disables the specified RCC interrupts.
1700
  * @param  RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
1701
  *          This parameter can be any combination of the following values:
1702
  *            @arg RCC_IT_LSIRDY: LSI ready interrupt
1703
  *            @arg RCC_IT_LSERDY: LSE ready interrupt
1704
  *            @arg RCC_IT_HSIRDY: HSI ready interrupt
1705
  *            @arg RCC_IT_HSERDY: HSE ready interrupt
1706
  *            @arg RCC_IT_PLLRDY: main PLL ready interrupt
1707
  *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
1708
  *              
1709
  * @param  NewState: new state of the specified RCC interrupts.
1710
  *          This parameter can be: ENABLE or DISABLE.
1711
  * @retval None
1712
  */
1713
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
1714
{
1715
  /* Check the parameters */
1716
  assert_param(IS_RCC_IT(RCC_IT));
1717
  assert_param(IS_FUNCTIONAL_STATE(NewState));
1718
  if (NewState != DISABLE)
1719
  {
1720
    /* Perform Byte access to RCC_CIR[14:8] bits to enable the selected interrupts */
1721
    *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;
1722
  }
1723
  else
1724
  {
1725
    /* Perform Byte access to RCC_CIR[14:8] bits to disable the selected interrupts */
1726
    *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
1727
  }
1728
}
1729
1730
/**
1731
  * @brief  Checks whether the specified RCC flag is set or not.
1732
  * @param  RCC_FLAG: specifies the flag to check.
1733
  *          This parameter can be one of the following values:
1734
  *            @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
1735
  *            @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
1736
  *            @arg RCC_FLAG_PLLRDY: main PLL clock ready
1737
  *            @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready
1738
  *            @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
1739
  *            @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
1740
  *            @arg RCC_FLAG_BORRST: POR/PDR or BOR reset
1741
  *            @arg RCC_FLAG_PINRST: Pin reset
1742
  *            @arg RCC_FLAG_PORRST: POR/PDR reset
1743
  *            @arg RCC_FLAG_SFTRST: Software reset
1744
  *            @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
1745
  *            @arg RCC_FLAG_WWDGRST: Window Watchdog reset
1746
  *            @arg RCC_FLAG_LPWRRST: Low Power reset
1747
  * @retval The new state of RCC_FLAG (SET or RESET).
1748
  */
1749
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
1750
{
1751
  uint32_t tmp = 0;
1752
  uint32_t statusreg = 0;
1753
  FlagStatus bitstatus = RESET;
1754
1755
  /* Check the parameters */
1756
  assert_param(IS_RCC_FLAG(RCC_FLAG));
1757
1758
  /* Get the RCC register index */
1759
  tmp = RCC_FLAG >> 5;
1760
  if (tmp == 1)               /* The flag to check is in CR register */
1761
  {
1762
    statusreg = RCC->CR;
1763
  }
1764
  else if (tmp == 2)          /* The flag to check is in BDCR register */
1765
  {
1766
    statusreg = RCC->BDCR;
1767
  }
1768
  else                       /* The flag to check is in CSR register */
1769
  {
1770
    statusreg = RCC->CSR;
1771
  }
1772
1773
  /* Get the flag position */
1774
  tmp = RCC_FLAG & FLAG_MASK;
1775
  if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
1776
  {
1777
    bitstatus = SET;
1778
  }
1779
  else
1780
  {
1781
    bitstatus = RESET;
1782
  }
1783
  /* Return the flag status */
1784
  return bitstatus;
1785
}
1786
1787
/**
1788
  * @brief  Clears the RCC reset flags.
1789
  *         The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST,  RCC_FLAG_SFTRST,
1790
  *         RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
1791
  * @param  None
1792
  * @retval None
1793
  */
1794
void RCC_ClearFlag(void)
1795
{
1796
  /* Set RMVF bit to clear the reset flags */
1797
  RCC->CSR |= RCC_CSR_RMVF;
1798
}
1799
1800
/**
1801
  * @brief  Checks whether the specified RCC interrupt has occurred or not.
1802
  * @param  RCC_IT: specifies the RCC interrupt source to check.
1803
  *          This parameter can be one of the following values:
1804
  *            @arg RCC_IT_LSIRDY: LSI ready interrupt
1805
  *            @arg RCC_IT_LSERDY: LSE ready interrupt
1806
  *            @arg RCC_IT_HSIRDY: HSI ready interrupt
1807
  *            @arg RCC_IT_HSERDY: HSE ready interrupt
1808
  *            @arg RCC_IT_PLLRDY: main PLL ready interrupt
1809
  *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt             
1810
  *            @arg RCC_IT_CSS: Clock Security System interrupt
1811
  * @retval The new state of RCC_IT (SET or RESET).
1812
  */
1813
ITStatus RCC_GetITStatus(uint8_t RCC_IT)
1814
{
1815
  ITStatus bitstatus = RESET;
1816
1817
  /* Check the parameters */
1818
  assert_param(IS_RCC_GET_IT(RCC_IT));
1819
1820
  /* Check the status of the specified RCC interrupt */
1821
  if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
1822
  {
1823
    bitstatus = SET;
1824
  }
1825
  else
1826
  {
1827
    bitstatus = RESET;
1828
  }
1829
  /* Return the RCC_IT status */
1830
  return  bitstatus;
1831
}
1832
1833
/**
1834
  * @brief  Clears the RCC's interrupt pending bits.
1835
  * @param  RCC_IT: specifies the interrupt pending bit to clear.
1836
  *          This parameter can be any combination of the following values:
1837
  *            @arg RCC_IT_LSIRDY: LSI ready interrupt
1838
  *            @arg RCC_IT_LSERDY: LSE ready interrupt
1839
  *            @arg RCC_IT_HSIRDY: HSI ready interrupt
1840
  *            @arg RCC_IT_HSERDY: HSE ready interrupt
1841
  *            @arg RCC_IT_PLLRDY: main PLL ready interrupt
1842
  *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt  
1843
  *            @arg RCC_IT_CSS: Clock Security System interrupt
1844
  * @retval None
1845
  */
1846
void RCC_ClearITPendingBit(uint8_t RCC_IT)
1847
{
1848
  /* Check the parameters */
1849
  assert_param(IS_RCC_CLEAR_IT(RCC_IT));
1850
1851
  /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
1852
     pending bits */
1853
  *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;
1854
}
1855
1856
/**
1857
  * @}
1858
  */ 
1859
1860
/**
1861
  * @}
1862
  */ 
1863
1864
/**
1865
  * @}
1866
  */ 
1867
1868
/**
1869
  * @}
1870
  */ 
1871
1872
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/