Statistics
| Branch: | Tag: | Revision:

amiro-blt / Target / Modules / PowerManagement_1-1 / Boot / lib / stdperiphlib / STM32F4xx_StdPeriph_Driver / src / stm32f4xx_syscfg.c @ 367c0652

History | View | Annotate | Download (7.57 KB)

1 69661903 Thomas Schöpping
/**
2
  ******************************************************************************
3
  * @file    stm32f4xx_syscfg.c
4
  * @author  MCD Application Team
5
  * @version V1.1.0
6
  * @date    11-January-2013
7
  * @brief   This file provides firmware functions to manage the SYSCFG peripheral.
8
  *
9
 @verbatim
10
    
11
 ===============================================================================
12
                     ##### How to use this driver #####
13
 ===============================================================================
14
    [..] This driver provides functions for:
15
            
16
       (#) Remapping the memory accessible in the code area using SYSCFG_MemoryRemapConfig()
17
                            
18
       (#) Manage the EXTI lines connection to the GPIOs using SYSCFG_EXTILineConfig()
19
              
20
       (#) Select the ETHERNET media interface (RMII/RII) using SYSCFG_ETH_MediaInterfaceConfig()
21
  
22
       -@- SYSCFG APB clock must be enabled to get write access to SYSCFG registers,
23
           using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
24
                   
25
 @endverbatim      
26
  ******************************************************************************
27
  * @attention
28
  *
29
  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
30
  *
31
  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
32
  * You may not use this file except in compliance with the License.
33
  * You may obtain a copy of the License at:
34
  *
35
  *        http://www.st.com/software_license_agreement_liberty_v2
36
  *
37
  * Unless required by applicable law or agreed to in writing, software 
38
  * distributed under the License is distributed on an "AS IS" BASIS, 
39
  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
40
  * See the License for the specific language governing permissions and
41
  * limitations under the License.
42
  *
43
  ******************************************************************************
44
  */
45
46
/* Includes ------------------------------------------------------------------*/
47
#include "stm32f4xx_syscfg.h"
48
#include "stm32f4xx_rcc.h"
49
50
/** @addtogroup STM32F4xx_StdPeriph_Driver
51
  * @{
52
  */
53
54
/** @defgroup SYSCFG 
55
  * @brief SYSCFG driver modules
56
  * @{
57
  */ 
58
59
/* Private typedef -----------------------------------------------------------*/
60
/* Private define ------------------------------------------------------------*/
61
/* ------------ RCC registers bit address in the alias region ----------- */
62
#define SYSCFG_OFFSET             (SYSCFG_BASE - PERIPH_BASE)
63
64
/* ---  PMC Register ---*/ 
65
/* Alias word address of MII_RMII_SEL bit */ 
66
#define PMC_OFFSET                (SYSCFG_OFFSET + 0x04) 
67
#define MII_RMII_SEL_BitNumber    ((uint8_t)0x17) 
68
#define PMC_MII_RMII_SEL_BB       (PERIPH_BB_BASE + (PMC_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4)) 
69
70
/* ---  CMPCR Register ---*/ 
71
/* Alias word address of CMP_PD bit */ 
72
#define CMPCR_OFFSET              (SYSCFG_OFFSET + 0x20) 
73
#define CMP_PD_BitNumber          ((uint8_t)0x00) 
74
#define CMPCR_CMP_PD_BB           (PERIPH_BB_BASE + (CMPCR_OFFSET * 32) + (CMP_PD_BitNumber * 4)) 
75
76
/* Private macro -------------------------------------------------------------*/
77
/* Private variables ---------------------------------------------------------*/
78
/* Private function prototypes -----------------------------------------------*/
79
/* Private functions ---------------------------------------------------------*/
80
81
/** @defgroup SYSCFG_Private_Functions
82
  * @{
83
  */ 
84
85
/**
86
  * @brief  Deinitializes the Alternate Functions (remap and EXTI configuration)
87
  *   registers to their default reset values.
88
  * @param  None
89
  * @retval None
90
  */
91
void SYSCFG_DeInit(void)
92
{
93
   RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, ENABLE);
94
   RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, DISABLE);
95
}
96
97
/**
98
  * @brief  Changes the mapping of the specified pin.
99
  * @param  SYSCFG_Memory: selects the memory remapping.
100
  *         This parameter can be one of the following values:
101
  *            @arg SYSCFG_MemoryRemap_Flash:       Main Flash memory mapped at 0x00000000  
102
  *            @arg SYSCFG_MemoryRemap_SystemFlash: System Flash memory mapped at 0x00000000
103
  *            @arg SYSCFG_MemoryRemap_FSMC:        FSMC (Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000   
104
  *            @arg SYSCFG_MemoryRemap_SRAM:        Embedded SRAM (112kB) mapped at 0x00000000          
105
  * @retval None
106
  */
107
void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap)
108
{
109
  /* Check the parameters */
110
  assert_param(IS_SYSCFG_MEMORY_REMAP_CONFING(SYSCFG_MemoryRemap));
111
112
  SYSCFG->MEMRMP = SYSCFG_MemoryRemap;
113
}
114
115
/**
116
  * @brief  Selects the GPIO pin used as EXTI Line.
117
  * @param  EXTI_PortSourceGPIOx : selects the GPIO port to be used as source for
118
  *          EXTI lines where x can be (A..I)  for STM32F40xx/STM32F41xx 
119
  *         and STM32F427x/STM32F437x devices.
120
  *            
121
  * @param  EXTI_PinSourcex: specifies the EXTI line to be configured.
122
  *           This parameter can be EXTI_PinSourcex where x can be (0..15, except
123
  *           for EXTI_PortSourceGPIOI x can be (0..11) for STM32F40xx/STM32F41xx 
124
  *           and STM32F427x/STM32F437x devices. 
125
  *             
126
  * @retval None
127
  */
128
void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)
129
{
130
  uint32_t tmp = 0x00;
131
132
  /* Check the parameters */
133
  assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx));
134
  assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex));
135
136
  tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03));
137
  SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp;
138
  SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)));
139
}
140
141
/**
142
  * @brief  Selects the ETHERNET media interface 
143
  * @param  SYSCFG_ETH_MediaInterface: specifies the Media Interface mode. 
144
  *          This parameter can be one of the following values: 
145
  *            @arg SYSCFG_ETH_MediaInterface_MII: MII mode selected
146
  *            @arg SYSCFG_ETH_MediaInterface_RMII: RMII mode selected 
147
  * @retval None 
148
  */
149
void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface) 
150
{ 
151
  assert_param(IS_SYSCFG_ETH_MEDIA_INTERFACE(SYSCFG_ETH_MediaInterface)); 
152
  /* Configure MII_RMII selection bit */ 
153
  *(__IO uint32_t *) PMC_MII_RMII_SEL_BB = SYSCFG_ETH_MediaInterface; 
154
}
155
156
/**
157
  * @brief  Enables or disables the I/O Compensation Cell.
158
  * @note   The I/O compensation cell can be used only when the device supply
159
  *         voltage ranges from 2.4 to 3.6 V.  
160
  * @param  NewState: new state of the I/O Compensation Cell.
161
  *          This parameter can be one of the following values:
162
  *            @arg ENABLE: I/O compensation cell enabled  
163
  *            @arg DISABLE: I/O compensation cell power-down mode  
164
  * @retval None
165
  */
166
void SYSCFG_CompensationCellCmd(FunctionalState NewState)
167
{
168
  /* Check the parameters */
169
  assert_param(IS_FUNCTIONAL_STATE(NewState));
170
171
  *(__IO uint32_t *) CMPCR_CMP_PD_BB = (uint32_t)NewState;
172
}
173
174
/**
175
  * @brief  Checks whether the I/O Compensation Cell ready flag is set or not.
176
  * @param  None
177
  * @retval The new state of the I/O Compensation Cell ready flag (SET or RESET)
178
  */
179
FlagStatus SYSCFG_GetCompensationCellStatus(void)
180
{
181
  FlagStatus bitstatus = RESET;
182
    
183
  if ((SYSCFG->CMPCR & SYSCFG_CMPCR_READY ) != (uint32_t)RESET)
184
  {
185
    bitstatus = SET;
186
  }
187
  else
188
  {
189
    bitstatus = RESET;
190
  }
191
  return bitstatus;
192
}
193
194
/**
195
  * @}
196
  */
197
198
/**
199
  * @}
200
  */
201
202
/**
203
  * @}
204
  */
205
206
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/