amiro-blt / Target / Modules / PowerManagement_1-1 / Boot / lib / stdperiphlib / STM32F4xx_StdPeriph_Driver / src / stm32f4xx_syscfg.c @ 367c0652
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1 | 69661903 | Thomas Schöpping | /**
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2 | ******************************************************************************
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3 | * @file stm32f4xx_syscfg.c
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4 | * @author MCD Application Team
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5 | * @version V1.1.0
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6 | * @date 11-January-2013
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7 | * @brief This file provides firmware functions to manage the SYSCFG peripheral.
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8 | *
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9 | @verbatim
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10 |
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11 | ===============================================================================
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12 | ##### How to use this driver #####
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13 | ===============================================================================
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14 | [..] This driver provides functions for:
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15 |
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16 | (#) Remapping the memory accessible in the code area using SYSCFG_MemoryRemapConfig()
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17 |
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18 | (#) Manage the EXTI lines connection to the GPIOs using SYSCFG_EXTILineConfig()
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19 |
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20 | (#) Select the ETHERNET media interface (RMII/RII) using SYSCFG_ETH_MediaInterfaceConfig()
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21 |
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22 | -@- SYSCFG APB clock must be enabled to get write access to SYSCFG registers,
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23 | using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
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24 |
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25 | @endverbatim
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26 | ******************************************************************************
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27 | * @attention
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28 | *
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29 | * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
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30 | *
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31 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
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32 | * You may not use this file except in compliance with the License.
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33 | * You may obtain a copy of the License at:
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34 | *
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35 | * http://www.st.com/software_license_agreement_liberty_v2
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36 | *
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37 | * Unless required by applicable law or agreed to in writing, software
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38 | * distributed under the License is distributed on an "AS IS" BASIS,
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39 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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40 | * See the License for the specific language governing permissions and
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41 | * limitations under the License.
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42 | *
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43 | ******************************************************************************
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44 | */
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45 | |||
46 | /* Includes ------------------------------------------------------------------*/
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47 | #include "stm32f4xx_syscfg.h" |
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48 | #include "stm32f4xx_rcc.h" |
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49 | |||
50 | /** @addtogroup STM32F4xx_StdPeriph_Driver
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51 | * @{
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52 | */
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53 | |||
54 | /** @defgroup SYSCFG
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55 | * @brief SYSCFG driver modules
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56 | * @{
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57 | */
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58 | |||
59 | /* Private typedef -----------------------------------------------------------*/
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60 | /* Private define ------------------------------------------------------------*/
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61 | /* ------------ RCC registers bit address in the alias region ----------- */
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62 | #define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE)
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63 | |||
64 | /* --- PMC Register ---*/
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65 | /* Alias word address of MII_RMII_SEL bit */
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66 | #define PMC_OFFSET (SYSCFG_OFFSET + 0x04) |
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67 | #define MII_RMII_SEL_BitNumber ((uint8_t)0x17) |
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68 | #define PMC_MII_RMII_SEL_BB (PERIPH_BB_BASE + (PMC_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4)) |
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69 | |||
70 | /* --- CMPCR Register ---*/
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71 | /* Alias word address of CMP_PD bit */
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72 | #define CMPCR_OFFSET (SYSCFG_OFFSET + 0x20) |
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73 | #define CMP_PD_BitNumber ((uint8_t)0x00) |
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74 | #define CMPCR_CMP_PD_BB (PERIPH_BB_BASE + (CMPCR_OFFSET * 32) + (CMP_PD_BitNumber * 4)) |
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75 | |||
76 | /* Private macro -------------------------------------------------------------*/
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77 | /* Private variables ---------------------------------------------------------*/
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78 | /* Private function prototypes -----------------------------------------------*/
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79 | /* Private functions ---------------------------------------------------------*/
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80 | |||
81 | /** @defgroup SYSCFG_Private_Functions
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82 | * @{
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83 | */
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84 | |||
85 | /**
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86 | * @brief Deinitializes the Alternate Functions (remap and EXTI configuration)
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87 | * registers to their default reset values.
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88 | * @param None
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89 | * @retval None
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90 | */
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91 | void SYSCFG_DeInit(void) |
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92 | { |
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93 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, ENABLE); |
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94 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, DISABLE); |
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95 | } |
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96 | |||
97 | /**
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98 | * @brief Changes the mapping of the specified pin.
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99 | * @param SYSCFG_Memory: selects the memory remapping.
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100 | * This parameter can be one of the following values:
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101 | * @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000
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102 | * @arg SYSCFG_MemoryRemap_SystemFlash: System Flash memory mapped at 0x00000000
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103 | * @arg SYSCFG_MemoryRemap_FSMC: FSMC (Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
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104 | * @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM (112kB) mapped at 0x00000000
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105 | * @retval None
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106 | */
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107 | void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap)
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108 | { |
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109 | /* Check the parameters */
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110 | assert_param(IS_SYSCFG_MEMORY_REMAP_CONFING(SYSCFG_MemoryRemap)); |
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111 | |||
112 | SYSCFG->MEMRMP = SYSCFG_MemoryRemap; |
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113 | } |
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114 | |||
115 | /**
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116 | * @brief Selects the GPIO pin used as EXTI Line.
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117 | * @param EXTI_PortSourceGPIOx : selects the GPIO port to be used as source for
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118 | * EXTI lines where x can be (A..I) for STM32F40xx/STM32F41xx
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119 | * and STM32F427x/STM32F437x devices.
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120 | *
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121 | * @param EXTI_PinSourcex: specifies the EXTI line to be configured.
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122 | * This parameter can be EXTI_PinSourcex where x can be (0..15, except
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123 | * for EXTI_PortSourceGPIOI x can be (0..11) for STM32F40xx/STM32F41xx
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124 | * and STM32F427x/STM32F437x devices.
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125 | *
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126 | * @retval None
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127 | */
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128 | void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)
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129 | { |
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130 | uint32_t tmp = 0x00;
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131 | |||
132 | /* Check the parameters */
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133 | assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx)); |
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134 | assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex)); |
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135 | |||
136 | tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)); |
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137 | SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp;
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138 | SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03))); |
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139 | } |
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140 | |||
141 | /**
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142 | * @brief Selects the ETHERNET media interface
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143 | * @param SYSCFG_ETH_MediaInterface: specifies the Media Interface mode.
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144 | * This parameter can be one of the following values:
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145 | * @arg SYSCFG_ETH_MediaInterface_MII: MII mode selected
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146 | * @arg SYSCFG_ETH_MediaInterface_RMII: RMII mode selected
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147 | * @retval None
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148 | */
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149 | void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface)
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150 | { |
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151 | assert_param(IS_SYSCFG_ETH_MEDIA_INTERFACE(SYSCFG_ETH_MediaInterface)); |
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152 | /* Configure MII_RMII selection bit */
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153 | *(__IO uint32_t *) PMC_MII_RMII_SEL_BB = SYSCFG_ETH_MediaInterface; |
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154 | } |
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155 | |||
156 | /**
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157 | * @brief Enables or disables the I/O Compensation Cell.
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158 | * @note The I/O compensation cell can be used only when the device supply
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159 | * voltage ranges from 2.4 to 3.6 V.
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160 | * @param NewState: new state of the I/O Compensation Cell.
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161 | * This parameter can be one of the following values:
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162 | * @arg ENABLE: I/O compensation cell enabled
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163 | * @arg DISABLE: I/O compensation cell power-down mode
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164 | * @retval None
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165 | */
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166 | void SYSCFG_CompensationCellCmd(FunctionalState NewState)
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167 | { |
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168 | /* Check the parameters */
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169 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
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170 | |||
171 | *(__IO uint32_t *) CMPCR_CMP_PD_BB = (uint32_t)NewState; |
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172 | } |
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173 | |||
174 | /**
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175 | * @brief Checks whether the I/O Compensation Cell ready flag is set or not.
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176 | * @param None
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177 | * @retval The new state of the I/O Compensation Cell ready flag (SET or RESET)
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178 | */
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179 | FlagStatus SYSCFG_GetCompensationCellStatus(void)
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180 | { |
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181 | FlagStatus bitstatus = RESET; |
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182 | |||
183 | if ((SYSCFG->CMPCR & SYSCFG_CMPCR_READY ) != (uint32_t)RESET)
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184 | { |
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185 | bitstatus = SET; |
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186 | } |
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187 | else
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188 | { |
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189 | bitstatus = RESET; |
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190 | } |
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191 | return bitstatus;
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192 | } |
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193 | |||
194 | /**
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195 | * @}
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196 | */
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197 | |||
198 | /**
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199 | * @}
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200 | */
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201 | |||
202 | /**
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203 | * @}
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204 | */
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205 | |||
206 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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