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amiro-blt / Target / Modules / PowerManagement_1-1 / Boot / lib / uip / netdev.c @ 367c0652

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1 69661903 Thomas Schöpping
/*
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 * Copyright (c) 2001, Swedish Institute of Computer Science.
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 * All rights reserved.
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * are met:
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 *
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 * 1. Redistributions of source code must retain the above copyright
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 *    notice, this list of conditions and the following disclaimer.
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 *
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 * 2. Redistributions in binary form must reproduce the above copyright
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 *    notice, this list of conditions and the following disclaimer in the
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 *    documentation and/or other materials provided with the distribution.
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 *
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 * 3. Neither the name of the Institute nor the names of its contributors
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 *    may be used to endorse or promote products derived from this software
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 *    without specific prior written permission.
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 *
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 * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
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 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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 * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
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 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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 * SUCH DAMAGE.
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 *
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 * Author: Adam Dunkels <adam@sics.se>
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 *
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 * $Id: netdev.c,v 1.8 2006/06/07 08:39:58 adam Exp $
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 */
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/*---------------------------------------------------------------------------*/
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#include "uip.h"
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#include "uip_arp.h"
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#include "boot.h"
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#include "stm32f4xx.h"                               /* STM32 registers                */
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#include "stm32f4xx_conf.h"                          /* STM32 peripheral drivers       */
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#include "stm32_eth.h"                               /* STM32 ethernet library         */
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#include <string.h>                                  /* for memcpy                     */
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/*---------------------------------------------------------------------------*/
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#define NETDEV_DEFAULT_MACADDR0           (0x08)
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#define NETDEV_DEFAULT_MACADDR1           (0x00)
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#define NETDEV_DEFAULT_MACADDR2           (0x27)
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#define NETDEV_DEFAULT_MACADDR3           (0x69)
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#define NETDEV_DEFAULT_MACADDR4           (0x5B)
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#define NETDEV_DEFAULT_MACADDR5           (0x45)
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/*---------------------------------------------------------------------------*/
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static void netdev_TxDscrInit(void);
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static void netdev_RxDscrInit(void);
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/*---------------------------------------------------------------------------*/
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typedef union _TranDesc0_t
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{
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  uint32_t Data;
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  struct {
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    uint32_t  DB            : 1;
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    uint32_t  UF            : 1;
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    uint32_t  ED            : 1;
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    uint32_t  CC            : 4;
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    uint32_t  VF            : 1;
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    uint32_t  EC            : 1;
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    uint32_t  LC            : 1;
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    uint32_t  NC            : 1;
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    uint32_t  LSC           : 1;
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    uint32_t  IPE           : 1;
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    uint32_t  FF            : 1;
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    uint32_t  JT            : 1;
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    uint32_t  ES            : 1;
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    uint32_t  IHE           : 1;
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    uint32_t                : 3;
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    uint32_t  TCH           : 1;
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    uint32_t  TER           : 1;
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    uint32_t  CIC           : 2;
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    uint32_t                : 2;
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    uint32_t  DP            : 1;
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    uint32_t  DC            : 1;
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    uint32_t  FS            : 1;
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    uint32_t  LSEG          : 1;
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    uint32_t  IC            : 1;
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    uint32_t  OWN           : 1;
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  };
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} TranDesc0_t, * pTranDesc0_t;
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typedef union _TranDesc1_t
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{
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  uint32_t Data;
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  struct {
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    uint32_t  TBS1          :13;
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    uint32_t                : 3;
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    uint32_t  TBS2          :12;
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    uint32_t                : 3;
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  };
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} TranDesc1_t, * pTranDesc1_t;
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typedef union _RecDesc0_t
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{
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  uint32_t Data;
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  struct {
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    uint32_t  RMAM_PCE      : 1;
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    uint32_t  CE            : 1;
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    uint32_t  DE            : 1;
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    uint32_t  RE            : 1;
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    uint32_t  RWT           : 1;
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    uint32_t  FT            : 1;
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    uint32_t  LC            : 1;
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    uint32_t  IPHCE         : 1;
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    uint32_t  LS            : 1;
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    uint32_t  FS            : 1;
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    uint32_t  VLAN          : 1;
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    uint32_t  OE            : 1;
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    uint32_t  LE            : 1;
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    uint32_t  SAF           : 1;
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    uint32_t  DERR          : 1;
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    uint32_t  ES            : 1;
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    uint32_t  FL            :14;
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    uint32_t  AFM           : 1;
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    uint32_t  OWN           : 1;
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  };
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} RecDesc0_t, * pRecDesc0_t;
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typedef union _recDesc1_t
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{
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  uint32_t Data;
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  struct {
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    uint32_t  RBS1          :13;
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    uint32_t                : 1;
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    uint32_t  RCH           : 1;
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    uint32_t  RER           : 1;
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    uint32_t  RBS2          :14;
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    uint32_t  DIC           : 1;
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  };
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} RecDesc1_t, * pRecDesc1_t;
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typedef union _EnetDmaDesc_t
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{
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  uint32_t Data[4];
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  // Rx DMA descriptor
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  struct
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  {
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    RecDesc0_t                RxDesc0;
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    RecDesc1_t                RxDesc1;
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    uint32_t *                   pBuffer;
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    union
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    {
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      uint32_t *                 pBuffer2;
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      union _EnetDmaDesc_t *  pEnetDmaNextDesc;
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    };
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  } Rx;
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  // Tx DMA descriptor
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  struct
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  {
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    TranDesc0_t               TxDesc0;
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    TranDesc1_t               TxDesc1;
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    uint32_t *                   pBuffer1;
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    union
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    {
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      uint32_t *                 pBuffer2;
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      union _EnetDmaDesc_t *  pEnetDmaNextDesc;
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    };
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  } Tx;
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} EnetDmaDesc_t, * pEnetDmaDesc_t;
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/*---------------------------------------------------------------------------*/
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uint8_t RxBuff[UIP_CONF_BUFFER_SIZE] __attribute__ ((aligned (4)));
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uint8_t TxBuff[UIP_CONF_BUFFER_SIZE] __attribute__ ((aligned (4)));
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EnetDmaDesc_t EnetDmaRx __attribute__((aligned (128)));
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EnetDmaDesc_t EnetDmaTx __attribute__ ((aligned (128)));
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/*---------------------------------------------------------------------------*/
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void netdev_init(void)
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{
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  GPIO_InitTypeDef GPIO_InitStructure;
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  ETH_InitTypeDef ETH_InitStructure;
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  /* Enable ETHERNET clocks  */
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  RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_ETH_MAC | RCC_AHB1Periph_ETH_MAC_Tx |
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                         RCC_AHB1Periph_ETH_MAC_Rx | RCC_AHB1Periph_ETH_MAC_PTP, ENABLE);
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  /* Enable GPIOs clocks */
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  RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA |        RCC_AHB1Periph_GPIOB | 
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                         RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOG, ENABLE);
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  /* Enable SYSCFG clock */
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  RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
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  /*Select RMII Interface*/
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  SYSCFG_ETH_MediaInterfaceConfig(SYSCFG_ETH_MediaInterface_RMII);
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  /* ETHERNET pins configuration */
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  /* PA
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    ETH_RMII_REF_CLK: PA1
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    ETH_RMII_MDIO: PA2
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    ETH_RMII_MDINT: PA3
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    ETH_RMII_CRS_DV: PA7
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   */
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  /* Configure PA1, PA2, PA3 and PA7*/
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  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_7;
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  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
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  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
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  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
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  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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  GPIO_Init(GPIOA, &GPIO_InitStructure);
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  /* Connect PA1, PA2, PA3 and PA7 to ethernet module*/
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  GPIO_PinAFConfig(GPIOA, GPIO_PinSource1, GPIO_AF_ETH);
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  GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_ETH);
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  GPIO_PinAFConfig(GPIOA, GPIO_PinSource3, GPIO_AF_ETH);
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  GPIO_PinAFConfig(GPIOA, GPIO_PinSource7, GPIO_AF_ETH);
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  /* PB
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    ETH_RMII_TX_EN: PG11
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  */
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  /* Configure PG11*/
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  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11;
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  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
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  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
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  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
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  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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  GPIO_Init(GPIOG, &GPIO_InitStructure);
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  /* Connect PG11 to ethernet module*/
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  GPIO_PinAFConfig(GPIOG, GPIO_PinSource11, GPIO_AF_ETH);
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  /* PC
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    ETH_RMII_MDC: PC1
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    ETH_RMII_RXD0: PC4
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    ETH_RMII_RXD1: PC5
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  */
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  /* Configure PC1, PC4 and PC5*/
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  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5;
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  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
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  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
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  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
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  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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  GPIO_Init(GPIOC, &GPIO_InitStructure);
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  /* Connect PC1, PC4 and PC5 to ethernet module*/
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  GPIO_PinAFConfig(GPIOC, GPIO_PinSource1, GPIO_AF_ETH);
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  GPIO_PinAFConfig(GPIOC, GPIO_PinSource4, GPIO_AF_ETH);
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  GPIO_PinAFConfig(GPIOC, GPIO_PinSource5, GPIO_AF_ETH);
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  /* PG
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    ETH_RMII_TXD0: PG13
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    ETH_RMII_TXD1: PG14
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  */
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  /* Configure PG13 and PG14*/
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  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13 | GPIO_Pin_14;
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  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
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  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
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  GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
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  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
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  GPIO_Init(GPIOG, &GPIO_InitStructure);
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  /* Connect PG13 and PG14 to ethernet module*/
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  GPIO_PinAFConfig(GPIOG, GPIO_PinSource13, GPIO_AF_ETH);
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  GPIO_PinAFConfig(GPIOG, GPIO_PinSource14, GPIO_AF_ETH);
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  /* Reset ETHERNET on AHB Bus */
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  ETH_DeInit();
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  /* Software reset */ 
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  ETH_SoftwareReset();
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  /* Wait for software reset */
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  while(ETH_GetSoftwareResetStatus()==SET);
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  /* ETHERNET Configuration ------------------------------------------------------*/
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  /* Call ETH_StructInit if you don't like to configure all ETH_InitStructure parameter */
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  ETH_StructInit(&ETH_InitStructure);
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  /* Fill ETH_InitStructure parametrs */
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  /*------------------------   MAC   -----------------------------------*/
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  ETH_InitStructure.ETH_AutoNegotiation = ETH_AutoNegotiation_Disable  ;  
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  ETH_InitStructure.ETH_LoopbackMode = ETH_LoopbackMode_Disable;              
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  ETH_InitStructure.ETH_RetryTransmission = ETH_RetryTransmission_Disable;                                                                                  
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  ETH_InitStructure.ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable;                                                                                                                                                                        
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  ETH_InitStructure.ETH_ReceiveAll = ETH_ReceiveAll_Enable;                                                                                                       
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  ETH_InitStructure.ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable;      
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  ETH_InitStructure.ETH_PromiscuousMode = ETH_PromiscuousMode_Disable;                                                             
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  ETH_InitStructure.ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect;      
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  ETH_InitStructure.ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect;                        
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  ETH_InitStructure.ETH_Mode = ETH_Mode_FullDuplex;                        
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  ETH_InitStructure.ETH_Speed = ETH_Speed_100M;                        
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  unsigned int PhyAddr;
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    union {
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      uint32_t    HI_LO;
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      struct
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      {
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        uint16_t  LO;
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        uint16_t  HI;
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      };
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    } PHYID;
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  for(PhyAddr = 0; 32 > PhyAddr; PhyAddr++)
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  { 
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    // datasheet for the ks8721bl ethernet controller (http://www.micrel.com/_PDF/Ethernet/datasheets/ks8721bl-sl.pdf)
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    // page 20 --> PHY Identifier 1 and 2
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    PHYID.HI = ETH_ReadPHYRegister(PhyAddr,2);  // 0x0022
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    PHYID.LO = ETH_ReadPHYRegister(PhyAddr,3);  // 0x1619
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    if ((0x00221619 == PHYID.HI_LO) || (0x0007C0F1 == PHYID.HI_LO))
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      break;
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  }
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  if (32 < PhyAddr)
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  {
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    ASSERT_RT(BLT_FALSE);
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  }
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  /* Configure Ethernet */
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  if(0 == ETH_Init(&ETH_InitStructure, PhyAddr))
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  {
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    ASSERT_RT(BLT_FALSE);
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  }
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  netdev_TxDscrInit();
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  netdev_RxDscrInit();
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  ETH_Start();
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}
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/*---------------------------------------------------------------------------*/
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void netdev_init_mac(void)
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{
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  struct uip_eth_addr macAddress;
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  /* set the default MAC address */
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  macAddress.addr[0] = NETDEV_DEFAULT_MACADDR0;
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  macAddress.addr[1] = NETDEV_DEFAULT_MACADDR1;
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  macAddress.addr[2] = NETDEV_DEFAULT_MACADDR2;
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  macAddress.addr[3] = NETDEV_DEFAULT_MACADDR3;
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  macAddress.addr[4] = NETDEV_DEFAULT_MACADDR4;
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  macAddress.addr[5] = NETDEV_DEFAULT_MACADDR5;
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  uip_setethaddr(macAddress);
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}
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/*---------------------------------------------------------------------------*/
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unsigned int netdev_read(void)
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{
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  uint32_t size;
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  /*check for validity*/
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  if(0 == EnetDmaRx.Rx.RxDesc0.OWN)
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  {
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    /*Get the size of the packet*/
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    size = EnetDmaRx.Rx.RxDesc0.FL; // CRC
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    memcpy(uip_buf, RxBuff, size);   //string.h library*/
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  }
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  else
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  {
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    return 0;
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  }
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  /* Give the buffer back to ENET */
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  EnetDmaRx.Rx.RxDesc0.OWN = 1;
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  /* Start the receive operation */
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  ETH->DMARPDR = 1;
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  /* Return no error */
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  return size;
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}
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/*---------------------------------------------------------------------------*/
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void netdev_send(void)
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{
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  while(EnetDmaTx.Tx.TxDesc0.OWN);
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  /* Copy the  application buffer to the driver buffer
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     Using this MEMCOPY_L2L_BY4 makes the copy routine faster
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     than memcpy */
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  memcpy(TxBuff, uip_buf, uip_len);
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  /* Assign ENET address to Temp Tx Array */
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  EnetDmaTx.Tx.pBuffer1 = (uint32_t *)TxBuff;
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  /* Setting the Frame Length*/
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  EnetDmaTx.Tx.TxDesc0.Data = 0;
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  EnetDmaTx.Tx.TxDesc0.TCH  = 1;
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  EnetDmaTx.Tx.TxDesc0.LSEG = 1;
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  EnetDmaTx.Tx.TxDesc0.FS   = 1;
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  EnetDmaTx.Tx.TxDesc0.DC   = 0;
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  EnetDmaTx.Tx.TxDesc0.DP   = 0;
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  EnetDmaTx.Tx.TxDesc1.Data = 0;
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  EnetDmaTx.Tx.TxDesc1.TBS1 = (uip_len&0xFFF);
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  /* Start the ENET by setting the VALID bit in dmaPackStatus of current descr*/
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  EnetDmaTx.Tx.TxDesc0.OWN = 1;
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  /* Start the transmit operation */
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  ETH->DMATPDR = 1;
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}
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/*---------------------------------------------------------------------------*/
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static void netdev_RxDscrInit(void)
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{
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  /* Initialization */
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  /* Assign temp Rx array to the ENET buffer */
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  EnetDmaRx.Rx.pBuffer = (uint32_t *)RxBuff;
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  /* Initialize RX ENET Status and control */
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  EnetDmaRx.Rx.RxDesc0.Data = 0;
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  /* Initialize the next descriptor- In our case its single descriptor */
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  EnetDmaRx.Rx.pEnetDmaNextDesc = &EnetDmaRx;
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  EnetDmaRx.Rx.RxDesc1.Data = 0;
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  EnetDmaRx.Rx.RxDesc1.RER  = 0; // end of ring
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  EnetDmaRx.Rx.RxDesc1.RCH  = 1; // end of ring
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  /* Set the max packet size  */
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  EnetDmaRx.Rx.RxDesc1.RBS1 = UIP_CONF_BUFFER_SIZE;
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  /* Setting the VALID bit */
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  EnetDmaRx.Rx.RxDesc0.OWN = 1;
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  /* Setting the RX NEXT Descriptor Register inside the ENET */
431
  ETH->DMARDLAR = (uint32_t)&EnetDmaRx;
432
}
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/*---------------------------------------------------------------------------*/
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static void netdev_TxDscrInit(void)
437
{
438
  /* ENET Start Address */
439
  EnetDmaTx.Tx.pBuffer1 = (uint32_t *)TxBuff;
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441
  /* Next Descriptor Address */
442
  EnetDmaTx.Tx.pEnetDmaNextDesc = &EnetDmaTx;
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  /* Initialize ENET status and control */
445
  EnetDmaTx.Tx.TxDesc0.TCH  = 1;
446
  EnetDmaTx.Tx.TxDesc0.Data = 0;
447
  EnetDmaTx.Tx.TxDesc1.Data = 0;
448
  /* Tx next set to Tx descriptor base */
449
  ETH->DMATDLAR = (uint32_t)&EnetDmaTx;
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}