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amiro-blt / Target / Modules / DiWheelDrive_1-1 / Boot / lib / STM32F10x_StdPeriph_Driver / inc / stm32f10x_dma.h @ 367c0652

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/**
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  ******************************************************************************
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  * @file    stm32f10x_dma.h
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  * @author  MCD Application Team
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  * @version V3.5.0
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  * @date    11-March-2011
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  * @brief   This file contains all the functions prototypes for the DMA firmware 
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  *          library.
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  ******************************************************************************
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  * @attention
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  *
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  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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  *
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  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
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  ******************************************************************************
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  */
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32F10x_DMA_H
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#define __STM32F10x_DMA_H
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#ifdef __cplusplus
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 extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f10x.h"
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/** @addtogroup STM32F10x_StdPeriph_Driver
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  * @{
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  */
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/** @addtogroup DMA
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  * @{
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  */
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/** @defgroup DMA_Exported_Types
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  * @{
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  */
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/** 
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  * @brief  DMA Init structure definition
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  */
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typedef struct
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{
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  uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */
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  uint32_t DMA_MemoryBaseAddr;     /*!< Specifies the memory base address for DMAy Channelx. */
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  uint32_t DMA_DIR;                /*!< Specifies if the peripheral is the source or destination.
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                                        This parameter can be a value of @ref DMA_data_transfer_direction */
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  uint32_t DMA_BufferSize;         /*!< Specifies the buffer size, in data unit, of the specified Channel. 
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                                        The data unit is equal to the configuration set in DMA_PeripheralDataSize
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                                        or DMA_MemoryDataSize members depending in the transfer direction. */
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  uint32_t DMA_PeripheralInc;      /*!< Specifies whether the Peripheral address register is incremented or not.
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                                        This parameter can be a value of @ref DMA_peripheral_incremented_mode */
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  uint32_t DMA_MemoryInc;          /*!< Specifies whether the memory address register is incremented or not.
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                                        This parameter can be a value of @ref DMA_memory_incremented_mode */
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  uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
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                                        This parameter can be a value of @ref DMA_peripheral_data_size */
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  uint32_t DMA_MemoryDataSize;     /*!< Specifies the Memory data width.
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                                        This parameter can be a value of @ref DMA_memory_data_size */
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  uint32_t DMA_Mode;               /*!< Specifies the operation mode of the DMAy Channelx.
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                                        This parameter can be a value of @ref DMA_circular_normal_mode.
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                                        @note: The circular buffer mode cannot be used if the memory-to-memory
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                                              data transfer is configured on the selected Channel */
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  uint32_t DMA_Priority;           /*!< Specifies the software priority for the DMAy Channelx.
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                                        This parameter can be a value of @ref DMA_priority_level */
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  uint32_t DMA_M2M;                /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
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                                        This parameter can be a value of @ref DMA_memory_to_memory */
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}DMA_InitTypeDef;
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/**
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  * @}
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  */
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/** @defgroup DMA_Exported_Constants
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  * @{
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  */
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#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
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                                   ((PERIPH) == DMA1_Channel2) || \
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                                   ((PERIPH) == DMA1_Channel3) || \
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                                   ((PERIPH) == DMA1_Channel4) || \
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                                   ((PERIPH) == DMA1_Channel5) || \
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                                   ((PERIPH) == DMA1_Channel6) || \
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                                   ((PERIPH) == DMA1_Channel7) || \
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                                   ((PERIPH) == DMA2_Channel1) || \
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                                   ((PERIPH) == DMA2_Channel2) || \
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                                   ((PERIPH) == DMA2_Channel3) || \
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                                   ((PERIPH) == DMA2_Channel4) || \
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                                   ((PERIPH) == DMA2_Channel5))
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/** @defgroup DMA_data_transfer_direction 
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  * @{
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  */
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#define DMA_DIR_PeripheralDST              ((uint32_t)0x00000010)
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#define DMA_DIR_PeripheralSRC              ((uint32_t)0x00000000)
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#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \
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                         ((DIR) == DMA_DIR_PeripheralSRC))
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/**
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  * @}
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  */
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/** @defgroup DMA_peripheral_incremented_mode 
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  * @{
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  */
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#define DMA_PeripheralInc_Enable           ((uint32_t)0x00000040)
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#define DMA_PeripheralInc_Disable          ((uint32_t)0x00000000)
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#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
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                                            ((STATE) == DMA_PeripheralInc_Disable))
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/**
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  * @}
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  */
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/** @defgroup DMA_memory_incremented_mode 
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  * @{
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  */
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#define DMA_MemoryInc_Enable               ((uint32_t)0x00000080)
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#define DMA_MemoryInc_Disable              ((uint32_t)0x00000000)
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#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
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                                        ((STATE) == DMA_MemoryInc_Disable))
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/**
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  * @}
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  */
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/** @defgroup DMA_peripheral_data_size 
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  * @{
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  */
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#define DMA_PeripheralDataSize_Byte        ((uint32_t)0x00000000)
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#define DMA_PeripheralDataSize_HalfWord    ((uint32_t)0x00000100)
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#define DMA_PeripheralDataSize_Word        ((uint32_t)0x00000200)
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#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
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                                           ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
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                                           ((SIZE) == DMA_PeripheralDataSize_Word))
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/**
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  * @}
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  */
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/** @defgroup DMA_memory_data_size 
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  * @{
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  */
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#define DMA_MemoryDataSize_Byte            ((uint32_t)0x00000000)
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#define DMA_MemoryDataSize_HalfWord        ((uint32_t)0x00000400)
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#define DMA_MemoryDataSize_Word            ((uint32_t)0x00000800)
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#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
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                                       ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
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                                       ((SIZE) == DMA_MemoryDataSize_Word))
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/**
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  * @}
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  */
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/** @defgroup DMA_circular_normal_mode 
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  * @{
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  */
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#define DMA_Mode_Circular                  ((uint32_t)0x00000020)
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#define DMA_Mode_Normal                    ((uint32_t)0x00000000)
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#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal))
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/**
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  * @}
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  */
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/** @defgroup DMA_priority_level 
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  * @{
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  */
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#define DMA_Priority_VeryHigh              ((uint32_t)0x00003000)
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#define DMA_Priority_High                  ((uint32_t)0x00002000)
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#define DMA_Priority_Medium                ((uint32_t)0x00001000)
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#define DMA_Priority_Low                   ((uint32_t)0x00000000)
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#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
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                                   ((PRIORITY) == DMA_Priority_High) || \
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                                   ((PRIORITY) == DMA_Priority_Medium) || \
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                                   ((PRIORITY) == DMA_Priority_Low))
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/**
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  * @}
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  */
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/** @defgroup DMA_memory_to_memory 
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  * @{
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  */
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#define DMA_M2M_Enable                     ((uint32_t)0x00004000)
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#define DMA_M2M_Disable                    ((uint32_t)0x00000000)
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#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable))
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/**
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  * @}
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  */
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/** @defgroup DMA_interrupts_definition 
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  * @{
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  */
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#define DMA_IT_TC                          ((uint32_t)0x00000002)
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#define DMA_IT_HT                          ((uint32_t)0x00000004)
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#define DMA_IT_TE                          ((uint32_t)0x00000008)
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#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
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#define DMA1_IT_GL1                        ((uint32_t)0x00000001)
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#define DMA1_IT_TC1                        ((uint32_t)0x00000002)
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#define DMA1_IT_HT1                        ((uint32_t)0x00000004)
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#define DMA1_IT_TE1                        ((uint32_t)0x00000008)
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#define DMA1_IT_GL2                        ((uint32_t)0x00000010)
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#define DMA1_IT_TC2                        ((uint32_t)0x00000020)
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#define DMA1_IT_HT2                        ((uint32_t)0x00000040)
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#define DMA1_IT_TE2                        ((uint32_t)0x00000080)
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#define DMA1_IT_GL3                        ((uint32_t)0x00000100)
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#define DMA1_IT_TC3                        ((uint32_t)0x00000200)
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#define DMA1_IT_HT3                        ((uint32_t)0x00000400)
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#define DMA1_IT_TE3                        ((uint32_t)0x00000800)
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#define DMA1_IT_GL4                        ((uint32_t)0x00001000)
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#define DMA1_IT_TC4                        ((uint32_t)0x00002000)
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#define DMA1_IT_HT4                        ((uint32_t)0x00004000)
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#define DMA1_IT_TE4                        ((uint32_t)0x00008000)
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#define DMA1_IT_GL5                        ((uint32_t)0x00010000)
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#define DMA1_IT_TC5                        ((uint32_t)0x00020000)
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#define DMA1_IT_HT5                        ((uint32_t)0x00040000)
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#define DMA1_IT_TE5                        ((uint32_t)0x00080000)
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#define DMA1_IT_GL6                        ((uint32_t)0x00100000)
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#define DMA1_IT_TC6                        ((uint32_t)0x00200000)
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#define DMA1_IT_HT6                        ((uint32_t)0x00400000)
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#define DMA1_IT_TE6                        ((uint32_t)0x00800000)
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#define DMA1_IT_GL7                        ((uint32_t)0x01000000)
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#define DMA1_IT_TC7                        ((uint32_t)0x02000000)
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#define DMA1_IT_HT7                        ((uint32_t)0x04000000)
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#define DMA1_IT_TE7                        ((uint32_t)0x08000000)
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#define DMA2_IT_GL1                        ((uint32_t)0x10000001)
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#define DMA2_IT_TC1                        ((uint32_t)0x10000002)
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#define DMA2_IT_HT1                        ((uint32_t)0x10000004)
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#define DMA2_IT_TE1                        ((uint32_t)0x10000008)
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#define DMA2_IT_GL2                        ((uint32_t)0x10000010)
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#define DMA2_IT_TC2                        ((uint32_t)0x10000020)
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#define DMA2_IT_HT2                        ((uint32_t)0x10000040)
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#define DMA2_IT_TE2                        ((uint32_t)0x10000080)
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#define DMA2_IT_GL3                        ((uint32_t)0x10000100)
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#define DMA2_IT_TC3                        ((uint32_t)0x10000200)
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#define DMA2_IT_HT3                        ((uint32_t)0x10000400)
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#define DMA2_IT_TE3                        ((uint32_t)0x10000800)
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#define DMA2_IT_GL4                        ((uint32_t)0x10001000)
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#define DMA2_IT_TC4                        ((uint32_t)0x10002000)
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#define DMA2_IT_HT4                        ((uint32_t)0x10004000)
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#define DMA2_IT_TE4                        ((uint32_t)0x10008000)
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#define DMA2_IT_GL5                        ((uint32_t)0x10010000)
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#define DMA2_IT_TC5                        ((uint32_t)0x10020000)
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#define DMA2_IT_HT5                        ((uint32_t)0x10040000)
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#define DMA2_IT_TE5                        ((uint32_t)0x10080000)
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#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))
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#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
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                           ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
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                           ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
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                           ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
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                           ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
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                           ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
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                           ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
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                           ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
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                           ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
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                           ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \
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                           ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \
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                           ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \
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                           ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \
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                           ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \
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                           ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \
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                           ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \
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                           ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \
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                           ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \
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                           ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \
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                           ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \
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                           ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \
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                           ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \
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                           ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \
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                           ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))
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/**
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  * @}
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  */
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/** @defgroup DMA_flags_definition 
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  * @{
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  */
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#define DMA1_FLAG_GL1                      ((uint32_t)0x00000001)
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#define DMA1_FLAG_TC1                      ((uint32_t)0x00000002)
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#define DMA1_FLAG_HT1                      ((uint32_t)0x00000004)
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#define DMA1_FLAG_TE1                      ((uint32_t)0x00000008)
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#define DMA1_FLAG_GL2                      ((uint32_t)0x00000010)
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#define DMA1_FLAG_TC2                      ((uint32_t)0x00000020)
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#define DMA1_FLAG_HT2                      ((uint32_t)0x00000040)
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#define DMA1_FLAG_TE2                      ((uint32_t)0x00000080)
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#define DMA1_FLAG_GL3                      ((uint32_t)0x00000100)
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#define DMA1_FLAG_TC3                      ((uint32_t)0x00000200)
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#define DMA1_FLAG_HT3                      ((uint32_t)0x00000400)
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#define DMA1_FLAG_TE3                      ((uint32_t)0x00000800)
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#define DMA1_FLAG_GL4                      ((uint32_t)0x00001000)
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#define DMA1_FLAG_TC4                      ((uint32_t)0x00002000)
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#define DMA1_FLAG_HT4                      ((uint32_t)0x00004000)
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#define DMA1_FLAG_TE4                      ((uint32_t)0x00008000)
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#define DMA1_FLAG_GL5                      ((uint32_t)0x00010000)
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#define DMA1_FLAG_TC5                      ((uint32_t)0x00020000)
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#define DMA1_FLAG_HT5                      ((uint32_t)0x00040000)
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#define DMA1_FLAG_TE5                      ((uint32_t)0x00080000)
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#define DMA1_FLAG_GL6                      ((uint32_t)0x00100000)
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#define DMA1_FLAG_TC6                      ((uint32_t)0x00200000)
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#define DMA1_FLAG_HT6                      ((uint32_t)0x00400000)
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#define DMA1_FLAG_TE6                      ((uint32_t)0x00800000)
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#define DMA1_FLAG_GL7                      ((uint32_t)0x01000000)
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#define DMA1_FLAG_TC7                      ((uint32_t)0x02000000)
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#define DMA1_FLAG_HT7                      ((uint32_t)0x04000000)
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#define DMA1_FLAG_TE7                      ((uint32_t)0x08000000)
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#define DMA2_FLAG_GL1                      ((uint32_t)0x10000001)
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#define DMA2_FLAG_TC1                      ((uint32_t)0x10000002)
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#define DMA2_FLAG_HT1                      ((uint32_t)0x10000004)
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#define DMA2_FLAG_TE1                      ((uint32_t)0x10000008)
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#define DMA2_FLAG_GL2                      ((uint32_t)0x10000010)
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#define DMA2_FLAG_TC2                      ((uint32_t)0x10000020)
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#define DMA2_FLAG_HT2                      ((uint32_t)0x10000040)
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#define DMA2_FLAG_TE2                      ((uint32_t)0x10000080)
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#define DMA2_FLAG_GL3                      ((uint32_t)0x10000100)
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#define DMA2_FLAG_TC3                      ((uint32_t)0x10000200)
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#define DMA2_FLAG_HT3                      ((uint32_t)0x10000400)
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#define DMA2_FLAG_TE3                      ((uint32_t)0x10000800)
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#define DMA2_FLAG_GL4                      ((uint32_t)0x10001000)
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#define DMA2_FLAG_TC4                      ((uint32_t)0x10002000)
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#define DMA2_FLAG_HT4                      ((uint32_t)0x10004000)
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#define DMA2_FLAG_TE4                      ((uint32_t)0x10008000)
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#define DMA2_FLAG_GL5                      ((uint32_t)0x10010000)
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#define DMA2_FLAG_TC5                      ((uint32_t)0x10020000)
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#define DMA2_FLAG_HT5                      ((uint32_t)0x10040000)
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#define DMA2_FLAG_TE5                      ((uint32_t)0x10080000)
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#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))
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#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
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                               ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
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                               ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
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                               ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
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                               ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
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                               ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
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                               ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
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                               ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
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                               ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
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                               ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \
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                               ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \
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                               ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \
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                               ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \
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                               ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \
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                               ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \
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                               ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \
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                               ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \
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                               ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \
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                               ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \
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                               ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \
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                               ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \
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                               ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \
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                               ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \
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                               ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))
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/**
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  * @}
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  */
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/** @defgroup DMA_Buffer_Size 
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  * @{
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  */
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#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
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/**
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  * @}
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  */
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/**
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  * @}
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  */
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/** @defgroup DMA_Exported_Macros
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  * @{
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  */
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/**
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  * @}
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  */
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/** @defgroup DMA_Exported_Functions
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  * @{
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  */
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void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
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void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
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void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
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void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
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void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
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void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber); 
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uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
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FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
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void DMA_ClearFlag(uint32_t DMAy_FLAG);
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ITStatus DMA_GetITStatus(uint32_t DMAy_IT);
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void DMA_ClearITPendingBit(uint32_t DMAy_IT);
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#ifdef __cplusplus
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}
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#endif
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#endif /*__STM32F10x_DMA_H */
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/**
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  * @}
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  */
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/**
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  * @}
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  */
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/**
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  * @}
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  */
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/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/