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amiro-blt / Target / Modules / DiWheelDrive_1-1 / Boot / lib / STM32F10x_StdPeriph_Driver / src / stm32f10x_sdio.c @ 367c0652

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/**
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  ******************************************************************************
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  * @file    stm32f10x_sdio.c
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  * @author  MCD Application Team
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  * @version V3.5.0
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  * @date    11-March-2011
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  * @brief   This file provides all the SDIO firmware functions.
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  ******************************************************************************
9
  * @attention
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  *
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  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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  *
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  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
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  ******************************************************************************
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  */
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f10x_sdio.h"
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#include "stm32f10x_rcc.h"
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/** @addtogroup STM32F10x_StdPeriph_Driver
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  * @{
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  */
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/** @defgroup SDIO 
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  * @brief SDIO driver modules
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  * @{
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  */ 
34

    
35
/** @defgroup SDIO_Private_TypesDefinitions
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  * @{
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  */ 
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/* ------------ SDIO registers bit address in the alias region ----------- */
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#define SDIO_OFFSET                (SDIO_BASE - PERIPH_BASE)
41

    
42
/* --- CLKCR Register ---*/
43

    
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/* Alias word address of CLKEN bit */
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#define CLKCR_OFFSET              (SDIO_OFFSET + 0x04)
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#define CLKEN_BitNumber           0x08
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#define CLKCR_CLKEN_BB            (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))
48

    
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/* --- CMD Register ---*/
50

    
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/* Alias word address of SDIOSUSPEND bit */
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#define CMD_OFFSET                (SDIO_OFFSET + 0x0C)
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#define SDIOSUSPEND_BitNumber     0x0B
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#define CMD_SDIOSUSPEND_BB        (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))
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/* Alias word address of ENCMDCOMPL bit */
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#define ENCMDCOMPL_BitNumber      0x0C
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#define CMD_ENCMDCOMPL_BB         (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))
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60
/* Alias word address of NIEN bit */
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#define NIEN_BitNumber            0x0D
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#define CMD_NIEN_BB               (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))
63

    
64
/* Alias word address of ATACMD bit */
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#define ATACMD_BitNumber          0x0E
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#define CMD_ATACMD_BB             (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
67

    
68
/* --- DCTRL Register ---*/
69

    
70
/* Alias word address of DMAEN bit */
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#define DCTRL_OFFSET              (SDIO_OFFSET + 0x2C)
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#define DMAEN_BitNumber           0x03
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#define DCTRL_DMAEN_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
74

    
75
/* Alias word address of RWSTART bit */
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#define RWSTART_BitNumber         0x08
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#define DCTRL_RWSTART_BB          (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))
78

    
79
/* Alias word address of RWSTOP bit */
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#define RWSTOP_BitNumber          0x09
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#define DCTRL_RWSTOP_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
82

    
83
/* Alias word address of RWMOD bit */
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#define RWMOD_BitNumber           0x0A
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#define DCTRL_RWMOD_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))
86

    
87
/* Alias word address of SDIOEN bit */
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#define SDIOEN_BitNumber          0x0B
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#define DCTRL_SDIOEN_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))
90

    
91
/* ---------------------- SDIO registers bit mask ------------------------ */
92

    
93
/* --- CLKCR Register ---*/
94

    
95
/* CLKCR register clear mask */
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#define CLKCR_CLEAR_MASK         ((uint32_t)0xFFFF8100) 
97

    
98
/* --- PWRCTRL Register ---*/
99

    
100
/* SDIO PWRCTRL Mask */
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#define PWR_PWRCTRL_MASK         ((uint32_t)0xFFFFFFFC)
102

    
103
/* --- DCTRL Register ---*/
104

    
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/* SDIO DCTRL Clear Mask */
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#define DCTRL_CLEAR_MASK         ((uint32_t)0xFFFFFF08)
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108
/* --- CMD Register ---*/
109

    
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/* CMD Register clear mask */
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#define CMD_CLEAR_MASK           ((uint32_t)0xFFFFF800)
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/* SDIO RESP Registers Address */
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#define SDIO_RESP_ADDR           ((uint32_t)(SDIO_BASE + 0x14))
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116
/**
117
  * @}
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  */
119

    
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/** @defgroup SDIO_Private_Defines
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  * @{
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  */
123

    
124
/**
125
  * @}
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  */
127

    
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/** @defgroup SDIO_Private_Macros
129
  * @{
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  */
131

    
132
/**
133
  * @}
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  */
135

    
136
/** @defgroup SDIO_Private_Variables
137
  * @{
138
  */
139

    
140
/**
141
  * @}
142
  */
143

    
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/** @defgroup SDIO_Private_FunctionPrototypes
145
  * @{
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  */
147

    
148
/**
149
  * @}
150
  */
151

    
152
/** @defgroup SDIO_Private_Functions
153
  * @{
154
  */
155

    
156
/**
157
  * @brief  Deinitializes the SDIO peripheral registers to their default reset values.
158
  * @param  None
159
  * @retval None
160
  */
161
void SDIO_DeInit(void)
162
{
163
  SDIO->POWER = 0x00000000;
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  SDIO->CLKCR = 0x00000000;
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  SDIO->ARG = 0x00000000;
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  SDIO->CMD = 0x00000000;
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  SDIO->DTIMER = 0x00000000;
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  SDIO->DLEN = 0x00000000;
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  SDIO->DCTRL = 0x00000000;
170
  SDIO->ICR = 0x00C007FF;
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  SDIO->MASK = 0x00000000;
172
}
173

    
174
/**
175
  * @brief  Initializes the SDIO peripheral according to the specified 
176
  *         parameters in the SDIO_InitStruct.
177
  * @param  SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure 
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  *         that contains the configuration information for the SDIO peripheral.
179
  * @retval None
180
  */
181
void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct)
182
{
183
  uint32_t tmpreg = 0;
184
    
185
  /* Check the parameters */
186
  assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge));
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  assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass));
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  assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave));
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  assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide));
190
  assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl)); 
191
   
192
/*---------------------------- SDIO CLKCR Configuration ------------------------*/  
193
  /* Get the SDIO CLKCR value */
194
  tmpreg = SDIO->CLKCR;
195
  
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  /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */
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  tmpreg &= CLKCR_CLEAR_MASK;
198
  
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  /* Set CLKDIV bits according to SDIO_ClockDiv value */
200
  /* Set PWRSAV bit according to SDIO_ClockPowerSave value */
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  /* Set BYPASS bit according to SDIO_ClockBypass value */
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  /* Set WIDBUS bits according to SDIO_BusWide value */
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  /* Set NEGEDGE bits according to SDIO_ClockEdge value */
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  /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */
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  tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv  | SDIO_InitStruct->SDIO_ClockPowerSave |
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             SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide |
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             SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl); 
208
  
209
  /* Write to SDIO CLKCR */
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  SDIO->CLKCR = tmpreg;
211
}
212

    
213
/**
214
  * @brief  Fills each SDIO_InitStruct member with its default value.
215
  * @param  SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which 
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  *   will be initialized.
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  * @retval None
218
  */
219
void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct)
220
{
221
  /* SDIO_InitStruct members default value */
222
  SDIO_InitStruct->SDIO_ClockDiv = 0x00;
223
  SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising;
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  SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable;
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  SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
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  SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b;
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  SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
228
}
229

    
230
/**
231
  * @brief  Enables or disables the SDIO Clock.
232
  * @param  NewState: new state of the SDIO Clock. This parameter can be: ENABLE or DISABLE.
233
  * @retval None
234
  */
235
void SDIO_ClockCmd(FunctionalState NewState)
236
{
237
  /* Check the parameters */
238
  assert_param(IS_FUNCTIONAL_STATE(NewState));
239
  
240
  *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState;
241
}
242

    
243
/**
244
  * @brief  Sets the power status of the controller.
245
  * @param  SDIO_PowerState: new state of the Power state. 
246
  *   This parameter can be one of the following values:
247
  *     @arg SDIO_PowerState_OFF
248
  *     @arg SDIO_PowerState_ON
249
  * @retval None
250
  */
251
void SDIO_SetPowerState(uint32_t SDIO_PowerState)
252
{
253
  /* Check the parameters */
254
  assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState));
255
  
256
  SDIO->POWER &= PWR_PWRCTRL_MASK;
257
  SDIO->POWER |= SDIO_PowerState;
258
}
259

    
260
/**
261
  * @brief  Gets the power status of the controller.
262
  * @param  None
263
  * @retval Power status of the controller. The returned value can
264
  *   be one of the following:
265
  * - 0x00: Power OFF
266
  * - 0x02: Power UP
267
  * - 0x03: Power ON 
268
  */
269
uint32_t SDIO_GetPowerState(void)
270
{
271
  return (SDIO->POWER & (~PWR_PWRCTRL_MASK));
272
}
273

    
274
/**
275
  * @brief  Enables or disables the SDIO interrupts.
276
  * @param  SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled.
277
  *   This parameter can be one or a combination of the following values:
278
  *     @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
279
  *     @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
280
  *     @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
281
  *     @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
282
  *     @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
283
  *     @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
284
  *     @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
285
  *     @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
286
  *     @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
287
  *     @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
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  *                            bus mode interrupt
289
  *     @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
290
  *     @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
291
  *     @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
292
  *     @arg SDIO_IT_RXACT:    Data receive in progress interrupt
293
  *     @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
294
  *     @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
295
  *     @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
296
  *     @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
297
  *     @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
298
  *     @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
299
  *     @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
300
  *     @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
301
  *     @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
302
  *     @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
303
  * @param  NewState: new state of the specified SDIO interrupts.
304
  *   This parameter can be: ENABLE or DISABLE.
305
  * @retval None 
306
  */
307
void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState)
308
{
309
  /* Check the parameters */
310
  assert_param(IS_SDIO_IT(SDIO_IT));
311
  assert_param(IS_FUNCTIONAL_STATE(NewState));
312
  
313
  if (NewState != DISABLE)
314
  {
315
    /* Enable the SDIO interrupts */
316
    SDIO->MASK |= SDIO_IT;
317
  }
318
  else
319
  {
320
    /* Disable the SDIO interrupts */
321
    SDIO->MASK &= ~SDIO_IT;
322
  } 
323
}
324

    
325
/**
326
  * @brief  Enables or disables the SDIO DMA request.
327
  * @param  NewState: new state of the selected SDIO DMA request.
328
  *   This parameter can be: ENABLE or DISABLE.
329
  * @retval None
330
  */
331
void SDIO_DMACmd(FunctionalState NewState)
332
{
333
  /* Check the parameters */
334
  assert_param(IS_FUNCTIONAL_STATE(NewState));
335
  
336
  *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState;
337
}
338

    
339
/**
340
  * @brief  Initializes the SDIO Command according to the specified 
341
  *         parameters in the SDIO_CmdInitStruct and send the command.
342
  * @param  SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef 
343
  *         structure that contains the configuration information for the SDIO command.
344
  * @retval None
345
  */
346
void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
347
{
348
  uint32_t tmpreg = 0;
349
  
350
  /* Check the parameters */
351
  assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex));
352
  assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response));
353
  assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait));
354
  assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM));
355
  
356
/*---------------------------- SDIO ARG Configuration ------------------------*/
357
  /* Set the SDIO Argument value */
358
  SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument;
359
  
360
/*---------------------------- SDIO CMD Configuration ------------------------*/  
361
  /* Get the SDIO CMD value */
362
  tmpreg = SDIO->CMD;
363
  /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */
364
  tmpreg &= CMD_CLEAR_MASK;
365
  /* Set CMDINDEX bits according to SDIO_CmdIndex value */
366
  /* Set WAITRESP bits according to SDIO_Response value */
367
  /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */
368
  /* Set CPSMEN bits according to SDIO_CPSM value */
369
  tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response
370
           | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM;
371
  
372
  /* Write to SDIO CMD */
373
  SDIO->CMD = tmpreg;
374
}
375

    
376
/**
377
  * @brief  Fills each SDIO_CmdInitStruct member with its default value.
378
  * @param  SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef 
379
  *         structure which will be initialized.
380
  * @retval None
381
  */
382
void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct)
383
{
384
  /* SDIO_CmdInitStruct members default value */
385
  SDIO_CmdInitStruct->SDIO_Argument = 0x00;
386
  SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00;
387
  SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No;
388
  SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No;
389
  SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable;
390
}
391

    
392
/**
393
  * @brief  Returns command index of last command for which response received.
394
  * @param  None
395
  * @retval Returns the command index of the last command response received.
396
  */
397
uint8_t SDIO_GetCommandResponse(void)
398
{
399
  return (uint8_t)(SDIO->RESPCMD);
400
}
401

    
402
/**
403
  * @brief  Returns response received from the card for the last command.
404
  * @param  SDIO_RESP: Specifies the SDIO response register. 
405
  *   This parameter can be one of the following values:
406
  *     @arg SDIO_RESP1: Response Register 1
407
  *     @arg SDIO_RESP2: Response Register 2
408
  *     @arg SDIO_RESP3: Response Register 3
409
  *     @arg SDIO_RESP4: Response Register 4
410
  * @retval The Corresponding response register value.
411
  */
412
uint32_t SDIO_GetResponse(uint32_t SDIO_RESP)
413
{
414
  __IO uint32_t tmp = 0;
415

    
416
  /* Check the parameters */
417
  assert_param(IS_SDIO_RESP(SDIO_RESP));
418

    
419
  tmp = SDIO_RESP_ADDR + SDIO_RESP;
420
  
421
  return (*(__IO uint32_t *) tmp); 
422
}
423

    
424
/**
425
  * @brief  Initializes the SDIO data path according to the specified 
426
  *   parameters in the SDIO_DataInitStruct.
427
  * @param  SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure that
428
  *   contains the configuration information for the SDIO command.
429
  * @retval None
430
  */
431
void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
432
{
433
  uint32_t tmpreg = 0;
434
  
435
  /* Check the parameters */
436
  assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength));
437
  assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize));
438
  assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir));
439
  assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode));
440
  assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM));
441

    
442
/*---------------------------- SDIO DTIMER Configuration ---------------------*/
443
  /* Set the SDIO Data TimeOut value */
444
  SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut;
445

    
446
/*---------------------------- SDIO DLEN Configuration -----------------------*/
447
  /* Set the SDIO DataLength value */
448
  SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength;
449

    
450
/*---------------------------- SDIO DCTRL Configuration ----------------------*/  
451
  /* Get the SDIO DCTRL value */
452
  tmpreg = SDIO->DCTRL;
453
  /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */
454
  tmpreg &= DCTRL_CLEAR_MASK;
455
  /* Set DEN bit according to SDIO_DPSM value */
456
  /* Set DTMODE bit according to SDIO_TransferMode value */
457
  /* Set DTDIR bit according to SDIO_TransferDir value */
458
  /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */
459
  tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir
460
           | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM;
461

    
462
  /* Write to SDIO DCTRL */
463
  SDIO->DCTRL = tmpreg;
464
}
465

    
466
/**
467
  * @brief  Fills each SDIO_DataInitStruct member with its default value.
468
  * @param  SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure which
469
  *         will be initialized.
470
  * @retval None
471
  */
472
void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
473
{
474
  /* SDIO_DataInitStruct members default value */
475
  SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF;
476
  SDIO_DataInitStruct->SDIO_DataLength = 0x00;
477
  SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b;
478
  SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard;
479
  SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block;  
480
  SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable;
481
}
482

    
483
/**
484
  * @brief  Returns number of remaining data bytes to be transferred.
485
  * @param  None
486
  * @retval Number of remaining data bytes to be transferred
487
  */
488
uint32_t SDIO_GetDataCounter(void)
489
{ 
490
  return SDIO->DCOUNT;
491
}
492

    
493
/**
494
  * @brief  Read one data word from Rx FIFO.
495
  * @param  None
496
  * @retval Data received
497
  */
498
uint32_t SDIO_ReadData(void)
499
{ 
500
  return SDIO->FIFO;
501
}
502

    
503
/**
504
  * @brief  Write one data word to Tx FIFO.
505
  * @param  Data: 32-bit data word to write.
506
  * @retval None
507
  */
508
void SDIO_WriteData(uint32_t Data)
509
{ 
510
  SDIO->FIFO = Data;
511
}
512

    
513
/**
514
  * @brief  Returns the number of words left to be written to or read from FIFO.        
515
  * @param  None
516
  * @retval Remaining number of words.
517
  */
518
uint32_t SDIO_GetFIFOCount(void)
519
{ 
520
  return SDIO->FIFOCNT;
521
}
522

    
523
/**
524
  * @brief  Starts the SD I/O Read Wait operation.        
525
  * @param  NewState: new state of the Start SDIO Read Wait operation. 
526
  *   This parameter can be: ENABLE or DISABLE.
527
  * @retval None
528
  */
529
void SDIO_StartSDIOReadWait(FunctionalState NewState)
530
{ 
531
  /* Check the parameters */
532
  assert_param(IS_FUNCTIONAL_STATE(NewState));
533
  
534
  *(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState;
535
}
536

    
537
/**
538
  * @brief  Stops the SD I/O Read Wait operation.        
539
  * @param  NewState: new state of the Stop SDIO Read Wait operation. 
540
  *   This parameter can be: ENABLE or DISABLE.
541
  * @retval None
542
  */
543
void SDIO_StopSDIOReadWait(FunctionalState NewState)
544
{ 
545
  /* Check the parameters */
546
  assert_param(IS_FUNCTIONAL_STATE(NewState));
547
  
548
  *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState;
549
}
550

    
551
/**
552
  * @brief  Sets one of the two options of inserting read wait interval.
553
  * @param  SDIO_ReadWaitMode: SD I/O Read Wait operation mode.
554
  *   This parameter can be:
555
  *     @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK
556
  *     @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2
557
  * @retval None
558
  */
559
void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)
560
{
561
  /* Check the parameters */
562
  assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));
563
  
564
  *(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode;
565
}
566

    
567
/**
568
  * @brief  Enables or disables the SD I/O Mode Operation.
569
  * @param  NewState: new state of SDIO specific operation. 
570
  *   This parameter can be: ENABLE or DISABLE.
571
  * @retval None
572
  */
573
void SDIO_SetSDIOOperation(FunctionalState NewState)
574
{ 
575
  /* Check the parameters */
576
  assert_param(IS_FUNCTIONAL_STATE(NewState));
577
  
578
  *(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState;
579
}
580

    
581
/**
582
  * @brief  Enables or disables the SD I/O Mode suspend command sending.
583
  * @param  NewState: new state of the SD I/O Mode suspend command.
584
  *   This parameter can be: ENABLE or DISABLE.
585
  * @retval None
586
  */
587
void SDIO_SendSDIOSuspendCmd(FunctionalState NewState)
588
{ 
589
  /* Check the parameters */
590
  assert_param(IS_FUNCTIONAL_STATE(NewState));
591
  
592
  *(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState;
593
}
594

    
595
/**
596
  * @brief  Enables or disables the command completion signal.
597
  * @param  NewState: new state of command completion signal. 
598
  *   This parameter can be: ENABLE or DISABLE.
599
  * @retval None
600
  */
601
void SDIO_CommandCompletionCmd(FunctionalState NewState)
602
{ 
603
  /* Check the parameters */
604
  assert_param(IS_FUNCTIONAL_STATE(NewState));
605
  
606
  *(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState;
607
}
608

    
609
/**
610
  * @brief  Enables or disables the CE-ATA interrupt.
611
  * @param  NewState: new state of CE-ATA interrupt. This parameter can be: ENABLE or DISABLE.
612
  * @retval None
613
  */
614
void SDIO_CEATAITCmd(FunctionalState NewState)
615
{ 
616
  /* Check the parameters */
617
  assert_param(IS_FUNCTIONAL_STATE(NewState));
618
  
619
  *(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1));
620
}
621

    
622
/**
623
  * @brief  Sends CE-ATA command (CMD61).
624
  * @param  NewState: new state of CE-ATA command. This parameter can be: ENABLE or DISABLE.
625
  * @retval None
626
  */
627
void SDIO_SendCEATACmd(FunctionalState NewState)
628
{ 
629
  /* Check the parameters */
630
  assert_param(IS_FUNCTIONAL_STATE(NewState));
631
  
632
  *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState;
633
}
634

    
635
/**
636
  * @brief  Checks whether the specified SDIO flag is set or not.
637
  * @param  SDIO_FLAG: specifies the flag to check. 
638
  *   This parameter can be one of the following values:
639
  *     @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
640
  *     @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
641
  *     @arg SDIO_FLAG_CTIMEOUT: Command response timeout
642
  *     @arg SDIO_FLAG_DTIMEOUT: Data timeout
643
  *     @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
644
  *     @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
645
  *     @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
646
  *     @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
647
  *     @arg SDIO_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
648
  *     @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide 
649
  *                              bus mode.
650
  *     @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
651
  *     @arg SDIO_FLAG_CMDACT:   Command transfer in progress
652
  *     @arg SDIO_FLAG_TXACT:    Data transmit in progress
653
  *     @arg SDIO_FLAG_RXACT:    Data receive in progress
654
  *     @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
655
  *     @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
656
  *     @arg SDIO_FLAG_TXFIFOF:  Transmit FIFO full
657
  *     @arg SDIO_FLAG_RXFIFOF:  Receive FIFO full
658
  *     @arg SDIO_FLAG_TXFIFOE:  Transmit FIFO empty
659
  *     @arg SDIO_FLAG_RXFIFOE:  Receive FIFO empty
660
  *     @arg SDIO_FLAG_TXDAVL:   Data available in transmit FIFO
661
  *     @arg SDIO_FLAG_RXDAVL:   Data available in receive FIFO
662
  *     @arg SDIO_FLAG_SDIOIT:   SD I/O interrupt received
663
  *     @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
664
  * @retval The new state of SDIO_FLAG (SET or RESET).
665
  */
666
FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG)
667
{ 
668
  FlagStatus bitstatus = RESET;
669
  
670
  /* Check the parameters */
671
  assert_param(IS_SDIO_FLAG(SDIO_FLAG));
672
  
673
  if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET)
674
  {
675
    bitstatus = SET;
676
  }
677
  else
678
  {
679
    bitstatus = RESET;
680
  }
681
  return bitstatus;
682
}
683

    
684
/**
685
  * @brief  Clears the SDIO's pending flags.
686
  * @param  SDIO_FLAG: specifies the flag to clear.  
687
  *   This parameter can be one or a combination of the following values:
688
  *     @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
689
  *     @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
690
  *     @arg SDIO_FLAG_CTIMEOUT: Command response timeout
691
  *     @arg SDIO_FLAG_DTIMEOUT: Data timeout
692
  *     @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
693
  *     @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
694
  *     @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
695
  *     @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
696
  *     @arg SDIO_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
697
  *     @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide 
698
  *                              bus mode
699
  *     @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
700
  *     @arg SDIO_FLAG_SDIOIT:   SD I/O interrupt received
701
  *     @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
702
  * @retval None
703
  */
704
void SDIO_ClearFlag(uint32_t SDIO_FLAG)
705
{ 
706
  /* Check the parameters */
707
  assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG));
708
   
709
  SDIO->ICR = SDIO_FLAG;
710
}
711

    
712
/**
713
  * @brief  Checks whether the specified SDIO interrupt has occurred or not.
714
  * @param  SDIO_IT: specifies the SDIO interrupt source to check. 
715
  *   This parameter can be one of the following values:
716
  *     @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
717
  *     @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
718
  *     @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
719
  *     @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
720
  *     @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
721
  *     @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
722
  *     @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
723
  *     @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
724
  *     @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
725
  *     @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
726
  *                            bus mode interrupt
727
  *     @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
728
  *     @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
729
  *     @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
730
  *     @arg SDIO_IT_RXACT:    Data receive in progress interrupt
731
  *     @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
732
  *     @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
733
  *     @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
734
  *     @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
735
  *     @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
736
  *     @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
737
  *     @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
738
  *     @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
739
  *     @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
740
  *     @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
741
  * @retval The new state of SDIO_IT (SET or RESET).
742
  */
743
ITStatus SDIO_GetITStatus(uint32_t SDIO_IT)
744
{ 
745
  ITStatus bitstatus = RESET;
746
  
747
  /* Check the parameters */
748
  assert_param(IS_SDIO_GET_IT(SDIO_IT));
749
  if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET)  
750
  {
751
    bitstatus = SET;
752
  }
753
  else
754
  {
755
    bitstatus = RESET;
756
  }
757
  return bitstatus;
758
}
759

    
760
/**
761
  * @brief  Clears the SDIO's interrupt pending bits.
762
  * @param  SDIO_IT: specifies the interrupt pending bit to clear. 
763
  *   This parameter can be one or a combination of the following values:
764
  *     @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
765
  *     @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
766
  *     @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
767
  *     @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
768
  *     @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
769
  *     @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
770
  *     @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
771
  *     @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
772
  *     @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
773
  *     @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
774
  *                            bus mode interrupt
775
  *     @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
776
  *     @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
777
  * @retval None
778
  */
779
void SDIO_ClearITPendingBit(uint32_t SDIO_IT)
780
{ 
781
  /* Check the parameters */
782
  assert_param(IS_SDIO_CLEAR_IT(SDIO_IT));
783
   
784
  SDIO->ICR = SDIO_IT;
785
}
786

    
787
/**
788
  * @}
789
  */
790

    
791
/**
792
  * @}
793
  */
794

    
795
/**
796
  * @}
797
  */
798

    
799
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/