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/**
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  ******************************************************************************
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  * @file    stm32f10x_fsmc.h
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  * @author  MCD Application Team
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  * @version V3.5.0
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  * @date    11-March-2011
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  * @brief   This file contains all the functions prototypes for the FSMC firmware 
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  *          library.
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  ******************************************************************************
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  * @attention
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  *
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  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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  *
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  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
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  ******************************************************************************
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  */
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32F10x_FSMC_H
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#define __STM32F10x_FSMC_H
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#ifdef __cplusplus
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 extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f10x.h"
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/** @addtogroup STM32F10x_StdPeriph_Driver
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  * @{
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  */
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/** @addtogroup FSMC
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  * @{
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  */
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/** @defgroup FSMC_Exported_Types
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  * @{
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  */
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/** 
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  * @brief  Timing parameters For NOR/SRAM Banks  
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  */
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typedef struct
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{
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  uint32_t FSMC_AddressSetupTime;       /*!< Defines the number of HCLK cycles to configure
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                                             the duration of the address setup time. 
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                                             This parameter can be a value between 0 and 0xF.
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                                             @note: It is not used with synchronous NOR Flash memories. */
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  uint32_t FSMC_AddressHoldTime;        /*!< Defines the number of HCLK cycles to configure
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                                             the duration of the address hold time.
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                                             This parameter can be a value between 0 and 0xF. 
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                                             @note: It is not used with synchronous NOR Flash memories.*/
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  uint32_t FSMC_DataSetupTime;          /*!< Defines the number of HCLK cycles to configure
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                                             the duration of the data setup time.
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                                             This parameter can be a value between 0 and 0xFF.
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                                             @note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
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  uint32_t FSMC_BusTurnAroundDuration;  /*!< Defines the number of HCLK cycles to configure
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                                             the duration of the bus turnaround.
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                                             This parameter can be a value between 0 and 0xF.
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                                             @note: It is only used for multiplexed NOR Flash memories. */
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  uint32_t FSMC_CLKDivision;            /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
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                                             This parameter can be a value between 1 and 0xF.
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                                             @note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
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  uint32_t FSMC_DataLatency;            /*!< Defines the number of memory clock cycles to issue
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                                             to the memory before getting the first data.
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                                             The value of this parameter depends on the memory type as shown below:
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                                              - It must be set to 0 in case of a CRAM
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                                              - It is don't care in asynchronous NOR, SRAM or ROM accesses
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                                              - It may assume a value between 0 and 0xF in NOR Flash memories
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                                                with synchronous burst mode enable */
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  uint32_t FSMC_AccessMode;             /*!< Specifies the asynchronous access mode. 
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                                             This parameter can be a value of @ref FSMC_Access_Mode */
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}FSMC_NORSRAMTimingInitTypeDef;
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/** 
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  * @brief  FSMC NOR/SRAM Init structure definition
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  */
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typedef struct
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{
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  uint32_t FSMC_Bank;                /*!< Specifies the NOR/SRAM memory bank that will be used.
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                                          This parameter can be a value of @ref FSMC_NORSRAM_Bank */
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  uint32_t FSMC_DataAddressMux;      /*!< Specifies whether the address and data values are
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                                          multiplexed on the databus or not. 
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                                          This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
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  uint32_t FSMC_MemoryType;          /*!< Specifies the type of external memory attached to
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                                          the corresponding memory bank.
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                                          This parameter can be a value of @ref FSMC_Memory_Type */
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  uint32_t FSMC_MemoryDataWidth;     /*!< Specifies the external memory device width.
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                                          This parameter can be a value of @ref FSMC_Data_Width */
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  uint32_t FSMC_BurstAccessMode;     /*!< Enables or disables the burst access mode for Flash memory,
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                                          valid only with synchronous burst Flash memories.
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                                          This parameter can be a value of @ref FSMC_Burst_Access_Mode */
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  uint32_t FSMC_AsynchronousWait;     /*!< Enables or disables wait signal during asynchronous transfers,
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                                          valid only with asynchronous Flash memories.
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                                          This parameter can be a value of @ref FSMC_AsynchronousWait */
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  uint32_t FSMC_WaitSignalPolarity;  /*!< Specifies the wait signal polarity, valid only when accessing
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                                          the Flash memory in burst mode.
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                                          This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
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  uint32_t FSMC_WrapMode;            /*!< Enables or disables the Wrapped burst access mode for Flash
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                                          memory, valid only when accessing Flash memories in burst mode.
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                                          This parameter can be a value of @ref FSMC_Wrap_Mode */
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  uint32_t FSMC_WaitSignalActive;    /*!< Specifies if the wait signal is asserted by the memory one
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                                          clock cycle before the wait state or during the wait state,
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                                          valid only when accessing memories in burst mode. 
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                                          This parameter can be a value of @ref FSMC_Wait_Timing */
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  uint32_t FSMC_WriteOperation;      /*!< Enables or disables the write operation in the selected bank by the FSMC. 
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                                          This parameter can be a value of @ref FSMC_Write_Operation */
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  uint32_t FSMC_WaitSignal;          /*!< Enables or disables the wait-state insertion via wait
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                                          signal, valid for Flash memory access in burst mode. 
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                                          This parameter can be a value of @ref FSMC_Wait_Signal */
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  uint32_t FSMC_ExtendedMode;        /*!< Enables or disables the extended mode.
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                                          This parameter can be a value of @ref FSMC_Extended_Mode */
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  uint32_t FSMC_WriteBurst;          /*!< Enables or disables the write burst operation.
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                                          This parameter can be a value of @ref FSMC_Write_Burst */ 
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  FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the  ExtendedMode is not used*/  
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  FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct;     /*!< Timing Parameters for write access if the  ExtendedMode is used*/      
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}FSMC_NORSRAMInitTypeDef;
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/** 
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  * @brief  Timing parameters For FSMC NAND and PCCARD Banks
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  */
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typedef struct
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{
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  uint32_t FSMC_SetupTime;      /*!< Defines the number of HCLK cycles to setup address before
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                                     the command assertion for NAND-Flash read or write access
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                                     to common/Attribute or I/O memory space (depending on
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                                     the memory space timing to be configured).
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                                     This parameter can be a value between 0 and 0xFF.*/
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  uint32_t FSMC_WaitSetupTime;  /*!< Defines the minimum number of HCLK cycles to assert the
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                                     command for NAND-Flash read or write access to
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                                     common/Attribute or I/O memory space (depending on the
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                                     memory space timing to be configured). 
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                                     This parameter can be a number between 0x00 and 0xFF */
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  uint32_t FSMC_HoldSetupTime;  /*!< Defines the number of HCLK clock cycles to hold address
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                                     (and data for write access) after the command deassertion
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                                     for NAND-Flash read or write access to common/Attribute
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                                     or I/O memory space (depending on the memory space timing
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                                     to be configured).
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                                     This parameter can be a number between 0x00 and 0xFF */
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  uint32_t FSMC_HiZSetupTime;   /*!< Defines the number of HCLK clock cycles during which the
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                                     databus is kept in HiZ after the start of a NAND-Flash
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                                     write access to common/Attribute or I/O memory space (depending
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                                     on the memory space timing to be configured).
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                                     This parameter can be a number between 0x00 and 0xFF */
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}FSMC_NAND_PCCARDTimingInitTypeDef;
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/** 
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  * @brief  FSMC NAND Init structure definition
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  */
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typedef struct
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{
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  uint32_t FSMC_Bank;              /*!< Specifies the NAND memory bank that will be used.
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                                      This parameter can be a value of @ref FSMC_NAND_Bank */
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  uint32_t FSMC_Waitfeature;      /*!< Enables or disables the Wait feature for the NAND Memory Bank.
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                                       This parameter can be any value of @ref FSMC_Wait_feature */
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  uint32_t FSMC_MemoryDataWidth;  /*!< Specifies the external memory device width.
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                                       This parameter can be any value of @ref FSMC_Data_Width */
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  uint32_t FSMC_ECC;              /*!< Enables or disables the ECC computation.
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                                       This parameter can be any value of @ref FSMC_ECC */
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  uint32_t FSMC_ECCPageSize;      /*!< Defines the page size for the extended ECC.
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                                       This parameter can be any value of @ref FSMC_ECC_Page_Size */
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  uint32_t FSMC_TCLRSetupTime;    /*!< Defines the number of HCLK cycles to configure the
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                                       delay between CLE low and RE low.
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                                       This parameter can be a value between 0 and 0xFF. */
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  uint32_t FSMC_TARSetupTime;     /*!< Defines the number of HCLK cycles to configure the
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                                       delay between ALE low and RE low.
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                                       This parameter can be a number between 0x0 and 0xFF */ 
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  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_CommonSpaceTimingStruct;   /*!< FSMC Common Space Timing */ 
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  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
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}FSMC_NANDInitTypeDef;
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/** 
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  * @brief  FSMC PCCARD Init structure definition
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  */
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typedef struct
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{
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  uint32_t FSMC_Waitfeature;    /*!< Enables or disables the Wait feature for the Memory Bank.
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                                    This parameter can be any value of @ref FSMC_Wait_feature */
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  uint32_t FSMC_TCLRSetupTime;  /*!< Defines the number of HCLK cycles to configure the
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                                     delay between CLE low and RE low.
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                                     This parameter can be a value between 0 and 0xFF. */
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  uint32_t FSMC_TARSetupTime;   /*!< Defines the number of HCLK cycles to configure the
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                                     delay between ALE low and RE low.
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                                     This parameter can be a number between 0x0 and 0xFF */ 
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  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
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  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_AttributeSpaceTimingStruct;  /*!< FSMC Attribute Space Timing */ 
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  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */  
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}FSMC_PCCARDInitTypeDef;
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/**
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  * @}
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  */
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/** @defgroup FSMC_Exported_Constants
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  * @{
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  */
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/** @defgroup FSMC_NORSRAM_Bank 
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  * @{
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  */
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#define FSMC_Bank1_NORSRAM1                             ((uint32_t)0x00000000)
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#define FSMC_Bank1_NORSRAM2                             ((uint32_t)0x00000002)
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#define FSMC_Bank1_NORSRAM3                             ((uint32_t)0x00000004)
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#define FSMC_Bank1_NORSRAM4                             ((uint32_t)0x00000006)
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/**
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  * @}
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  */
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/** @defgroup FSMC_NAND_Bank 
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  * @{
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  */  
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#define FSMC_Bank2_NAND                                 ((uint32_t)0x00000010)
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#define FSMC_Bank3_NAND                                 ((uint32_t)0x00000100)
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/**
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  * @}
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  */
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/** @defgroup FSMC_PCCARD_Bank 
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  * @{
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  */    
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#define FSMC_Bank4_PCCARD                               ((uint32_t)0x00001000)
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/**
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  * @}
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  */
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#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \
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                                    ((BANK) == FSMC_Bank1_NORSRAM2) || \
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                                    ((BANK) == FSMC_Bank1_NORSRAM3) || \
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                                    ((BANK) == FSMC_Bank1_NORSRAM4))
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#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
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                                 ((BANK) == FSMC_Bank3_NAND))
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#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
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                                    ((BANK) == FSMC_Bank3_NAND) || \
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                                    ((BANK) == FSMC_Bank4_PCCARD))
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#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
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                               ((BANK) == FSMC_Bank3_NAND) || \
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                               ((BANK) == FSMC_Bank4_PCCARD))
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/** @defgroup NOR_SRAM_Controller 
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  * @{
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  */
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/** @defgroup FSMC_Data_Address_Bus_Multiplexing 
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  * @{
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  */
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#define FSMC_DataAddressMux_Disable                       ((uint32_t)0x00000000)
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#define FSMC_DataAddressMux_Enable                        ((uint32_t)0x00000002)
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#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
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                          ((MUX) == FSMC_DataAddressMux_Enable))
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/**
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  * @}
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  */
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/** @defgroup FSMC_Memory_Type 
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  * @{
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  */
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#define FSMC_MemoryType_SRAM                            ((uint32_t)0x00000000)
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#define FSMC_MemoryType_PSRAM                           ((uint32_t)0x00000004)
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#define FSMC_MemoryType_NOR                             ((uint32_t)0x00000008)
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#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
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                                ((MEMORY) == FSMC_MemoryType_PSRAM)|| \
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                                ((MEMORY) == FSMC_MemoryType_NOR))
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/**
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  * @}
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  */
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/** @defgroup FSMC_Data_Width 
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  * @{
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  */
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#define FSMC_MemoryDataWidth_8b                         ((uint32_t)0x00000000)
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#define FSMC_MemoryDataWidth_16b                        ((uint32_t)0x00000010)
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#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
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                                     ((WIDTH) == FSMC_MemoryDataWidth_16b))
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/**
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  * @}
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  */
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/** @defgroup FSMC_Burst_Access_Mode 
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  * @{
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  */
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#define FSMC_BurstAccessMode_Disable                    ((uint32_t)0x00000000) 
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#define FSMC_BurstAccessMode_Enable                     ((uint32_t)0x00000100)
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#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
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                                  ((STATE) == FSMC_BurstAccessMode_Enable))
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/**
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  * @}
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  */
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/** @defgroup FSMC_AsynchronousWait 
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  * @{
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  */
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#define FSMC_AsynchronousWait_Disable                   ((uint32_t)0x00000000)
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#define FSMC_AsynchronousWait_Enable                    ((uint32_t)0x00008000)
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#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \
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                                 ((STATE) == FSMC_AsynchronousWait_Enable))
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/**
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  * @}
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  */
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/** @defgroup FSMC_Wait_Signal_Polarity 
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  * @{
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  */
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#define FSMC_WaitSignalPolarity_Low                     ((uint32_t)0x00000000)
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#define FSMC_WaitSignalPolarity_High                    ((uint32_t)0x00000200)
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#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
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                                         ((POLARITY) == FSMC_WaitSignalPolarity_High)) 
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/**
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  * @}
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  */
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/** @defgroup FSMC_Wrap_Mode 
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  * @{
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  */
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#define FSMC_WrapMode_Disable                           ((uint32_t)0x00000000)
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#define FSMC_WrapMode_Enable                            ((uint32_t)0x00000400) 
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#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
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                                 ((MODE) == FSMC_WrapMode_Enable))
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/**
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  * @}
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  */
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/** @defgroup FSMC_Wait_Timing 
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  * @{
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  */
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#define FSMC_WaitSignalActive_BeforeWaitState           ((uint32_t)0x00000000)
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#define FSMC_WaitSignalActive_DuringWaitState           ((uint32_t)0x00000800) 
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#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
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                                            ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
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/**
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  * @}
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  */
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/** @defgroup FSMC_Write_Operation 
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  * @{
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  */
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#define FSMC_WriteOperation_Disable                     ((uint32_t)0x00000000)
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#define FSMC_WriteOperation_Enable                      ((uint32_t)0x00001000)
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#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
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                                            ((OPERATION) == FSMC_WriteOperation_Enable))
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/**
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  * @}
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  */
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/** @defgroup FSMC_Wait_Signal 
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  * @{
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  */
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#define FSMC_WaitSignal_Disable                         ((uint32_t)0x00000000)
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#define FSMC_WaitSignal_Enable                          ((uint32_t)0x00002000) 
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#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
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                                      ((SIGNAL) == FSMC_WaitSignal_Enable))
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/**
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  * @}
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  */
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/** @defgroup FSMC_Extended_Mode 
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  * @{
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  */
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#define FSMC_ExtendedMode_Disable                       ((uint32_t)0x00000000)
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#define FSMC_ExtendedMode_Enable                        ((uint32_t)0x00004000)
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#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
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                                     ((MODE) == FSMC_ExtendedMode_Enable)) 
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/**
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  * @}
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  */
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/** @defgroup FSMC_Write_Burst 
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  * @{
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  */
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#define FSMC_WriteBurst_Disable                         ((uint32_t)0x00000000)
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#define FSMC_WriteBurst_Enable                          ((uint32_t)0x00080000) 
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#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
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                                    ((BURST) == FSMC_WriteBurst_Enable))
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/**
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  * @}
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  */
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/** @defgroup FSMC_Address_Setup_Time 
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  * @{
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  */
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#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
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/**
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  * @}
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  */
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/** @defgroup FSMC_Address_Hold_Time 
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  * @{
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  */
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#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
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/**
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  * @}
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  */
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/** @defgroup FSMC_Data_Setup_Time 
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  * @{
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  */
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#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
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/**
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  * @}
477
  */
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/** @defgroup FSMC_Bus_Turn_around_Duration 
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  * @{
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  */
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#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
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/**
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  * @}
487
  */
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/** @defgroup FSMC_CLK_Division 
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  * @{
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  */
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#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
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/**
496
  * @}
497
  */
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/** @defgroup FSMC_Data_Latency 
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  * @{
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  */
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#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
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/**
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  * @}
507
  */
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/** @defgroup FSMC_Access_Mode 
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  * @{
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  */
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#define FSMC_AccessMode_A                               ((uint32_t)0x00000000)
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#define FSMC_AccessMode_B                               ((uint32_t)0x10000000) 
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#define FSMC_AccessMode_C                               ((uint32_t)0x20000000)
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#define FSMC_AccessMode_D                               ((uint32_t)0x30000000)
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#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \
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                                   ((MODE) == FSMC_AccessMode_B) || \
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                                   ((MODE) == FSMC_AccessMode_C) || \
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                                   ((MODE) == FSMC_AccessMode_D)) 
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/**
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  * @}
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  */
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/**
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  * @}
528
  */
529
  
530
/** @defgroup NAND_PCCARD_Controller 
531
  * @{
532
  */
533

    
534
/** @defgroup FSMC_Wait_feature 
535
  * @{
536
  */
537

    
538
#define FSMC_Waitfeature_Disable                        ((uint32_t)0x00000000)
539
#define FSMC_Waitfeature_Enable                         ((uint32_t)0x00000002)
540
#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \
541
                                       ((FEATURE) == FSMC_Waitfeature_Enable))
542

    
543
/**
544
  * @}
545
  */
546

    
547

    
548
/** @defgroup FSMC_ECC 
549
  * @{
550
  */
551

    
552
#define FSMC_ECC_Disable                                ((uint32_t)0x00000000)
553
#define FSMC_ECC_Enable                                 ((uint32_t)0x00000040)
554
#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \
555
                                  ((STATE) == FSMC_ECC_Enable))
556

    
557
/**
558
  * @}
559
  */
560

    
561
/** @defgroup FSMC_ECC_Page_Size 
562
  * @{
563
  */
564

    
565
#define FSMC_ECCPageSize_256Bytes                       ((uint32_t)0x00000000)
566
#define FSMC_ECCPageSize_512Bytes                       ((uint32_t)0x00020000)
567
#define FSMC_ECCPageSize_1024Bytes                      ((uint32_t)0x00040000)
568
#define FSMC_ECCPageSize_2048Bytes                      ((uint32_t)0x00060000)
569
#define FSMC_ECCPageSize_4096Bytes                      ((uint32_t)0x00080000)
570
#define FSMC_ECCPageSize_8192Bytes                      ((uint32_t)0x000A0000)
571
#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \
572
                                    ((SIZE) == FSMC_ECCPageSize_512Bytes) || \
573
                                    ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \
574
                                    ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \
575
                                    ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \
576
                                    ((SIZE) == FSMC_ECCPageSize_8192Bytes))
577

    
578
/**
579
  * @}
580
  */
581

    
582
/** @defgroup FSMC_TCLR_Setup_Time 
583
  * @{
584
  */
585

    
586
#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)
587

    
588
/**
589
  * @}
590
  */
591

    
592
/** @defgroup FSMC_TAR_Setup_Time 
593
  * @{
594
  */
595

    
596
#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)
597

    
598
/**
599
  * @}
600
  */
601

    
602
/** @defgroup FSMC_Setup_Time 
603
  * @{
604
  */
605

    
606
#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)
607

    
608
/**
609
  * @}
610
  */
611

    
612
/** @defgroup FSMC_Wait_Setup_Time 
613
  * @{
614
  */
615

    
616
#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)
617

    
618
/**
619
  * @}
620
  */
621

    
622
/** @defgroup FSMC_Hold_Setup_Time 
623
  * @{
624
  */
625

    
626
#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)
627

    
628
/**
629
  * @}
630
  */
631

    
632
/** @defgroup FSMC_HiZ_Setup_Time 
633
  * @{
634
  */
635

    
636
#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)
637

    
638
/**
639
  * @}
640
  */
641

    
642
/** @defgroup FSMC_Interrupt_sources 
643
  * @{
644
  */
645

    
646
#define FSMC_IT_RisingEdge                              ((uint32_t)0x00000008)
647
#define FSMC_IT_Level                                   ((uint32_t)0x00000010)
648
#define FSMC_IT_FallingEdge                             ((uint32_t)0x00000020)
649
#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))
650
#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \
651
                            ((IT) == FSMC_IT_Level) || \
652
                            ((IT) == FSMC_IT_FallingEdge)) 
653
/**
654
  * @}
655
  */
656

    
657
/** @defgroup FSMC_Flags 
658
  * @{
659
  */
660

    
661
#define FSMC_FLAG_RisingEdge                            ((uint32_t)0x00000001)
662
#define FSMC_FLAG_Level                                 ((uint32_t)0x00000002)
663
#define FSMC_FLAG_FallingEdge                           ((uint32_t)0x00000004)
664
#define FSMC_FLAG_FEMPT                                 ((uint32_t)0x00000040)
665
#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \
666
                                ((FLAG) == FSMC_FLAG_Level) || \
667
                                ((FLAG) == FSMC_FLAG_FallingEdge) || \
668
                                ((FLAG) == FSMC_FLAG_FEMPT))
669

    
670
#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
671

    
672
/**
673
  * @}
674
  */
675

    
676
/**
677
  * @}
678
  */
679

    
680
/**
681
  * @}
682
  */
683

    
684
/** @defgroup FSMC_Exported_Macros
685
  * @{
686
  */
687

    
688
/**
689
  * @}
690
  */
691

    
692
/** @defgroup FSMC_Exported_Functions
693
  * @{
694
  */
695

    
696
void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
697
void FSMC_NANDDeInit(uint32_t FSMC_Bank);
698
void FSMC_PCCARDDeInit(void);
699
void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
700
void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
701
void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
702
void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
703
void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
704
void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
705
void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
706
void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);
707
void FSMC_PCCARDCmd(FunctionalState NewState);
708
void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);
709
uint32_t FSMC_GetECC(uint32_t FSMC_Bank);
710
void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);
711
FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
712
void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
713
ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT);
714
void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);
715

    
716
#ifdef __cplusplus
717
}
718
#endif
719

    
720
#endif /*__STM32F10x_FSMC_H */
721
/**
722
  * @}
723
  */
724

    
725
/**
726
  * @}
727
  */
728

    
729
/**
730
  * @}
731
  */ 
732

    
733
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/