amiro-blt / Target / Modules / LightRing_1-0 / Boot / lib / STM32F10x_StdPeriph_Driver / src / stm32f10x_dma.c @ 367c0652
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/**
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******************************************************************************
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* @file stm32f10x_dma.c
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* @author MCD Application Team
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* @version V3.5.0
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* @date 11-March-2011
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* @brief This file provides all the DMA firmware functions.
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******************************************************************************
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* @attention
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*
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*
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* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f10x_dma.h" |
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#include "stm32f10x_rcc.h" |
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/** @addtogroup STM32F10x_StdPeriph_Driver
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* @{
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*/
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/** @defgroup DMA
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* @brief DMA driver modules
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* @{
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*/
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/** @defgroup DMA_Private_TypesDefinitions
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup DMA_Private_Defines
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* @{
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*/
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/* DMA1 Channelx interrupt pending bit masks */
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#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
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#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
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#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
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#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
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#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
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#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6))
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#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7))
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/* DMA2 Channelx interrupt pending bit masks */
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#define DMA2_Channel1_IT_Mask ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
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#define DMA2_Channel2_IT_Mask ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
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#define DMA2_Channel3_IT_Mask ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
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#define DMA2_Channel4_IT_Mask ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
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#define DMA2_Channel5_IT_Mask ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
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/* DMA2 FLAG mask */
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#define FLAG_Mask ((uint32_t)0x10000000) |
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/* DMA registers Masks */
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#define CCR_CLEAR_Mask ((uint32_t)0xFFFF800F) |
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/**
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* @}
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*/
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/** @defgroup DMA_Private_Macros
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup DMA_Private_Variables
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup DMA_Private_FunctionPrototypes
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup DMA_Private_Functions
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* @{
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*/
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/**
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* @brief Deinitializes the DMAy Channelx registers to their default reset
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* values.
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* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
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* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
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* @retval None
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*/
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void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
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{
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/* Check the parameters */
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assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); |
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/* Disable the selected DMAy Channelx */
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DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN); |
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/* Reset DMAy Channelx control register */
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DMAy_Channelx->CCR = 0;
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/* Reset DMAy Channelx remaining bytes register */
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DMAy_Channelx->CNDTR = 0;
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/* Reset DMAy Channelx peripheral address register */
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DMAy_Channelx->CPAR = 0;
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/* Reset DMAy Channelx memory address register */
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DMAy_Channelx->CMAR = 0;
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if (DMAy_Channelx == DMA1_Channel1)
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{
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/* Reset interrupt pending bits for DMA1 Channel1 */
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DMA1->IFCR |= DMA1_Channel1_IT_Mask; |
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} |
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else if (DMAy_Channelx == DMA1_Channel2) |
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{
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/* Reset interrupt pending bits for DMA1 Channel2 */
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DMA1->IFCR |= DMA1_Channel2_IT_Mask; |
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} |
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else if (DMAy_Channelx == DMA1_Channel3) |
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{
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/* Reset interrupt pending bits for DMA1 Channel3 */
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DMA1->IFCR |= DMA1_Channel3_IT_Mask; |
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} |
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else if (DMAy_Channelx == DMA1_Channel4) |
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{
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/* Reset interrupt pending bits for DMA1 Channel4 */
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DMA1->IFCR |= DMA1_Channel4_IT_Mask; |
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} |
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else if (DMAy_Channelx == DMA1_Channel5) |
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{
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/* Reset interrupt pending bits for DMA1 Channel5 */
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DMA1->IFCR |= DMA1_Channel5_IT_Mask; |
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} |
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else if (DMAy_Channelx == DMA1_Channel6) |
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{
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/* Reset interrupt pending bits for DMA1 Channel6 */
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DMA1->IFCR |= DMA1_Channel6_IT_Mask; |
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} |
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else if (DMAy_Channelx == DMA1_Channel7) |
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{
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/* Reset interrupt pending bits for DMA1 Channel7 */
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DMA1->IFCR |= DMA1_Channel7_IT_Mask; |
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} |
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else if (DMAy_Channelx == DMA2_Channel1) |
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{
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/* Reset interrupt pending bits for DMA2 Channel1 */
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DMA2->IFCR |= DMA2_Channel1_IT_Mask; |
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} |
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else if (DMAy_Channelx == DMA2_Channel2) |
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{
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/* Reset interrupt pending bits for DMA2 Channel2 */
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DMA2->IFCR |= DMA2_Channel2_IT_Mask; |
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} |
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else if (DMAy_Channelx == DMA2_Channel3) |
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{
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/* Reset interrupt pending bits for DMA2 Channel3 */
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DMA2->IFCR |= DMA2_Channel3_IT_Mask; |
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} |
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else if (DMAy_Channelx == DMA2_Channel4) |
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{
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/* Reset interrupt pending bits for DMA2 Channel4 */
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DMA2->IFCR |= DMA2_Channel4_IT_Mask; |
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} |
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else
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{
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if (DMAy_Channelx == DMA2_Channel5)
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{
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/* Reset interrupt pending bits for DMA2 Channel5 */
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DMA2->IFCR |= DMA2_Channel5_IT_Mask; |
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} |
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} |
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} |
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/**
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* @brief Initializes the DMAy Channelx according to the specified
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* parameters in the DMA_InitStruct.
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* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
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* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
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* @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that
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* contains the configuration information for the specified DMA Channel.
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* @retval None
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*/
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void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
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{
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uint32_t tmpreg = 0;
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/* Check the parameters */
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assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); |
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assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR)); |
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assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize)); |
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assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc)); |
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assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc)); |
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assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize)); |
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assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize)); |
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assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode)); |
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assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority)); |
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assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M)); |
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/*--------------------------- DMAy Channelx CCR Configuration -----------------*/
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/* Get the DMAy_Channelx CCR value */
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tmpreg = DMAy_Channelx->CCR; |
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/* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
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tmpreg &= CCR_CLEAR_Mask; |
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/* Configure DMAy Channelx: data transfer, data size, priority level and mode */
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/* Set DIR bit according to DMA_DIR value */
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/* Set CIRC bit according to DMA_Mode value */
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/* Set PINC bit according to DMA_PeripheralInc value */
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/* Set MINC bit according to DMA_MemoryInc value */
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/* Set PSIZE bits according to DMA_PeripheralDataSize value */
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/* Set MSIZE bits according to DMA_MemoryDataSize value */
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/* Set PL bits according to DMA_Priority value */
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/* Set the MEM2MEM bit according to DMA_M2M value */
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tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | |
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DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | |
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DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | |
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DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; |
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/* Write to DMAy Channelx CCR */
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DMAy_Channelx->CCR = tmpreg; |
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/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
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/* Write to DMAy Channelx CNDTR */
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DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize; |
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/*--------------------------- DMAy Channelx CPAR Configuration ----------------*/
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/* Write to DMAy Channelx CPAR */
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DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr; |
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/*--------------------------- DMAy Channelx CMAR Configuration ----------------*/
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/* Write to DMAy Channelx CMAR */
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DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr; |
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} |
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/**
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* @brief Fills each DMA_InitStruct member with its default value.
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* @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will
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* be initialized.
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* @retval None
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*/
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void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
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{
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/*-------------- Reset DMA init structure parameters values ------------------*/
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/* Initialize the DMA_PeripheralBaseAddr member */
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DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
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/* Initialize the DMA_MemoryBaseAddr member */
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DMA_InitStruct->DMA_MemoryBaseAddr = 0;
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/* Initialize the DMA_DIR member */
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DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; |
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/* Initialize the DMA_BufferSize member */
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DMA_InitStruct->DMA_BufferSize = 0;
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/* Initialize the DMA_PeripheralInc member */
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DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; |
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/* Initialize the DMA_MemoryInc member */
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DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; |
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/* Initialize the DMA_PeripheralDataSize member */
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DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; |
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/* Initialize the DMA_MemoryDataSize member */
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DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; |
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/* Initialize the DMA_Mode member */
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DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; |
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/* Initialize the DMA_Priority member */
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DMA_InitStruct->DMA_Priority = DMA_Priority_Low; |
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/* Initialize the DMA_M2M member */
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DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; |
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} |
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/**
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* @brief Enables or disables the specified DMAy Channelx.
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* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
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* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
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* @param NewState: new state of the DMAy Channelx.
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* This parameter can be: ENABLE or DISABLE.
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* @retval None
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*/
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void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
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{
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/* Check the parameters */
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assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); |
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assert_param(IS_FUNCTIONAL_STATE(NewState)); |
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if (NewState != DISABLE)
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{
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/* Enable the selected DMAy Channelx */
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DMAy_Channelx->CCR |= DMA_CCR1_EN; |
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} |
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else
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{
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/* Disable the selected DMAy Channelx */
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DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN); |
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} |
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} |
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/**
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* @brief Enables or disables the specified DMAy Channelx interrupts.
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* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
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* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
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* @param DMA_IT: specifies the DMA interrupts sources to be enabled
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* or disabled.
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* This parameter can be any combination of the following values:
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* @arg DMA_IT_TC: Transfer complete interrupt mask
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* @arg DMA_IT_HT: Half transfer interrupt mask
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* @arg DMA_IT_TE: Transfer error interrupt mask
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* @param NewState: new state of the specified DMA interrupts.
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* This parameter can be: ENABLE or DISABLE.
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* @retval None
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*/
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void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
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{
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/* Check the parameters */
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assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); |
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assert_param(IS_DMA_CONFIG_IT(DMA_IT)); |
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assert_param(IS_FUNCTIONAL_STATE(NewState)); |
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if (NewState != DISABLE)
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{
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/* Enable the selected DMA interrupts */
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DMAy_Channelx->CCR |= DMA_IT; |
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} |
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else
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{
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/* Disable the selected DMA interrupts */
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DMAy_Channelx->CCR &= ~DMA_IT; |
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} |
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} |
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/**
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* @brief Sets the number of data units in the current DMAy Channelx transfer.
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* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
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* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
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* @param DataNumber: The number of data units in the current DMAy Channelx
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* transfer.
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* @note This function can only be used when the DMAy_Channelx is disabled.
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* @retval None.
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*/
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void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)
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{
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/* Check the parameters */
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assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); |
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/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
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/* Write to DMAy Channelx CNDTR */
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DMAy_Channelx->CNDTR = DataNumber; |
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} |
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/**
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* @brief Returns the number of remaining data units in the current
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* DMAy Channelx transfer.
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* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
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* x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
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* @retval The number of remaining data units in the current DMAy Channelx
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* transfer.
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*/
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uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx) |
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{
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/* Check the parameters */
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assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); |
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/* Return the number of remaining data units for DMAy Channelx */
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return ((uint16_t)(DMAy_Channelx->CNDTR));
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} |
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/**
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* @brief Checks whether the specified DMAy Channelx flag is set or not.
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* @param DMAy_FLAG: specifies the flag to check.
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* This parameter can be one of the following values:
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* @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
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* @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
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* @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
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* @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
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* @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
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* @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
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* @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
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* @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
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* @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
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* @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
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* @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
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* @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
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* @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
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* @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
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* @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
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* @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
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* @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
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* @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
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* @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
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* @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
|
| 403 |
* @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
|
| 404 |
* @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
|
| 405 |
* @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
|
| 406 |
* @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
|
| 407 |
* @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
|
| 408 |
* @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
|
| 409 |
* @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
|
| 410 |
* @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
|
| 411 |
* @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
|
| 412 |
* @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
|
| 413 |
* @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
|
| 414 |
* @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
|
| 415 |
* @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
|
| 416 |
* @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
|
| 417 |
* @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
|
| 418 |
* @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
|
| 419 |
* @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
|
| 420 |
* @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
|
| 421 |
* @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
|
| 422 |
* @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
|
| 423 |
* @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
|
| 424 |
* @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
|
| 425 |
* @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
|
| 426 |
* @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
|
| 427 |
* @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
|
| 428 |
* @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
|
| 429 |
* @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
|
| 430 |
* @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
|
| 431 |
* @retval The new state of DMAy_FLAG (SET or RESET).
|
| 432 |
*/
|
| 433 |
FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG) |
| 434 |
{
|
| 435 |
FlagStatus bitstatus = RESET; |
| 436 |
uint32_t tmpreg = 0;
|
| 437 |
|
| 438 |
/* Check the parameters */
|
| 439 |
assert_param(IS_DMA_GET_FLAG(DMAy_FLAG)); |
| 440 |
|
| 441 |
/* Calculate the used DMAy */
|
| 442 |
if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
|
| 443 |
{
|
| 444 |
/* Get DMA2 ISR register value */
|
| 445 |
tmpreg = DMA2->ISR ; |
| 446 |
} |
| 447 |
else
|
| 448 |
{
|
| 449 |
/* Get DMA1 ISR register value */
|
| 450 |
tmpreg = DMA1->ISR ; |
| 451 |
} |
| 452 |
|
| 453 |
/* Check the status of the specified DMAy flag */
|
| 454 |
if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET)
|
| 455 |
{
|
| 456 |
/* DMAy_FLAG is set */
|
| 457 |
bitstatus = SET; |
| 458 |
} |
| 459 |
else
|
| 460 |
{
|
| 461 |
/* DMAy_FLAG is reset */
|
| 462 |
bitstatus = RESET; |
| 463 |
} |
| 464 |
|
| 465 |
/* Return the DMAy_FLAG status */
|
| 466 |
return bitstatus;
|
| 467 |
} |
| 468 |
|
| 469 |
/**
|
| 470 |
* @brief Clears the DMAy Channelx's pending flags.
|
| 471 |
* @param DMAy_FLAG: specifies the flag to clear.
|
| 472 |
* This parameter can be any combination (for the same DMA) of the following values:
|
| 473 |
* @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
|
| 474 |
* @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
|
| 475 |
* @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
|
| 476 |
* @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
|
| 477 |
* @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
|
| 478 |
* @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
|
| 479 |
* @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
|
| 480 |
* @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
|
| 481 |
* @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
|
| 482 |
* @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
|
| 483 |
* @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
|
| 484 |
* @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
|
| 485 |
* @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
|
| 486 |
* @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
|
| 487 |
* @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
|
| 488 |
* @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
|
| 489 |
* @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
|
| 490 |
* @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
|
| 491 |
* @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
|
| 492 |
* @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
|
| 493 |
* @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
|
| 494 |
* @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
|
| 495 |
* @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
|
| 496 |
* @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
|
| 497 |
* @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
|
| 498 |
* @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
|
| 499 |
* @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
|
| 500 |
* @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
|
| 501 |
* @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
|
| 502 |
* @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
|
| 503 |
* @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
|
| 504 |
* @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
|
| 505 |
* @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
|
| 506 |
* @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
|
| 507 |
* @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
|
| 508 |
* @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
|
| 509 |
* @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
|
| 510 |
* @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
|
| 511 |
* @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
|
| 512 |
* @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
|
| 513 |
* @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
|
| 514 |
* @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
|
| 515 |
* @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
|
| 516 |
* @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
|
| 517 |
* @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
|
| 518 |
* @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
|
| 519 |
* @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
|
| 520 |
* @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
|
| 521 |
* @retval None
|
| 522 |
*/
|
| 523 |
void DMA_ClearFlag(uint32_t DMAy_FLAG)
|
| 524 |
{
|
| 525 |
/* Check the parameters */
|
| 526 |
assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG)); |
| 527 |
|
| 528 |
/* Calculate the used DMAy */
|
| 529 |
if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
|
| 530 |
{
|
| 531 |
/* Clear the selected DMAy flags */
|
| 532 |
DMA2->IFCR = DMAy_FLAG; |
| 533 |
} |
| 534 |
else
|
| 535 |
{
|
| 536 |
/* Clear the selected DMAy flags */
|
| 537 |
DMA1->IFCR = DMAy_FLAG; |
| 538 |
} |
| 539 |
} |
| 540 |
|
| 541 |
/**
|
| 542 |
* @brief Checks whether the specified DMAy Channelx interrupt has occurred or not.
|
| 543 |
* @param DMAy_IT: specifies the DMAy interrupt source to check.
|
| 544 |
* This parameter can be one of the following values:
|
| 545 |
* @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
|
| 546 |
* @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
|
| 547 |
* @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
|
| 548 |
* @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
|
| 549 |
* @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
|
| 550 |
* @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
|
| 551 |
* @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
|
| 552 |
* @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
|
| 553 |
* @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
|
| 554 |
* @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
|
| 555 |
* @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
|
| 556 |
* @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
|
| 557 |
* @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
|
| 558 |
* @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
|
| 559 |
* @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
|
| 560 |
* @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
|
| 561 |
* @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
|
| 562 |
* @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
|
| 563 |
* @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
|
| 564 |
* @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
|
| 565 |
* @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
|
| 566 |
* @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
|
| 567 |
* @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
|
| 568 |
* @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
|
| 569 |
* @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
|
| 570 |
* @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
|
| 571 |
* @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
|
| 572 |
* @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
|
| 573 |
* @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
|
| 574 |
* @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
|
| 575 |
* @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
|
| 576 |
* @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
|
| 577 |
* @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
|
| 578 |
* @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
|
| 579 |
* @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
|
| 580 |
* @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
|
| 581 |
* @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
|
| 582 |
* @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
|
| 583 |
* @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
|
| 584 |
* @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
|
| 585 |
* @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
|
| 586 |
* @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
|
| 587 |
* @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
|
| 588 |
* @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
|
| 589 |
* @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
|
| 590 |
* @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
|
| 591 |
* @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
|
| 592 |
* @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
|
| 593 |
* @retval The new state of DMAy_IT (SET or RESET).
|
| 594 |
*/
|
| 595 |
ITStatus DMA_GetITStatus(uint32_t DMAy_IT) |
| 596 |
{
|
| 597 |
ITStatus bitstatus = RESET; |
| 598 |
uint32_t tmpreg = 0;
|
| 599 |
|
| 600 |
/* Check the parameters */
|
| 601 |
assert_param(IS_DMA_GET_IT(DMAy_IT)); |
| 602 |
|
| 603 |
/* Calculate the used DMA */
|
| 604 |
if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
|
| 605 |
{
|
| 606 |
/* Get DMA2 ISR register value */
|
| 607 |
tmpreg = DMA2->ISR; |
| 608 |
} |
| 609 |
else
|
| 610 |
{
|
| 611 |
/* Get DMA1 ISR register value */
|
| 612 |
tmpreg = DMA1->ISR; |
| 613 |
} |
| 614 |
|
| 615 |
/* Check the status of the specified DMAy interrupt */
|
| 616 |
if ((tmpreg & DMAy_IT) != (uint32_t)RESET)
|
| 617 |
{
|
| 618 |
/* DMAy_IT is set */
|
| 619 |
bitstatus = SET; |
| 620 |
} |
| 621 |
else
|
| 622 |
{
|
| 623 |
/* DMAy_IT is reset */
|
| 624 |
bitstatus = RESET; |
| 625 |
} |
| 626 |
/* Return the DMA_IT status */
|
| 627 |
return bitstatus;
|
| 628 |
} |
| 629 |
|
| 630 |
/**
|
| 631 |
* @brief Clears the DMAy Channelx's interrupt pending bits.
|
| 632 |
* @param DMAy_IT: specifies the DMAy interrupt pending bit to clear.
|
| 633 |
* This parameter can be any combination (for the same DMA) of the following values:
|
| 634 |
* @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
|
| 635 |
* @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
|
| 636 |
* @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
|
| 637 |
* @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
|
| 638 |
* @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
|
| 639 |
* @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
|
| 640 |
* @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
|
| 641 |
* @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
|
| 642 |
* @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
|
| 643 |
* @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
|
| 644 |
* @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
|
| 645 |
* @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
|
| 646 |
* @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
|
| 647 |
* @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
|
| 648 |
* @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
|
| 649 |
* @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
|
| 650 |
* @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
|
| 651 |
* @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
|
| 652 |
* @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
|
| 653 |
* @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
|
| 654 |
* @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
|
| 655 |
* @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
|
| 656 |
* @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
|
| 657 |
* @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
|
| 658 |
* @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
|
| 659 |
* @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
|
| 660 |
* @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
|
| 661 |
* @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
|
| 662 |
* @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
|
| 663 |
* @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
|
| 664 |
* @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
|
| 665 |
* @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
|
| 666 |
* @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
|
| 667 |
* @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
|
| 668 |
* @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
|
| 669 |
* @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
|
| 670 |
* @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
|
| 671 |
* @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
|
| 672 |
* @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
|
| 673 |
* @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
|
| 674 |
* @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
|
| 675 |
* @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
|
| 676 |
* @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
|
| 677 |
* @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
|
| 678 |
* @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
|
| 679 |
* @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
|
| 680 |
* @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
|
| 681 |
* @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
|
| 682 |
* @retval None
|
| 683 |
*/
|
| 684 |
void DMA_ClearITPendingBit(uint32_t DMAy_IT)
|
| 685 |
{
|
| 686 |
/* Check the parameters */
|
| 687 |
assert_param(IS_DMA_CLEAR_IT(DMAy_IT)); |
| 688 |
|
| 689 |
/* Calculate the used DMAy */
|
| 690 |
if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
|
| 691 |
{
|
| 692 |
/* Clear the selected DMAy interrupt pending bits */
|
| 693 |
DMA2->IFCR = DMAy_IT; |
| 694 |
} |
| 695 |
else
|
| 696 |
{
|
| 697 |
/* Clear the selected DMAy interrupt pending bits */
|
| 698 |
DMA1->IFCR = DMAy_IT; |
| 699 |
} |
| 700 |
} |
| 701 |
|
| 702 |
/**
|
| 703 |
* @}
|
| 704 |
*/
|
| 705 |
|
| 706 |
/**
|
| 707 |
* @}
|
| 708 |
*/
|
| 709 |
|
| 710 |
/**
|
| 711 |
* @}
|
| 712 |
*/
|
| 713 |
|
| 714 |
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|