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/**
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  ******************************************************************************
3
  * @file    system_stm32f4xx.c
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  * @author  MCD Application Team
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  * @version V1.1.0
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  * @date    24-May-2013
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  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
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  *          This file contains the system clock configuration for STM32F4xx devices,
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  *          and is generated by the clock configuration tool
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  *          stm32f4xx_Clock_Configuration_V1.1.0.xls
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  *             
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  * 1.  This file provides two functions and one global variable to be called from 
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  *     user application:
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  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
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  *                      and Divider factors, AHB/APBx prescalers and Flash settings),
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  *                      depending on the configuration made in the clock xls tool. 
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  *                      This function is called at startup just after reset and 
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  *                      before branch to main program. This call is made inside
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  *                      the "startup_stm32f4xx.s" file.
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  *
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  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
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  *                                  by the user application to setup the SysTick 
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  *                                  timer or configure other parameters.
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  *                                     
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  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
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  *                                 be called whenever the core clock is changed
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  *                                 during program execution.
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  *
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  * 2. After each device reset the HSI (16 MHz) is used as system clock source.
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  *    Then SystemInit() function is called, in "startup_stm32f4xx.s" file, to
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  *    configure the system clock before to branch to main program.
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  *
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  * 3. If the system clock source selected by user fails to startup, the SystemInit()
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  *    function will do nothing and HSI still used as system clock source. User can 
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  *    add some code to deal with this issue inside the SetSysClock() function.
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  *
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  * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define
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  *    in "stm32f4xx.h" file. When HSE is used as system clock source, directly or
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  *    through PLL, and you are using different crystal you have to adapt the HSE
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  *    value to your own configuration.
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  *
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  * 5. This file configures the system clock as follows:
43
  *=============================================================================
44
  *=============================================================================
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  *        Supported STM32F40xx/41xx/427x/437x devices
46
  *-----------------------------------------------------------------------------
47
  *        System Clock source                    | PLL (HSE)
48
  *-----------------------------------------------------------------------------
49
  *        SYSCLK(Hz)                             | 168000000
50
  *-----------------------------------------------------------------------------
51
  *        HCLK(Hz)                               | 168000000
52
  *-----------------------------------------------------------------------------
53
  *        AHB Prescaler                          | 1
54
  *-----------------------------------------------------------------------------
55
  *        APB1 Prescaler                         | 4
56
  *-----------------------------------------------------------------------------
57
  *        APB2 Prescaler                         | 2
58
  *-----------------------------------------------------------------------------
59
  *        HSE Frequency(Hz)                      | 8000000
60
  *-----------------------------------------------------------------------------
61
  *        PLL_M                                  | 8
62
  *-----------------------------------------------------------------------------
63
  *        PLL_N                                  | 336
64
  *-----------------------------------------------------------------------------
65
  *        PLL_P                                  | 2
66
  *-----------------------------------------------------------------------------
67
  *        PLL_Q                                  | 7
68
  *-----------------------------------------------------------------------------
69
  *        PLLI2S_N                               | NA
70
  *-----------------------------------------------------------------------------
71
  *        PLLI2S_R                               | NA
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  *-----------------------------------------------------------------------------
73
  *        I2S input clock                        | NA
74
  *-----------------------------------------------------------------------------
75
  *        VDD(V)                                 | 3,3
76
  *-----------------------------------------------------------------------------
77
  *        Main regulator output voltage          | Scale1 mode
78
  *-----------------------------------------------------------------------------
79
  *        Flash Latency(WS)                      | 5
80
  *-----------------------------------------------------------------------------
81
  *        Prefetch Buffer                        | OFF
82
  *-----------------------------------------------------------------------------
83
  *        Instruction cache                      | ON
84
  *-----------------------------------------------------------------------------
85
  *        Data cache                             | ON
86
  *-----------------------------------------------------------------------------
87
  *        Require 48MHz for USB OTG FS,          | Enabled
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  *        SDIO and RNG clock                     |
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  *-----------------------------------------------------------------------------
90
  *=============================================================================
91
  ****************************************************************************** 
92
  * @attention
93
  *
94
  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
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  *
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  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
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  * You may not use this file except in compliance with the License.
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  * You may obtain a copy of the License at:
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  *
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  *        http://www.st.com/software_license_agreement_liberty_v2
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  *
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  * Unless required by applicable law or agreed to in writing, software 
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  * distributed under the License is distributed on an "AS IS" BASIS, 
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  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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  * See the License for the specific language governing permissions and
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  * limitations under the License.
107
  *
108
  ******************************************************************************
109
  */
110

    
111
/** @addtogroup CMSIS
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  * @{
113
  */
114

    
115
/** @addtogroup stm32f4xx_system
116
  * @{
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  */  
118
  
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/** @addtogroup STM32F4xx_System_Private_Includes
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  * @{
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  */
122

    
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#include "stm32f4xx.h"
124

    
125
/**
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  * @}
127
  */
128

    
129
/** @addtogroup STM32F4xx_System_Private_TypesDefinitions
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  * @{
131
  */
132

    
133
/**
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  * @}
135
  */
136

    
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/** @addtogroup STM32F4xx_System_Private_Defines
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  * @{
139
  */
140

    
141
/************************* Miscellaneous Configuration ************************/
142
/*!< Uncomment the following line if you need to use external SRAM mounted
143
     on STM324xG_EVAL/STM324x7I_EVAL board as data memory  */
144
/* #define DATA_IN_ExtSRAM */
145

    
146
/*!< Uncomment the following line if you need to relocate your vector Table in
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     Internal SRAM. */
148
/* #define VECT_TAB_SRAM */
149
#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field. 
150
                                   This value must be a multiple of 0x200. */
151
/******************************************************************************/
152

    
153
/************************* PLL Parameters *************************************/
154
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
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#define PLL_M      (HSE_VALUE/1000000)
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#define PLL_N      336
157

    
158
/* SYSCLK = PLL_VCO / PLL_P */
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#define PLL_P      2
160

    
161
/* USB OTG FS, SDIO and RNG Clock =  PLL_VCO / PLLQ */
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#define PLL_Q      7
163

    
164
/******************************************************************************/
165

    
166
/**
167
  * @}
168
  */
169

    
170
/** @addtogroup STM32F4xx_System_Private_Macros
171
  * @{
172
  */
173

    
174
/**
175
  * @}
176
  */
177

    
178
/** @addtogroup STM32F4xx_System_Private_Variables
179
  * @{
180
  */
181

    
182
  uint32_t SystemCoreClock = 168000000;
183

    
184
  __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
185

    
186
/**
187
  * @}
188
  */
189

    
190
/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
191
  * @{
192
  */
193

    
194
static void SetSysClock(void);
195
#ifdef DATA_IN_ExtSRAM
196
  static void SystemInit_ExtMemCtl(void); 
197
#endif /* DATA_IN_ExtSRAM */
198

    
199
/**
200
  * @}
201
  */
202

    
203
/** @addtogroup STM32F4xx_System_Private_Functions
204
  * @{
205
  */
206

    
207
/**
208
  * @brief  Setup the microcontroller system
209
  *         Initialize the Embedded Flash Interface, the PLL and update the 
210
  *         SystemFrequency variable.
211
  * @param  None
212
  * @retval None
213
  */
214
void SystemInit(void)
215
{
216
  /* FPU settings ------------------------------------------------------------*/
217
  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
218
    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
219
  #endif
220
  /* Reset the RCC clock configuration to the default reset state ------------*/
221
  /* Set HSION bit */
222
  RCC->CR |= (uint32_t)0x00000001;
223

    
224
  /* Reset CFGR register */
225
  RCC->CFGR = 0x00000000;
226

    
227
  /* Reset HSEON, CSSON and PLLON bits */
228
  RCC->CR &= (uint32_t)0xFEF6FFFF;
229

    
230
  /* Reset PLLCFGR register */
231
  RCC->PLLCFGR = 0x24003010;
232

    
233
  /* Reset HSEBYP bit */
234
  RCC->CR &= (uint32_t)0xFFFBFFFF;
235

    
236
  /* Disable all interrupts */
237
  RCC->CIR = 0x00000000;
238

    
239
#ifdef DATA_IN_ExtSRAM
240
  SystemInit_ExtMemCtl(); 
241
#endif /* DATA_IN_ExtSRAM */
242
         
243
  /* Configure the System clock source, PLL Multiplier and Divider factors, 
244
     AHB/APBx prescalers and Flash settings ----------------------------------*/
245
  SetSysClock();
246

    
247
  /* Configure the Vector Table location add offset address ------------------*/
248
#ifdef VECT_TAB_SRAM
249
  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
250
#else
251
  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
252
#endif
253
}
254

    
255
/**
256
   * @brief  Update SystemCoreClock variable according to Clock Register Values.
257
  *         The SystemCoreClock variable contains the core clock (HCLK), it can
258
  *         be used by the user application to setup the SysTick timer or configure
259
  *         other parameters.
260
  *           
261
  * @note   Each time the core clock (HCLK) changes, this function must be called
262
  *         to update SystemCoreClock variable value. Otherwise, any configuration
263
  *         based on this variable will be incorrect.         
264
  *     
265
  * @note   - The system frequency computed by this function is not the real 
266
  *           frequency in the chip. It is calculated based on the predefined 
267
  *           constant and the selected clock source:
268
  *             
269
  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
270
  *                                              
271
  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
272
  *                          
273
  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
274
  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
275
  *         
276
  *         (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value
277
  *             16 MHz) but the real value may vary depending on the variations
278
  *             in voltage and temperature.   
279
  *    
280
  *         (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value
281
  *              25 MHz), user has to ensure that HSE_VALUE is same as the real
282
  *              frequency of the crystal used. Otherwise, this function may
283
  *              have wrong result.
284
  *                
285
  *         - The result of this function could be not correct when using fractional
286
  *           value for HSE crystal.
287
  *     
288
  * @param  None
289
  * @retval None
290
  */
291
void SystemCoreClockUpdate(void)
292
{
293
  uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
294
  
295
  /* Get SYSCLK source -------------------------------------------------------*/
296
  tmp = RCC->CFGR & RCC_CFGR_SWS;
297

    
298
  switch (tmp)
299
  {
300
    case 0x00:  /* HSI used as system clock source */
301
      SystemCoreClock = HSI_VALUE;
302
      break;
303
    case 0x04:  /* HSE used as system clock source */
304
      SystemCoreClock = HSE_VALUE;
305
      break;
306
    case 0x08:  /* PLL used as system clock source */
307

    
308
      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
309
         SYSCLK = PLL_VCO / PLL_P
310
         */    
311
      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
312
      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
313
      
314
      if (pllsource != 0)
315
      {
316
        /* HSE used as PLL clock source */
317
        pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
318
      }
319
      else
320
      {
321
        /* HSI used as PLL clock source */
322
        pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);      
323
      }
324

    
325
      pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
326
      SystemCoreClock = pllvco/pllp;
327
      break;
328
    default:
329
      SystemCoreClock = HSI_VALUE;
330
      break;
331
  }
332
  /* Compute HCLK frequency --------------------------------------------------*/
333
  /* Get HCLK prescaler */
334
  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
335
  /* HCLK frequency */
336
  SystemCoreClock >>= tmp;
337
}
338

    
339
/**
340
  * @brief  Configures the System clock source, PLL Multiplier and Divider factors, 
341
  *         AHB/APBx prescalers and Flash settings
342
  * @Note   This function should be called only once the RCC clock configuration  
343
  *         is reset to the default reset state (done in SystemInit() function).   
344
  * @param  None
345
  * @retval None
346
  */
347
static void SetSysClock(void)
348
{
349
/******************************************************************************/
350
/*            PLL (clocked by HSE) used as System clock source                */
351
/******************************************************************************/
352
  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
353
  
354
  /* Enable HSE */
355
  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
356
 
357
  /* Wait till HSE is ready and if Time out is reached exit */
358
  do
359
  {
360
    HSEStatus = RCC->CR & RCC_CR_HSERDY;
361
    StartUpCounter++;
362
  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
363

    
364
  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
365
  {
366
    HSEStatus = (uint32_t)0x01;
367
  }
368
  else
369
  {
370
    HSEStatus = (uint32_t)0x00;
371
  }
372

    
373
  if (HSEStatus == (uint32_t)0x01)
374
  {
375
    /* Select regulator voltage output Scale 1 mode, System frequency up to 168 MHz */
376
    RCC->APB1ENR |= RCC_APB1ENR_PWREN;
377
    PWR->CR |= PWR_CR_VOS;
378

    
379
    /* HCLK = SYSCLK / 1*/
380
    RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
381
      
382
    /* PCLK2 = HCLK / 2*/
383
    RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
384
    
385
    /* PCLK1 = HCLK / 4*/
386
    RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
387

    
388
    /* Configure the main PLL */
389
    RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
390
                   (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
391

    
392
    /* Enable the main PLL */
393
    RCC->CR |= RCC_CR_PLLON;
394

    
395
    /* Wait till the main PLL is ready */
396
    while((RCC->CR & RCC_CR_PLLRDY) == 0)
397
    {
398
    }
399
   
400
    /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
401
    FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
402

    
403
    /* Select the main PLL as system clock source */
404
    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
405
    RCC->CFGR |= RCC_CFGR_SW_PLL;
406

    
407
    /* Wait till the main PLL is used as system clock source */
408
    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
409
    {
410
    }
411
  }
412
  else
413
  { /* If HSE fails to start-up, the application will have wrong clock
414
         configuration. User can add here some code to deal with this error */
415
  }
416

    
417
}
418

    
419
/**
420
  * @brief  Setup the external memory controller. Called in startup_stm32f4xx.s 
421
  *          before jump to __main
422
  * @param  None
423
  * @retval None
424
  */ 
425
#ifdef DATA_IN_ExtSRAM
426
/**
427
  * @brief  Setup the external memory controller.
428
  *         Called in startup_stm32f4xx.s before jump to main.
429
  *         This function configures the external SRAM mounted on STM324xG_EVAL/STM324x7I_EVAL board
430
  *         This SRAM will be used as program data memory (including heap and stack).
431
  * @param  None
432
  * @retval None
433
  */
434
void SystemInit_ExtMemCtl(void)
435
{
436
/*-- GPIOs Configuration -----------------------------------------------------*/
437
/*
438
 +-------------------+--------------------+------------------+------------------+
439
 +                       SRAM pins assignment                                   +
440
 +-------------------+--------------------+------------------+------------------+
441
 | PD0  <-> FSMC_D2  | PE0  <-> FSMC_NBL0 | PF0 <-> FSMC_A0  | PG0 <-> FSMC_A10 |
442
 | PD1  <-> FSMC_D3  | PE1  <-> FSMC_NBL1 | PF1 <-> FSMC_A1  | PG1 <-> FSMC_A11 |
443
 | PD4  <-> FSMC_NOE | PE2  <-> FSMC_A23  | PF2 <-> FSMC_A2  | PG2 <-> FSMC_A12 |
444
 | PD5  <-> FSMC_NWE | PE3  <-> FSMC_A19  | PF3 <-> FSMC_A3  | PG3 <-> FSMC_A13 |
445
 | PD8  <-> FSMC_D13 | PE4  <-> FSMC_A20  | PF4 <-> FSMC_A4  | PG4 <-> FSMC_A14 |
446
 | PD9  <-> FSMC_D14 | PE5  <-> FSMC_A21  | PF5 <-> FSMC_A5  | PG5 <-> FSMC_A15 |
447
 | PD10 <-> FSMC_D15 | PE6  <-> FSMC_A22  | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 |
448
 | PD11 <-> FSMC_A16 | PE7  <-> FSMC_D4   | PF13 <-> FSMC_A7 |------------------+
449
 | PD12 <-> FSMC_A17 | PE8  <-> FSMC_D5   | PF14 <-> FSMC_A8 |
450
 | PD13 <-> FSMC_A18 | PE9  <-> FSMC_D6   | PF15 <-> FSMC_A9 |
451
 | PD14 <-> FSMC_D0  | PE10 <-> FSMC_D7   |------------------+
452
 | PD15 <-> FSMC_D1  | PE11 <-> FSMC_D8   |
453
 +-------------------| PE12 <-> FSMC_D9   |
454
                     | PE13 <-> FSMC_D10  |
455
                     | PE14 <-> FSMC_D11  |
456
                     | PE15 <-> FSMC_D12  |
457
                     +--------------------+
458
*/
459
   /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
460
  RCC->AHB1ENR   |= 0x00000078;
461
  
462
  /* Connect PDx pins to FSMC Alternate function */
463
  GPIOD->AFR[0]  = 0x00cc00cc;
464
  GPIOD->AFR[1]  = 0xcccccccc;
465
  /* Configure PDx pins in Alternate function mode */  
466
  GPIOD->MODER   = 0xaaaa0a0a;
467
  /* Configure PDx pins speed to 100 MHz */  
468
  GPIOD->OSPEEDR = 0xffff0f0f;
469
  /* Configure PDx pins Output type to push-pull */  
470
  GPIOD->OTYPER  = 0x00000000;
471
  /* No pull-up, pull-down for PDx pins */ 
472
  GPIOD->PUPDR   = 0x00000000;
473

    
474
  /* Connect PEx pins to FSMC Alternate function */
475
  GPIOE->AFR[0]  = 0xcccccccc;
476
  GPIOE->AFR[1]  = 0xcccccccc;
477
  /* Configure PEx pins in Alternate function mode */ 
478
  GPIOE->MODER   = 0xaaaaaaaa;
479
  /* Configure PEx pins speed to 100 MHz */ 
480
  GPIOE->OSPEEDR = 0xffffffff;
481
  /* Configure PEx pins Output type to push-pull */  
482
  GPIOE->OTYPER  = 0x00000000;
483
  /* No pull-up, pull-down for PEx pins */ 
484
  GPIOE->PUPDR   = 0x00000000;
485

    
486
  /* Connect PFx pins to FSMC Alternate function */
487
  GPIOF->AFR[0]  = 0x00cccccc;
488
  GPIOF->AFR[1]  = 0xcccc0000;
489
  /* Configure PFx pins in Alternate function mode */   
490
  GPIOF->MODER   = 0xaa000aaa;
491
  /* Configure PFx pins speed to 100 MHz */ 
492
  GPIOF->OSPEEDR = 0xff000fff;
493
  /* Configure PFx pins Output type to push-pull */  
494
  GPIOF->OTYPER  = 0x00000000;
495
  /* No pull-up, pull-down for PFx pins */ 
496
  GPIOF->PUPDR   = 0x00000000;
497

    
498
  /* Connect PGx pins to FSMC Alternate function */
499
  GPIOG->AFR[0]  = 0x00cccccc;
500
  GPIOG->AFR[1]  = 0x000000c0;
501
  /* Configure PGx pins in Alternate function mode */ 
502
  GPIOG->MODER   = 0x00080aaa;
503
  /* Configure PGx pins speed to 100 MHz */ 
504
  GPIOG->OSPEEDR = 0x000c0fff;
505
  /* Configure PGx pins Output type to push-pull */  
506
  GPIOG->OTYPER  = 0x00000000;
507
  /* No pull-up, pull-down for PGx pins */ 
508
  GPIOG->PUPDR   = 0x00000000;
509
  
510
/*-- FSMC Configuration ------------------------------------------------------*/
511
  /* Enable the FSMC interface clock */
512
  RCC->AHB3ENR         |= 0x00000001;
513

    
514
  /* Configure and enable Bank1_SRAM2 */
515
  FSMC_Bank1->BTCR[2]  = 0x00001011;
516
  FSMC_Bank1->BTCR[3]  = 0x00000201;
517
  FSMC_Bank1E->BWTR[2] = 0x0fffffff;
518
/*
519
  Bank1_SRAM2 is configured as follow:
520

521
  p.FSMC_AddressSetupTime = 1;
522
  p.FSMC_AddressHoldTime = 0;
523
  p.FSMC_DataSetupTime = 2;
524
  p.FSMC_BusTurnAroundDuration = 0;
525
  p.FSMC_CLKDivision = 0;
526
  p.FSMC_DataLatency = 0;
527
  p.FSMC_AccessMode = FSMC_AccessMode_A;
528

529
  FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
530
  FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
531
  FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
532
  FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
533
  FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
534
  FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;  
535
  FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
536
  FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
537
  FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
538
  FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
539
  FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
540
  FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
541
  FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
542
  FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
543
  FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
544
*/
545
}
546
#endif /* DATA_IN_ExtSRAM */
547

    
548

    
549
/**
550
  * @}
551
  */
552

    
553
/**
554
  * @}
555
  */
556
  
557
/**
558
  * @}
559
  */    
560
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
561