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amiro-blt / Target / Modules / PowerManagement_1-1 / Boot / lib / stdperiphlib / STM32F4xx_StdPeriph_Driver / inc / stm32f4xx_rcc.h @ 367c0652

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/**
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  ******************************************************************************
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  * @file    stm32f4xx_rcc.h
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  * @author  MCD Application Team
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  * @version V1.1.0
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  * @date    11-January-2013
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  * @brief   This file contains all the functions prototypes for the RCC firmware library.  
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  ******************************************************************************
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  * @attention
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  *
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  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
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  *
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  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
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  * You may not use this file except in compliance with the License.
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  * You may obtain a copy of the License at:
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  *
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  *        http://www.st.com/software_license_agreement_liberty_v2
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  *
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  * Unless required by applicable law or agreed to in writing, software 
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  * distributed under the License is distributed on an "AS IS" BASIS, 
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  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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  * See the License for the specific language governing permissions and
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  * limitations under the License.
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  *
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  ******************************************************************************
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  */
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32F4xx_RCC_H
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#define __STM32F4xx_RCC_H
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#ifdef __cplusplus
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 extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f4xx.h"
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/** @addtogroup STM32F4xx_StdPeriph_Driver
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  * @{
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  */
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/** @addtogroup RCC
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  * @{
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  */ 
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/* Exported types ------------------------------------------------------------*/
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typedef struct
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{
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  uint32_t SYSCLK_Frequency; /*!<  SYSCLK clock frequency expressed in Hz */
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  uint32_t HCLK_Frequency;   /*!<  HCLK clock frequency expressed in Hz   */
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  uint32_t PCLK1_Frequency;  /*!<  PCLK1 clock frequency expressed in Hz  */
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  uint32_t PCLK2_Frequency;  /*!<  PCLK2 clock frequency expressed in Hz  */
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}RCC_ClocksTypeDef;
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup RCC_Exported_Constants
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  * @{
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  */
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/** @defgroup RCC_HSE_configuration 
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  * @{
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  */
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#define RCC_HSE_OFF                      ((uint8_t)0x00)
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#define RCC_HSE_ON                       ((uint8_t)0x01)
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#define RCC_HSE_Bypass                   ((uint8_t)0x05)
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#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
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                         ((HSE) == RCC_HSE_Bypass))
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/**
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  * @}
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  */ 
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/** @defgroup RCC_PLL_Clock_Source 
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  * @{
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  */
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#define RCC_PLLSource_HSI                ((uint32_t)0x00000000)
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#define RCC_PLLSource_HSE                ((uint32_t)0x00400000)
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#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \
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                                   ((SOURCE) == RCC_PLLSource_HSE))
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#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63)
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#define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
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#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
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#define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
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#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
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#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))  
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/**                                                                     
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  * @}
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  */ 
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/** @defgroup RCC_System_Clock_Source 
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  * @{
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  */
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#define RCC_SYSCLKSource_HSI             ((uint32_t)0x00000000)
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#define RCC_SYSCLKSource_HSE             ((uint32_t)0x00000001)
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#define RCC_SYSCLKSource_PLLCLK          ((uint32_t)0x00000002)
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#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
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                                      ((SOURCE) == RCC_SYSCLKSource_HSE) || \
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                                      ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
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/**
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  * @}
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  */ 
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/** @defgroup RCC_AHB_Clock_Source
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  * @{
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  */
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#define RCC_SYSCLK_Div1                  ((uint32_t)0x00000000)
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#define RCC_SYSCLK_Div2                  ((uint32_t)0x00000080)
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#define RCC_SYSCLK_Div4                  ((uint32_t)0x00000090)
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#define RCC_SYSCLK_Div8                  ((uint32_t)0x000000A0)
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#define RCC_SYSCLK_Div16                 ((uint32_t)0x000000B0)
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#define RCC_SYSCLK_Div64                 ((uint32_t)0x000000C0)
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#define RCC_SYSCLK_Div128                ((uint32_t)0x000000D0)
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#define RCC_SYSCLK_Div256                ((uint32_t)0x000000E0)
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#define RCC_SYSCLK_Div512                ((uint32_t)0x000000F0)
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#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
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                           ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
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                           ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
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                           ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
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                           ((HCLK) == RCC_SYSCLK_Div512))
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/**
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  * @}
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  */ 
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/** @defgroup RCC_APB1_APB2_Clock_Source
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  * @{
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  */
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#define RCC_HCLK_Div1                    ((uint32_t)0x00000000)
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#define RCC_HCLK_Div2                    ((uint32_t)0x00001000)
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#define RCC_HCLK_Div4                    ((uint32_t)0x00001400)
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#define RCC_HCLK_Div8                    ((uint32_t)0x00001800)
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#define RCC_HCLK_Div16                   ((uint32_t)0x00001C00)
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#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
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                           ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
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                           ((PCLK) == RCC_HCLK_Div16))
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/**
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  * @}
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  */ 
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/** @defgroup RCC_Interrupt_Source 
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  * @{
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  */
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#define RCC_IT_LSIRDY                    ((uint8_t)0x01)
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#define RCC_IT_LSERDY                    ((uint8_t)0x02)
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#define RCC_IT_HSIRDY                    ((uint8_t)0x04)
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#define RCC_IT_HSERDY                    ((uint8_t)0x08)
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#define RCC_IT_PLLRDY                    ((uint8_t)0x10)
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#define RCC_IT_PLLI2SRDY                 ((uint8_t)0x20)
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#define RCC_IT_CSS                       ((uint8_t)0x80)
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#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00))
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#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
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                           ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
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                           ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \
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                           ((IT) == RCC_IT_PLLI2SRDY))
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#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00))
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/**
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  * @}
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  */ 
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/** @defgroup RCC_LSE_Configuration 
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  * @{
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  */
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#define RCC_LSE_OFF                      ((uint8_t)0x00)
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#define RCC_LSE_ON                       ((uint8_t)0x01)
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#define RCC_LSE_Bypass                   ((uint8_t)0x04)
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#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
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                         ((LSE) == RCC_LSE_Bypass))
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/**
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  * @}
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  */ 
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/** @defgroup RCC_RTC_Clock_Source
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  * @{
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  */
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#define RCC_RTCCLKSource_LSE             ((uint32_t)0x00000100)
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#define RCC_RTCCLKSource_LSI             ((uint32_t)0x00000200)
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#define RCC_RTCCLKSource_HSE_Div2        ((uint32_t)0x00020300)
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#define RCC_RTCCLKSource_HSE_Div3        ((uint32_t)0x00030300)
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#define RCC_RTCCLKSource_HSE_Div4        ((uint32_t)0x00040300)
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#define RCC_RTCCLKSource_HSE_Div5        ((uint32_t)0x00050300)
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#define RCC_RTCCLKSource_HSE_Div6        ((uint32_t)0x00060300)
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#define RCC_RTCCLKSource_HSE_Div7        ((uint32_t)0x00070300)
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#define RCC_RTCCLKSource_HSE_Div8        ((uint32_t)0x00080300)
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#define RCC_RTCCLKSource_HSE_Div9        ((uint32_t)0x00090300)
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#define RCC_RTCCLKSource_HSE_Div10       ((uint32_t)0x000A0300)
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#define RCC_RTCCLKSource_HSE_Div11       ((uint32_t)0x000B0300)
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#define RCC_RTCCLKSource_HSE_Div12       ((uint32_t)0x000C0300)
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#define RCC_RTCCLKSource_HSE_Div13       ((uint32_t)0x000D0300)
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#define RCC_RTCCLKSource_HSE_Div14       ((uint32_t)0x000E0300)
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#define RCC_RTCCLKSource_HSE_Div15       ((uint32_t)0x000F0300)
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#define RCC_RTCCLKSource_HSE_Div16       ((uint32_t)0x00100300)
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#define RCC_RTCCLKSource_HSE_Div17       ((uint32_t)0x00110300)
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#define RCC_RTCCLKSource_HSE_Div18       ((uint32_t)0x00120300)
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#define RCC_RTCCLKSource_HSE_Div19       ((uint32_t)0x00130300)
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#define RCC_RTCCLKSource_HSE_Div20       ((uint32_t)0x00140300)
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#define RCC_RTCCLKSource_HSE_Div21       ((uint32_t)0x00150300)
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#define RCC_RTCCLKSource_HSE_Div22       ((uint32_t)0x00160300)
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#define RCC_RTCCLKSource_HSE_Div23       ((uint32_t)0x00170300)
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#define RCC_RTCCLKSource_HSE_Div24       ((uint32_t)0x00180300)
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#define RCC_RTCCLKSource_HSE_Div25       ((uint32_t)0x00190300)
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#define RCC_RTCCLKSource_HSE_Div26       ((uint32_t)0x001A0300)
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#define RCC_RTCCLKSource_HSE_Div27       ((uint32_t)0x001B0300)
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#define RCC_RTCCLKSource_HSE_Div28       ((uint32_t)0x001C0300)
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#define RCC_RTCCLKSource_HSE_Div29       ((uint32_t)0x001D0300)
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#define RCC_RTCCLKSource_HSE_Div30       ((uint32_t)0x001E0300)
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#define RCC_RTCCLKSource_HSE_Div31       ((uint32_t)0x001F0300)
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#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
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                                      ((SOURCE) == RCC_RTCCLKSource_LSI) || \
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                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \
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                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div3) || \
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                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \
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                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div5) || \
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                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div6) || \
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                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div7) || \
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                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \
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                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div9) || \
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                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div10) || \
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                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div11) || \
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                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div12) || \
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                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div13) || \
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                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div14) || \
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                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div15) || \
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                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div16) || \
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                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div17) || \
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                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div18) || \
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                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div19) || \
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                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div20) || \
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                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div21) || \
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                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div22) || \
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                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div23) || \
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                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div24) || \
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                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div25) || \
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                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div26) || \
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                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div27) || \
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                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div28) || \
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                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div29) || \
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                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div30) || \
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                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div31))
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/**
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  * @}
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  */ 
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/** @defgroup RCC_I2S_Clock_Source
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  * @{
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  */
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#define RCC_I2S2CLKSource_PLLI2S             ((uint8_t)0x00)
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#define RCC_I2S2CLKSource_Ext                ((uint8_t)0x01)
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#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_PLLI2S) || ((SOURCE) == RCC_I2S2CLKSource_Ext))                                
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/**
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  * @}
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  */ 
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/** @defgroup RCC_TIM_PRescaler_Selection
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  * @{
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  */
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#define RCC_TIMPrescDesactivated             ((uint8_t)0x00)
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#define RCC_TIMPrescActivated                ((uint8_t)0x01)
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#define IS_RCC_TIMCLK_PRESCALER(VALUE) (((VALUE) == RCC_TIMPrescDesactivated) || ((VALUE) == RCC_TIMPrescActivated))
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/**
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  * @}
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  */
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/** @defgroup RCC_AHB1_Peripherals 
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  * @{
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  */ 
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#define RCC_AHB1Periph_GPIOA             ((uint32_t)0x00000001)
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#define RCC_AHB1Periph_GPIOB             ((uint32_t)0x00000002)
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#define RCC_AHB1Periph_GPIOC             ((uint32_t)0x00000004)
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#define RCC_AHB1Periph_GPIOD             ((uint32_t)0x00000008)
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#define RCC_AHB1Periph_GPIOE             ((uint32_t)0x00000010)
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#define RCC_AHB1Periph_GPIOF             ((uint32_t)0x00000020)
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#define RCC_AHB1Periph_GPIOG             ((uint32_t)0x00000040)
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#define RCC_AHB1Periph_GPIOH             ((uint32_t)0x00000080)
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#define RCC_AHB1Periph_GPIOI             ((uint32_t)0x00000100)
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#define RCC_AHB1Periph_CRC               ((uint32_t)0x00001000)
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#define RCC_AHB1Periph_FLITF             ((uint32_t)0x00008000)
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#define RCC_AHB1Periph_SRAM1             ((uint32_t)0x00010000)
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#define RCC_AHB1Periph_SRAM2             ((uint32_t)0x00020000)
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#define RCC_AHB1Periph_BKPSRAM           ((uint32_t)0x00040000)
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#define RCC_AHB1Periph_SRAM3             ((uint32_t)0x00080000)
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#define RCC_AHB1Periph_CCMDATARAMEN      ((uint32_t)0x00100000)
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#define RCC_AHB1Periph_DMA1              ((uint32_t)0x00200000)
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#define RCC_AHB1Periph_DMA2              ((uint32_t)0x00400000)
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#define RCC_AHB1Periph_ETH_MAC           ((uint32_t)0x02000000)
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#define RCC_AHB1Periph_ETH_MAC_Tx        ((uint32_t)0x04000000)
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#define RCC_AHB1Periph_ETH_MAC_Rx        ((uint32_t)0x08000000)
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#define RCC_AHB1Periph_ETH_MAC_PTP       ((uint32_t)0x10000000)
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#define RCC_AHB1Periph_OTG_HS            ((uint32_t)0x20000000)
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#define RCC_AHB1Periph_OTG_HS_ULPI       ((uint32_t)0x40000000)
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#define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x818BEE00) == 0x00) && ((PERIPH) != 0x00))
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#define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xDD9FEE00) == 0x00) && ((PERIPH) != 0x00))
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#define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x81906E00) == 0x00) && ((PERIPH) != 0x00))
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/**
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  * @}
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  */ 
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/** @defgroup RCC_AHB2_Peripherals 
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  * @{
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  */  
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#define RCC_AHB2Periph_DCMI              ((uint32_t)0x00000001)
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#define RCC_AHB2Periph_CRYP              ((uint32_t)0x00000010)
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#define RCC_AHB2Periph_HASH              ((uint32_t)0x00000020)
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#define RCC_AHB2Periph_RNG               ((uint32_t)0x00000040)
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#define RCC_AHB2Periph_OTG_FS            ((uint32_t)0x00000080)
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#define IS_RCC_AHB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFF0E) == 0x00) && ((PERIPH) != 0x00))
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/**
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  * @}
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  */ 
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/** @defgroup RCC_AHB3_Peripherals 
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  * @{
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  */ 
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#define RCC_AHB3Periph_FSMC                ((uint32_t)0x00000001)
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#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00))
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/**
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  * @}
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  */ 
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/** @defgroup RCC_APB1_Peripherals 
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  * @{
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  */ 
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#define RCC_APB1Periph_TIM2              ((uint32_t)0x00000001)
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#define RCC_APB1Periph_TIM3              ((uint32_t)0x00000002)
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#define RCC_APB1Periph_TIM4              ((uint32_t)0x00000004)
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#define RCC_APB1Periph_TIM5              ((uint32_t)0x00000008)
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#define RCC_APB1Periph_TIM6              ((uint32_t)0x00000010)
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#define RCC_APB1Periph_TIM7              ((uint32_t)0x00000020)
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#define RCC_APB1Periph_TIM12             ((uint32_t)0x00000040)
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#define RCC_APB1Periph_TIM13             ((uint32_t)0x00000080)
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#define RCC_APB1Periph_TIM14             ((uint32_t)0x00000100)
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#define RCC_APB1Periph_WWDG              ((uint32_t)0x00000800)
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#define RCC_APB1Periph_SPI2              ((uint32_t)0x00004000)
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#define RCC_APB1Periph_SPI3              ((uint32_t)0x00008000)
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#define RCC_APB1Periph_USART2            ((uint32_t)0x00020000)
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#define RCC_APB1Periph_USART3            ((uint32_t)0x00040000)
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#define RCC_APB1Periph_UART4             ((uint32_t)0x00080000)
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#define RCC_APB1Periph_UART5             ((uint32_t)0x00100000)
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#define RCC_APB1Periph_I2C1              ((uint32_t)0x00200000)
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#define RCC_APB1Periph_I2C2              ((uint32_t)0x00400000)
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#define RCC_APB1Periph_I2C3              ((uint32_t)0x00800000)
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#define RCC_APB1Periph_CAN1              ((uint32_t)0x02000000)
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#define RCC_APB1Periph_CAN2              ((uint32_t)0x04000000)
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#define RCC_APB1Periph_PWR               ((uint32_t)0x10000000)
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#define RCC_APB1Periph_DAC               ((uint32_t)0x20000000)
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#define RCC_APB1Periph_UART7             ((uint32_t)0x40000000)
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#define RCC_APB1Periph_UART8             ((uint32_t)0x80000000)
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#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x09013600) == 0x00) && ((PERIPH) != 0x00))
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/**
359
  * @}
360
  */ 
361
  
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/** @defgroup RCC_APB2_Peripherals 
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  * @{
364
  */ 
365
#define RCC_APB2Periph_TIM1              ((uint32_t)0x00000001)
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#define RCC_APB2Periph_TIM8              ((uint32_t)0x00000002)
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#define RCC_APB2Periph_USART1            ((uint32_t)0x00000010)
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#define RCC_APB2Periph_USART6            ((uint32_t)0x00000020)
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#define RCC_APB2Periph_ADC               ((uint32_t)0x00000100)
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#define RCC_APB2Periph_ADC1              ((uint32_t)0x00000100)
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#define RCC_APB2Periph_ADC2              ((uint32_t)0x00000200)
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#define RCC_APB2Periph_ADC3              ((uint32_t)0x00000400)
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#define RCC_APB2Periph_SDIO              ((uint32_t)0x00000800)
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#define RCC_APB2Periph_SPI1              ((uint32_t)0x00001000)
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#define RCC_APB2Periph_SPI4              ((uint32_t)0x00002000)
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#define RCC_APB2Periph_SYSCFG            ((uint32_t)0x00004000)
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#define RCC_APB2Periph_TIM9              ((uint32_t)0x00010000)
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#define RCC_APB2Periph_TIM10             ((uint32_t)0x00020000)
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#define RCC_APB2Periph_TIM11             ((uint32_t)0x00040000)
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#define RCC_APB2Periph_SPI5              ((uint32_t)0x00100000)
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#define RCC_APB2Periph_SPI6              ((uint32_t)0x00200000)
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#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFC880CC) == 0x00) && ((PERIPH) != 0x00))
384
#define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xFFC886CC) == 0x00) && ((PERIPH) != 0x00))
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386

    
387
/**
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  * @}
389
  */ 
390
  
391
/** @defgroup RCC_MCO1_Clock_Source_Prescaler
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  * @{
393
  */
394
#define RCC_MCO1Source_HSI               ((uint32_t)0x00000000)
395
#define RCC_MCO1Source_LSE               ((uint32_t)0x00200000)
396
#define RCC_MCO1Source_HSE               ((uint32_t)0x00400000)
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#define RCC_MCO1Source_PLLCLK            ((uint32_t)0x00600000)
398
#define RCC_MCO1Div_1                    ((uint32_t)0x00000000)
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#define RCC_MCO1Div_2                    ((uint32_t)0x04000000)
400
#define RCC_MCO1Div_3                    ((uint32_t)0x05000000)
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#define RCC_MCO1Div_4                    ((uint32_t)0x06000000)
402
#define RCC_MCO1Div_5                    ((uint32_t)0x07000000)
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#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1Source_HSI) || ((SOURCE) == RCC_MCO1Source_LSE) || \
404
                                   ((SOURCE) == RCC_MCO1Source_HSE) || ((SOURCE) == RCC_MCO1Source_PLLCLK))
405
                                   
406
#define IS_RCC_MCO1DIV(DIV) (((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) || \
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                             ((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) || \
408
                             ((DIV) == RCC_MCO1Div_5)) 
409
/**
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  * @}
411
  */ 
412
  
413
/** @defgroup RCC_MCO2_Clock_Source_Prescaler
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  * @{
415
  */
416
#define RCC_MCO2Source_SYSCLK            ((uint32_t)0x00000000)
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#define RCC_MCO2Source_PLLI2SCLK         ((uint32_t)0x40000000)
418
#define RCC_MCO2Source_HSE               ((uint32_t)0x80000000)
419
#define RCC_MCO2Source_PLLCLK            ((uint32_t)0xC0000000)
420
#define RCC_MCO2Div_1                    ((uint32_t)0x00000000)
421
#define RCC_MCO2Div_2                    ((uint32_t)0x20000000)
422
#define RCC_MCO2Div_3                    ((uint32_t)0x28000000)
423
#define RCC_MCO2Div_4                    ((uint32_t)0x30000000)
424
#define RCC_MCO2Div_5                    ((uint32_t)0x38000000)
425
#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2Source_SYSCLK) || ((SOURCE) == RCC_MCO2Source_PLLI2SCLK)|| \
426
                                   ((SOURCE) == RCC_MCO2Source_HSE) || ((SOURCE) == RCC_MCO2Source_PLLCLK))
427
                                   
428
#define IS_RCC_MCO2DIV(DIV) (((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) || \
429
                             ((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) || \
430
                             ((DIV) == RCC_MCO2Div_5))                             
431
/**
432
  * @}
433
  */ 
434
  
435
/** @defgroup RCC_Flag 
436
  * @{
437
  */
438
#define RCC_FLAG_HSIRDY                  ((uint8_t)0x21)
439
#define RCC_FLAG_HSERDY                  ((uint8_t)0x31)
440
#define RCC_FLAG_PLLRDY                  ((uint8_t)0x39)
441
#define RCC_FLAG_PLLI2SRDY               ((uint8_t)0x3B)
442
#define RCC_FLAG_LSERDY                  ((uint8_t)0x41)
443
#define RCC_FLAG_LSIRDY                  ((uint8_t)0x61)
444
#define RCC_FLAG_BORRST                  ((uint8_t)0x79)
445
#define RCC_FLAG_PINRST                  ((uint8_t)0x7A)
446
#define RCC_FLAG_PORRST                  ((uint8_t)0x7B)
447
#define RCC_FLAG_SFTRST                  ((uint8_t)0x7C)
448
#define RCC_FLAG_IWDGRST                 ((uint8_t)0x7D)
449
#define RCC_FLAG_WWDGRST                 ((uint8_t)0x7E)
450
#define RCC_FLAG_LPWRRST                 ((uint8_t)0x7F)
451

    
452
#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
453
                           ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
454
                           ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \
455
                           ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
456
                           ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \
457
                           ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \
458
                           ((FLAG) == RCC_FLAG_PLLI2SRDY))
459

    
460
#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
461
/**
462
  * @}
463
  */ 
464

    
465
/**
466
  * @}
467
  */ 
468

    
469
/* Exported macro ------------------------------------------------------------*/
470
/* Exported functions --------------------------------------------------------*/ 
471

    
472
/* Function used to set the RCC clock configuration to the default reset state */
473
void RCC_DeInit(void);
474

    
475
/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
476
void        RCC_HSEConfig(uint8_t RCC_HSE);
477
ErrorStatus RCC_WaitForHSEStartUp(void);
478
void        RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
479
void        RCC_HSICmd(FunctionalState NewState);
480
void        RCC_LSEConfig(uint8_t RCC_LSE);
481
void        RCC_LSICmd(FunctionalState NewState);
482

    
483
void        RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ);
484
void        RCC_PLLCmd(FunctionalState NewState);
485
void        RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR);
486
void        RCC_PLLI2SCmd(FunctionalState NewState);
487
void        RCC_ClockSecuritySystemCmd(FunctionalState NewState);
488
void        RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div);
489
void        RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div);
490

    
491
/* System, AHB and APB busses clocks configuration functions ******************/
492
void    RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
493
uint8_t RCC_GetSYSCLKSource(void);
494
void    RCC_HCLKConfig(uint32_t RCC_SYSCLK);
495
void    RCC_PCLK1Config(uint32_t RCC_HCLK);
496
void    RCC_PCLK2Config(uint32_t RCC_HCLK);
497
void    RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
498

    
499
/* Peripheral clocks configuration functions **********************************/
500
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
501
void RCC_RTCCLKCmd(FunctionalState NewState);
502
void RCC_BackupResetCmd(FunctionalState NewState);
503
void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource); 
504
void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler);
505

    
506
void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
507
void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
508
void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
509
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
510
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
511

    
512
void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
513
void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
514
void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
515
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
516
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
517

    
518
void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
519
void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
520
void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
521
void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
522
void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
523

    
524
/* Interrupts and flags management functions **********************************/
525
void       RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
526
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
527
void       RCC_ClearFlag(void);
528
ITStatus   RCC_GetITStatus(uint8_t RCC_IT);
529
void       RCC_ClearITPendingBit(uint8_t RCC_IT);
530

    
531
#ifdef __cplusplus
532
}
533
#endif
534

    
535
#endif /* __STM32F4xx_RCC_H */
536

    
537
/**
538
  * @}
539
  */ 
540

    
541
/**
542
  * @}
543
  */ 
544

    
545
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/