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/**
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  ******************************************************************************
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  * @file    stm32f4xx_dac.c
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  * @author  MCD Application Team
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  * @version V1.1.0
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  * @date    11-January-2013
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   * @brief   This file provides firmware functions to manage the following 
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  *          functionalities of the Digital-to-Analog Converter (DAC) peripheral: 
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  *           + DAC channels configuration: trigger, output buffer, data format
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  *           + DMA management      
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  *           + Interrupts and flags management
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  *
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 @verbatim      
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 ===============================================================================
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                      ##### DAC Peripheral features #####
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 ===============================================================================
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    [..]        
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      *** DAC Channels ***
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      ====================  
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    [..]  
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    The device integrates two 12-bit Digital Analog Converters that can 
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    be used independently or simultaneously (dual mode):
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      (#) DAC channel1 with DAC_OUT1 (PA4) as output
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      (#) DAC channel2 with DAC_OUT2 (PA5) as output
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      *** DAC Triggers ***
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      ====================
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    [..]
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    Digital to Analog conversion can be non-triggered using DAC_Trigger_None
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    and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register 
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    using DAC_SetChannel1Data() / DAC_SetChannel2Data() functions.
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    [..] 
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    Digital to Analog conversion can be triggered by:
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      (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9.
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          The used pin (GPIOx_Pin9) must be configured in input mode.
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      (#) Timers TRGO: TIM2, TIM4, TIM5, TIM6, TIM7 and TIM8 
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          (DAC_Trigger_T2_TRGO, DAC_Trigger_T4_TRGO...)
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          The timer TRGO event should be selected using TIM_SelectOutputTrigger()
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      (#) Software using DAC_Trigger_Software
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      *** DAC Buffer mode feature ***
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      =============================== 
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      [..] 
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      Each DAC channel integrates an output buffer that can be used to 
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      reduce the output impedance, and to drive external loads directly
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      without having to add an external operational amplifier.
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      To enable, the output buffer use  
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      DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable;
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      [..]           
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      (@) Refer to the device datasheet for more details about output 
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          impedance value with and without output buffer.
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       *** DAC wave generation feature ***
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       =================================== 
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       [..]     
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       Both DAC channels can be used to generate
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         (#) Noise wave using DAC_WaveGeneration_Noise
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         (#) Triangle wave using DAC_WaveGeneration_Triangle
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          -@-  Wave generation can be disabled using DAC_WaveGeneration_None
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       *** DAC data format ***
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       =======================
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       [..]   
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       The DAC data format can be:
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         (#) 8-bit right alignment using DAC_Align_8b_R
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         (#) 12-bit left alignment using DAC_Align_12b_L
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         (#) 12-bit right alignment using DAC_Align_12b_R
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       *** DAC data value to voltage correspondence ***  
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       ================================================ 
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       [..] 
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       The analog output voltage on each DAC channel pin is determined
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       by the following equation: 
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       DAC_OUTx = VREF+ * DOR / 4095
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       with  DOR is the Data Output Register
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          VEF+ is the input voltage reference (refer to the device datasheet)
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        e.g. To set DAC_OUT1 to 0.7V, use
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          DAC_SetChannel1Data(DAC_Align_12b_R, 868);
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          Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
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       *** DMA requests  ***
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       =====================
86
       [..]    
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       A DMA1 request can be generated when an external trigger (but not
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       a software trigger) occurs if DMA1 requests are enabled using
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       DAC_DMACmd()
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       [..]
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       DMA1 requests are mapped as following:
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         (#) DAC channel1 : mapped on DMA1 Stream5 channel7 which must be 
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             already configured
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         (#) DAC channel2 : mapped on DMA1 Stream6 channel7 which must be 
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             already configured
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                      ##### How to use this driver #####
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 ===============================================================================
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    [..]          
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      (+) DAC APB clock must be enabled to get write access to DAC
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          registers using
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          RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE)
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      (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
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      (+) Configure the DAC channel using DAC_Init() function
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      (+) Enable the DAC channel using DAC_Cmd() function
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108
 @endverbatim    
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  ******************************************************************************
110
  * @attention
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  *
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  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
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  *
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  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
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  * You may not use this file except in compliance with the License.
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  * You may obtain a copy of the License at:
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  *
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  *        http://www.st.com/software_license_agreement_liberty_v2
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  *
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  * Unless required by applicable law or agreed to in writing, software 
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  * distributed under the License is distributed on an "AS IS" BASIS, 
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  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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  * See the License for the specific language governing permissions and
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  * limitations under the License.
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  *
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  ******************************************************************************  
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  */ 
128

    
129

    
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f4xx_dac.h"
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#include "stm32f4xx_rcc.h"
133

    
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/** @addtogroup STM32F4xx_StdPeriph_Driver
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  * @{
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  */
137

    
138
/** @defgroup DAC 
139
  * @brief DAC driver modules
140
  * @{
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  */ 
142

    
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
145

    
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/* CR register Mask */
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#define CR_CLEAR_MASK              ((uint32_t)0x00000FFE)
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/* DAC Dual Channels SWTRIG masks */
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#define DUAL_SWTRIG_SET            ((uint32_t)0x00000003)
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#define DUAL_SWTRIG_RESET          ((uint32_t)0xFFFFFFFC)
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/* DHR registers offsets */
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#define DHR12R1_OFFSET             ((uint32_t)0x00000008)
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#define DHR12R2_OFFSET             ((uint32_t)0x00000014)
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#define DHR12RD_OFFSET             ((uint32_t)0x00000020)
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/* DOR register offset */
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#define DOR_OFFSET                 ((uint32_t)0x0000002C)
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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/* Private functions ---------------------------------------------------------*/
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/** @defgroup DAC_Private_Functions
167
  * @{
168
  */
169

    
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/** @defgroup DAC_Group1 DAC channels configuration
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 *  @brief   DAC channels configuration: trigger, output buffer, data format 
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 *
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@verbatim   
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 ===============================================================================
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   ##### DAC channels configuration: trigger, output buffer, data format #####
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 ===============================================================================  
177

178
@endverbatim
179
  * @{
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  */
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/**
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  * @brief  Deinitializes the DAC peripheral registers to their default reset values.
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  * @param  None
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  * @retval None
186
  */
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void DAC_DeInit(void)
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{
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  /* Enable DAC reset state */
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  RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);
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  /* Release DAC from reset state */
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  RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);
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}
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/**
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  * @brief  Initializes the DAC peripheral according to the specified parameters
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  *         in the DAC_InitStruct.
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  * @param  DAC_Channel: the selected DAC channel. 
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  *          This parameter can be one of the following values:
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  *            @arg DAC_Channel_1: DAC Channel1 selected
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  *            @arg DAC_Channel_2: DAC Channel2 selected
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  * @param  DAC_InitStruct: pointer to a DAC_InitTypeDef structure that contains
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  *         the configuration information for the  specified DAC channel.
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  * @retval None
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  */
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void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)
207
{
208
  uint32_t tmpreg1 = 0, tmpreg2 = 0;
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  /* Check the DAC parameters */
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  assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));
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  assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));
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  assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));
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  assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));
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/*---------------------------- DAC CR Configuration --------------------------*/
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  /* Get the DAC CR value */
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  tmpreg1 = DAC->CR;
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  /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
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  tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel);
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  /* Configure for the selected DAC channel: buffer output, trigger, 
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     wave generation, mask/amplitude for wave generation */
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  /* Set TSELx and TENx bits according to DAC_Trigger value */
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  /* Set WAVEx bits according to DAC_WaveGeneration value */
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  /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ 
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  /* Set BOFFx bit according to DAC_OutputBuffer value */   
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  tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
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             DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | \
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             DAC_InitStruct->DAC_OutputBuffer);
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  /* Calculate CR register value depending on DAC_Channel */
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  tmpreg1 |= tmpreg2 << DAC_Channel;
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  /* Write to DAC CR */
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  DAC->CR = tmpreg1;
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}
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/**
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  * @brief  Fills each DAC_InitStruct member with its default value.
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  * @param  DAC_InitStruct: pointer to a DAC_InitTypeDef structure which will 
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  *         be initialized.
240
  * @retval None
241
  */
242
void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)
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{
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/*--------------- Reset DAC init structure parameters values -----------------*/
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  /* Initialize the DAC_Trigger member */
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  DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
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  /* Initialize the DAC_WaveGeneration member */
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  DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
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  /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
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  DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
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  /* Initialize the DAC_OutputBuffer member */
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  DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
253
}
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255
/**
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  * @brief  Enables or disables the specified DAC channel.
257
  * @param  DAC_Channel: The selected DAC channel. 
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  *          This parameter can be one of the following values:
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  *            @arg DAC_Channel_1: DAC Channel1 selected
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  *            @arg DAC_Channel_2: DAC Channel2 selected
261
  * @param  NewState: new state of the DAC channel. 
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  *          This parameter can be: ENABLE or DISABLE.
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  * @note   When the DAC channel is enabled the trigger source can no more be modified.
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  * @retval None
265
  */
266
void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)
267
{
268
  /* Check the parameters */
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  assert_param(IS_DAC_CHANNEL(DAC_Channel));
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  assert_param(IS_FUNCTIONAL_STATE(NewState));
271

    
272
  if (NewState != DISABLE)
273
  {
274
    /* Enable the selected DAC channel */
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    DAC->CR |= (DAC_CR_EN1 << DAC_Channel);
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  }
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  else
278
  {
279
    /* Disable the selected DAC channel */
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    DAC->CR &= (~(DAC_CR_EN1 << DAC_Channel));
281
  }
282
}
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284
/**
285
  * @brief  Enables or disables the selected DAC channel software trigger.
286
  * @param  DAC_Channel: The selected DAC channel. 
287
  *          This parameter can be one of the following values:
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  *            @arg DAC_Channel_1: DAC Channel1 selected
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  *            @arg DAC_Channel_2: DAC Channel2 selected
290
  * @param  NewState: new state of the selected DAC channel software trigger.
291
  *          This parameter can be: ENABLE or DISABLE.
292
  * @retval None
293
  */
294
void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)
295
{
296
  /* Check the parameters */
297
  assert_param(IS_DAC_CHANNEL(DAC_Channel));
298
  assert_param(IS_FUNCTIONAL_STATE(NewState));
299

    
300
  if (NewState != DISABLE)
301
  {
302
    /* Enable software trigger for the selected DAC channel */
303
    DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4);
304
  }
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  else
306
  {
307
    /* Disable software trigger for the selected DAC channel */
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    DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4));
309
  }
310
}
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312
/**
313
  * @brief  Enables or disables simultaneously the two DAC channels software triggers.
314
  * @param  NewState: new state of the DAC channels software triggers.
315
  *          This parameter can be: ENABLE or DISABLE.
316
  * @retval None
317
  */
318
void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)
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{
320
  /* Check the parameters */
321
  assert_param(IS_FUNCTIONAL_STATE(NewState));
322

    
323
  if (NewState != DISABLE)
324
  {
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    /* Enable software trigger for both DAC channels */
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    DAC->SWTRIGR |= DUAL_SWTRIG_SET;
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  }
328
  else
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  {
330
    /* Disable software trigger for both DAC channels */
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    DAC->SWTRIGR &= DUAL_SWTRIG_RESET;
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  }
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}
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/**
336
  * @brief  Enables or disables the selected DAC channel wave generation.
337
  * @param  DAC_Channel: The selected DAC channel. 
338
  *          This parameter can be one of the following values:
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  *            @arg DAC_Channel_1: DAC Channel1 selected
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  *            @arg DAC_Channel_2: DAC Channel2 selected
341
  * @param  DAC_Wave: specifies the wave type to enable or disable.
342
  *          This parameter can be one of the following values:
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  *            @arg DAC_Wave_Noise: noise wave generation
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  *            @arg DAC_Wave_Triangle: triangle wave generation
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  * @param  NewState: new state of the selected DAC channel wave generation.
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  *          This parameter can be: ENABLE or DISABLE.  
347
  * @retval None
348
  */
349
void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
350
{
351
  /* Check the parameters */
352
  assert_param(IS_DAC_CHANNEL(DAC_Channel));
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  assert_param(IS_DAC_WAVE(DAC_Wave)); 
354
  assert_param(IS_FUNCTIONAL_STATE(NewState));
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356
  if (NewState != DISABLE)
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  {
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    /* Enable the selected wave generation for the selected DAC channel */
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    DAC->CR |= DAC_Wave << DAC_Channel;
360
  }
361
  else
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  {
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    /* Disable the selected wave generation for the selected DAC channel */
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    DAC->CR &= ~(DAC_Wave << DAC_Channel);
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  }
366
}
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368
/**
369
  * @brief  Set the specified data holding register value for DAC channel1.
370
  * @param  DAC_Align: Specifies the data alignment for DAC channel1.
371
  *          This parameter can be one of the following values:
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  *            @arg DAC_Align_8b_R: 8bit right data alignment selected
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  *            @arg DAC_Align_12b_L: 12bit left data alignment selected
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  *            @arg DAC_Align_12b_R: 12bit right data alignment selected
375
  * @param  Data: Data to be loaded in the selected data holding register.
376
  * @retval None
377
  */
378
void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
379
{  
380
  __IO uint32_t tmp = 0;
381
  
382
  /* Check the parameters */
383
  assert_param(IS_DAC_ALIGN(DAC_Align));
384
  assert_param(IS_DAC_DATA(Data));
385
  
386
  tmp = (uint32_t)DAC_BASE; 
387
  tmp += DHR12R1_OFFSET + DAC_Align;
388

    
389
  /* Set the DAC channel1 selected data holding register */
390
  *(__IO uint32_t *) tmp = Data;
391
}
392

    
393
/**
394
  * @brief  Set the specified data holding register value for DAC channel2.
395
  * @param  DAC_Align: Specifies the data alignment for DAC channel2.
396
  *          This parameter can be one of the following values:
397
  *            @arg DAC_Align_8b_R: 8bit right data alignment selected
398
  *            @arg DAC_Align_12b_L: 12bit left data alignment selected
399
  *            @arg DAC_Align_12b_R: 12bit right data alignment selected
400
  * @param  Data: Data to be loaded in the selected data holding register.
401
  * @retval None
402
  */
403
void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
404
{
405
  __IO uint32_t tmp = 0;
406

    
407
  /* Check the parameters */
408
  assert_param(IS_DAC_ALIGN(DAC_Align));
409
  assert_param(IS_DAC_DATA(Data));
410
  
411
  tmp = (uint32_t)DAC_BASE;
412
  tmp += DHR12R2_OFFSET + DAC_Align;
413

    
414
  /* Set the DAC channel2 selected data holding register */
415
  *(__IO uint32_t *)tmp = Data;
416
}
417

    
418
/**
419
  * @brief  Set the specified data holding register value for dual channel DAC.
420
  * @param  DAC_Align: Specifies the data alignment for dual channel DAC.
421
  *          This parameter can be one of the following values:
422
  *            @arg DAC_Align_8b_R: 8bit right data alignment selected
423
  *            @arg DAC_Align_12b_L: 12bit left data alignment selected
424
  *            @arg DAC_Align_12b_R: 12bit right data alignment selected
425
  * @param  Data2: Data for DAC Channel2 to be loaded in the selected data holding register.
426
  * @param  Data1: Data for DAC Channel1 to be loaded in the selected data  holding register.
427
  * @note   In dual mode, a unique register access is required to write in both
428
  *          DAC channels at the same time.
429
  * @retval None
430
  */
431
void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
432
{
433
  uint32_t data = 0, tmp = 0;
434
  
435
  /* Check the parameters */
436
  assert_param(IS_DAC_ALIGN(DAC_Align));
437
  assert_param(IS_DAC_DATA(Data1));
438
  assert_param(IS_DAC_DATA(Data2));
439
  
440
  /* Calculate and set dual DAC data holding register value */
441
  if (DAC_Align == DAC_Align_8b_R)
442
  {
443
    data = ((uint32_t)Data2 << 8) | Data1; 
444
  }
445
  else
446
  {
447
    data = ((uint32_t)Data2 << 16) | Data1;
448
  }
449
  
450
  tmp = (uint32_t)DAC_BASE;
451
  tmp += DHR12RD_OFFSET + DAC_Align;
452

    
453
  /* Set the dual DAC selected data holding register */
454
  *(__IO uint32_t *)tmp = data;
455
}
456

    
457
/**
458
  * @brief  Returns the last data output value of the selected DAC channel.
459
  * @param  DAC_Channel: The selected DAC channel. 
460
  *          This parameter can be one of the following values:
461
  *            @arg DAC_Channel_1: DAC Channel1 selected
462
  *            @arg DAC_Channel_2: DAC Channel2 selected
463
  * @retval The selected DAC channel data output value.
464
  */
465
uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
466
{
467
  __IO uint32_t tmp = 0;
468
  
469
  /* Check the parameters */
470
  assert_param(IS_DAC_CHANNEL(DAC_Channel));
471
  
472
  tmp = (uint32_t) DAC_BASE ;
473
  tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);
474
  
475
  /* Returns the DAC channel data output register value */
476
  return (uint16_t) (*(__IO uint32_t*) tmp);
477
}
478
/**
479
  * @}
480
  */
481

    
482
/** @defgroup DAC_Group2 DMA management functions
483
 *  @brief   DMA management functions
484
 *
485
@verbatim   
486
 ===============================================================================
487
                       ##### DMA management functions #####
488
 ===============================================================================  
489

490
@endverbatim
491
  * @{
492
  */
493

    
494
/**
495
  * @brief  Enables or disables the specified DAC channel DMA request.
496
  * @note   When enabled DMA1 is generated when an external trigger (EXTI Line9,
497
  *         TIM2, TIM4, TIM5, TIM6, TIM7 or TIM8  but not a software trigger) occurs.
498
  * @param  DAC_Channel: The selected DAC channel. 
499
  *          This parameter can be one of the following values:
500
  *            @arg DAC_Channel_1: DAC Channel1 selected
501
  *            @arg DAC_Channel_2: DAC Channel2 selected
502
  * @param  NewState: new state of the selected DAC channel DMA request.
503
  *          This parameter can be: ENABLE or DISABLE.
504
  * @note   The DAC channel1 is mapped on DMA1 Stream 5 channel7 which must be
505
  *          already configured.
506
  * @note   The DAC channel2 is mapped on DMA1 Stream 6 channel7 which must be
507
  *          already configured.    
508
  * @retval None
509
  */
510
void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)
511
{
512
  /* Check the parameters */
513
  assert_param(IS_DAC_CHANNEL(DAC_Channel));
514
  assert_param(IS_FUNCTIONAL_STATE(NewState));
515

    
516
  if (NewState != DISABLE)
517
  {
518
    /* Enable the selected DAC channel DMA request */
519
    DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel);
520
  }
521
  else
522
  {
523
    /* Disable the selected DAC channel DMA request */
524
    DAC->CR &= (~(DAC_CR_DMAEN1 << DAC_Channel));
525
  }
526
}
527
/**
528
  * @}
529
  */
530

    
531
/** @defgroup DAC_Group3 Interrupts and flags management functions
532
 *  @brief   Interrupts and flags management functions
533
 *
534
@verbatim   
535
 ===============================================================================
536
             ##### Interrupts and flags management functions #####
537
 ===============================================================================  
538

539
@endverbatim
540
  * @{
541
  */
542

    
543
/**
544
  * @brief  Enables or disables the specified DAC interrupts.
545
  * @param  DAC_Channel: The selected DAC channel. 
546
  *          This parameter can be one of the following values:
547
  *            @arg DAC_Channel_1: DAC Channel1 selected
548
  *            @arg DAC_Channel_2: DAC Channel2 selected
549
  * @param  DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. 
550
  *          This parameter can be the following values:
551
  *            @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
552
  * @note   The DMA underrun occurs when a second external trigger arrives before the 
553
  *         acknowledgement for the first external trigger is received (first request).
554
  * @param  NewState: new state of the specified DAC interrupts.
555
  *          This parameter can be: ENABLE or DISABLE.
556
  * @retval None
557
  */ 
558
void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState)  
559
{
560
  /* Check the parameters */
561
  assert_param(IS_DAC_CHANNEL(DAC_Channel));
562
  assert_param(IS_FUNCTIONAL_STATE(NewState));
563
  assert_param(IS_DAC_IT(DAC_IT)); 
564

    
565
  if (NewState != DISABLE)
566
  {
567
    /* Enable the selected DAC interrupts */
568
    DAC->CR |=  (DAC_IT << DAC_Channel);
569
  }
570
  else
571
  {
572
    /* Disable the selected DAC interrupts */
573
    DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel));
574
  }
575
}
576

    
577
/**
578
  * @brief  Checks whether the specified DAC flag is set or not.
579
  * @param  DAC_Channel: The selected DAC channel. 
580
  *          This parameter can be one of the following values:
581
  *            @arg DAC_Channel_1: DAC Channel1 selected
582
  *            @arg DAC_Channel_2: DAC Channel2 selected
583
  * @param  DAC_FLAG: specifies the flag to check. 
584
  *          This parameter can be only of the following value:
585
  *            @arg DAC_FLAG_DMAUDR: DMA underrun flag
586
  * @note   The DMA underrun occurs when a second external trigger arrives before the 
587
  *         acknowledgement for the first external trigger is received (first request).
588
  * @retval The new state of DAC_FLAG (SET or RESET).
589
  */
590
FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG)
591
{
592
  FlagStatus bitstatus = RESET;
593
  /* Check the parameters */
594
  assert_param(IS_DAC_CHANNEL(DAC_Channel));
595
  assert_param(IS_DAC_FLAG(DAC_FLAG));
596

    
597
  /* Check the status of the specified DAC flag */
598
  if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET)
599
  {
600
    /* DAC_FLAG is set */
601
    bitstatus = SET;
602
  }
603
  else
604
  {
605
    /* DAC_FLAG is reset */
606
    bitstatus = RESET;
607
  }
608
  /* Return the DAC_FLAG status */
609
  return  bitstatus;
610
}
611

    
612
/**
613
  * @brief  Clears the DAC channel's pending flags.
614
  * @param  DAC_Channel: The selected DAC channel. 
615
  *          This parameter can be one of the following values:
616
  *            @arg DAC_Channel_1: DAC Channel1 selected
617
  *            @arg DAC_Channel_2: DAC Channel2 selected
618
  * @param  DAC_FLAG: specifies the flag to clear. 
619
  *          This parameter can be of the following value:
620
  *            @arg DAC_FLAG_DMAUDR: DMA underrun flag 
621
  * @note   The DMA underrun occurs when a second external trigger arrives before the 
622
  *         acknowledgement for the first external trigger is received (first request).                           
623
  * @retval None
624
  */
625
void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG)
626
{
627
  /* Check the parameters */
628
  assert_param(IS_DAC_CHANNEL(DAC_Channel));
629
  assert_param(IS_DAC_FLAG(DAC_FLAG));
630

    
631
  /* Clear the selected DAC flags */
632
  DAC->SR = (DAC_FLAG << DAC_Channel);
633
}
634

    
635
/**
636
  * @brief  Checks whether the specified DAC interrupt has occurred or not.
637
  * @param  DAC_Channel: The selected DAC channel. 
638
  *          This parameter can be one of the following values:
639
  *            @arg DAC_Channel_1: DAC Channel1 selected
640
  *            @arg DAC_Channel_2: DAC Channel2 selected
641
  * @param  DAC_IT: specifies the DAC interrupt source to check. 
642
  *          This parameter can be the following values:
643
  *            @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
644
  * @note   The DMA underrun occurs when a second external trigger arrives before the 
645
  *         acknowledgement for the first external trigger is received (first request).
646
  * @retval The new state of DAC_IT (SET or RESET).
647
  */
648
ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT)
649
{
650
  ITStatus bitstatus = RESET;
651
  uint32_t enablestatus = 0;
652
  
653
  /* Check the parameters */
654
  assert_param(IS_DAC_CHANNEL(DAC_Channel));
655
  assert_param(IS_DAC_IT(DAC_IT));
656

    
657
  /* Get the DAC_IT enable bit status */
658
  enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ;
659
  
660
  /* Check the status of the specified DAC interrupt */
661
  if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus)
662
  {
663
    /* DAC_IT is set */
664
    bitstatus = SET;
665
  }
666
  else
667
  {
668
    /* DAC_IT is reset */
669
    bitstatus = RESET;
670
  }
671
  /* Return the DAC_IT status */
672
  return  bitstatus;
673
}
674

    
675
/**
676
  * @brief  Clears the DAC channel's interrupt pending bits.
677
  * @param  DAC_Channel: The selected DAC channel. 
678
  *          This parameter can be one of the following values:
679
  *            @arg DAC_Channel_1: DAC Channel1 selected
680
  *            @arg DAC_Channel_2: DAC Channel2 selected
681
  * @param  DAC_IT: specifies the DAC interrupt pending bit to clear.
682
  *          This parameter can be the following values:
683
  *            @arg DAC_IT_DMAUDR: DMA underrun interrupt mask                         
684
  * @note   The DMA underrun occurs when a second external trigger arrives before the 
685
  *         acknowledgement for the first external trigger is received (first request).                           
686
  * @retval None
687
  */
688
void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT)
689
{
690
  /* Check the parameters */
691
  assert_param(IS_DAC_CHANNEL(DAC_Channel));
692
  assert_param(IS_DAC_IT(DAC_IT)); 
693

    
694
  /* Clear the selected DAC interrupt pending bits */
695
  DAC->SR = (DAC_IT << DAC_Channel);
696
}
697

    
698
/**
699
  * @}
700
  */
701

    
702
/**
703
  * @}
704
  */
705

    
706
/**
707
  * @}
708
  */
709

    
710
/**
711
  * @}
712
  */
713

    
714
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/