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amiro-blt / Target / Modules / PowerManagement_1-1 / Boot / lib / stdperiphlib / STM32F4xx_StdPeriph_Driver / src / stm32f4xx_fsmc.c @ 367c0652

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/**
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  ******************************************************************************
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  * @file    stm32f4xx_fsmc.c
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  * @author  MCD Application Team
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  * @version V1.1.0
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  * @date    11-January-2013
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 * @brief    This file provides firmware functions to manage the following 
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  *          functionalities of the FSMC peripheral:           
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  *           + Interface with SRAM, PSRAM, NOR and OneNAND memories
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  *           + Interface with NAND memories
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  *           + Interface with 16-bit PC Card compatible memories  
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  *           + Interrupts and flags management   
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  *           
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  ******************************************************************************
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  * @attention
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  *
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  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
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  *
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  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
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  * You may not use this file except in compliance with the License.
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  * You may obtain a copy of the License at:
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  *
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  *        http://www.st.com/software_license_agreement_liberty_v2
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  *
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  * Unless required by applicable law or agreed to in writing, software 
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  * distributed under the License is distributed on an "AS IS" BASIS, 
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  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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  * See the License for the specific language governing permissions and
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  * limitations under the License.
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  *
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  ******************************************************************************
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  */
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f4xx_fsmc.h"
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#include "stm32f4xx_rcc.h"
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/** @addtogroup STM32F4xx_StdPeriph_Driver
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  * @{
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  */
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/** @defgroup FSMC 
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  * @brief FSMC driver modules
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  * @{
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  */ 
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/* --------------------- FSMC registers bit mask ---------------------------- */
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/* FSMC BCRx Mask */
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#define BCR_MBKEN_SET          ((uint32_t)0x00000001)
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#define BCR_MBKEN_RESET        ((uint32_t)0x000FFFFE)
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#define BCR_FACCEN_SET         ((uint32_t)0x00000040)
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/* FSMC PCRx Mask */
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#define PCR_PBKEN_SET          ((uint32_t)0x00000004)
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#define PCR_PBKEN_RESET        ((uint32_t)0x000FFFFB)
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#define PCR_ECCEN_SET          ((uint32_t)0x00000040)
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#define PCR_ECCEN_RESET        ((uint32_t)0x000FFFBF)
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#define PCR_MEMORYTYPE_NAND    ((uint32_t)0x00000008)
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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/* Private functions ---------------------------------------------------------*/
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/** @defgroup FSMC_Private_Functions
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  * @{
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  */
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/** @defgroup FSMC_Group1 NOR/SRAM Controller functions
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 *  @brief   NOR/SRAM Controller functions 
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 *
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@verbatim   
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 ===============================================================================
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                    ##### NOR and SRAM Controller functions #####
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 ===============================================================================  
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 [..] The following sequence should be followed to configure the FSMC to interface
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      with SRAM, PSRAM, NOR or OneNAND memory connected to the NOR/SRAM Bank:
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   (#) Enable the clock for the FSMC and associated GPIOs using the following functions:
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          RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE);
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          RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
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   (#) FSMC pins configuration 
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       (++) Connect the involved FSMC pins to AF12 using the following function 
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            GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC); 
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       (++) Configure these FSMC pins in alternate function mode by calling the function
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            GPIO_Init();    
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   (#) Declare a FSMC_NORSRAMInitTypeDef structure, for example:
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          FSMC_NORSRAMInitTypeDef  FSMC_NORSRAMInitStructure;
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      and fill the FSMC_NORSRAMInitStructure variable with the allowed values of
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      the structure member.
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   (#) Initialize the NOR/SRAM Controller by calling the function
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          FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); 
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   (#) Then enable the NOR/SRAM Bank, for example:
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          FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM2, ENABLE);  
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   (#) At this stage you can read/write from/to the memory connected to the NOR/SRAM Bank. 
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@endverbatim
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  * @{
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  */
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/**
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  * @brief  De-initializes the FSMC NOR/SRAM Banks registers to their default 
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  *   reset values.
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  * @param  FSMC_Bank: specifies the FSMC Bank to be used
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  *          This parameter can be one of the following values:
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  *            @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1  
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  *            @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 
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  *            @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 
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  *            @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 
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  * @retval None
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  */
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void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)
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{
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  /* Check the parameter */
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  assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
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  /* FSMC_Bank1_NORSRAM1 */
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  if(FSMC_Bank == FSMC_Bank1_NORSRAM1)
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  {
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    FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;    
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  }
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  /* FSMC_Bank1_NORSRAM2,  FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */
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  else
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  {   
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    FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; 
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  }
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  FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;
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  FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;  
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}
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/**
141
  * @brief  Initializes the FSMC NOR/SRAM Banks according to the specified
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  *         parameters in the FSMC_NORSRAMInitStruct.
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  * @param  FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef structure
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  *         that contains the configuration information for the FSMC NOR/SRAM 
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  *         specified Banks.                       
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  * @retval None
147
  */
148
void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
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{ 
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  /* Check the parameters */
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  assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));
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  assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));
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  assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));
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  assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));
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  assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));
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  assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait));
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  assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));
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  assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));
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  assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));
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  assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));
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  assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));
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  assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));
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  assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));  
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  assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));
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  assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));
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  assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));
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  assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));
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  assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));
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  assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));
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  assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode)); 
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  /* Bank1 NOR/SRAM control register configuration */ 
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  FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 
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            (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
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            FSMC_NORSRAMInitStruct->FSMC_MemoryType |
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            FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
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            FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
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            FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait |
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            FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
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            FSMC_NORSRAMInitStruct->FSMC_WrapMode |
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            FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
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            FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
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            FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
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            FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
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            FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
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  if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
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  {
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    FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_SET;
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  }
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  /* Bank1 NOR/SRAM timing register configuration */
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  FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] = 
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            (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
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            (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
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            (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
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            (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
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            (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
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            (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
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             FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
199
            
200
    
201
  /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
202
  if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
203
  {
204
    assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));
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    assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));
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    assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));
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    assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));
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    assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));
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    assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));
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    FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 
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              (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
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              (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
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              (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
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              (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
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              (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
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               FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
217
  }
218
  else
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  {
220
    FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
221
  }
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}
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/**
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  * @brief  Fills each FSMC_NORSRAMInitStruct member with its default value.
226
  * @param  FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef structure 
227
  *         which will be initialized.
228
  * @retval None
229
  */
230
void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
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{  
232
  /* Reset NOR/SRAM Init structure parameters values */
233
  FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;
234
  FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;
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  FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;
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  FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
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  FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
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  FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
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  FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
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  FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;
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  FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
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  FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;
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  FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
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  FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
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  FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;
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  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;
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  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;
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  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;
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  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
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  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;
251
  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;
252
  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; 
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  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;
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  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;
255
  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;
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  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
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  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;
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  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;
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  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
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}
261

    
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/**
263
  * @brief  Enables or disables the specified NOR/SRAM Memory Bank.
264
  * @param  FSMC_Bank: specifies the FSMC Bank to be used
265
  *          This parameter can be one of the following values:
266
  *            @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1  
267
  *            @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 
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  *            @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 
269
  *            @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 
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  * @param  NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
271
  * @retval None
272
  */
273
void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)
274
{
275
  assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
276
  assert_param(IS_FUNCTIONAL_STATE(NewState));
277
  
278
  if (NewState != DISABLE)
279
  {
280
    /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */
281
    FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_SET;
282
  }
283
  else
284
  {
285
    /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */
286
    FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_RESET;
287
  }
288
}
289
/**
290
  * @}
291
  */
292

    
293
/** @defgroup FSMC_Group2 NAND Controller functions
294
 *  @brief   NAND Controller functions 
295
 *
296
@verbatim   
297
 ===============================================================================
298
                    ##### NAND Controller functions #####
299
 ===============================================================================  
300

301
 [..]  The following sequence should be followed to configure the FSMC to interface 
302
       with 8-bit or 16-bit NAND memory connected to the NAND Bank:
303
 
304
  (#) Enable the clock for the FSMC and associated GPIOs using the following functions:
305
      (++)  RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE);
306
      (++)  RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
307

308
  (#) FSMC pins configuration 
309
      (++) Connect the involved FSMC pins to AF12 using the following function 
310
           GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC); 
311
      (++) Configure these FSMC pins in alternate function mode by calling the function
312
           GPIO_Init();    
313
       
314
  (#) Declare a FSMC_NANDInitTypeDef structure, for example:
315
      FSMC_NANDInitTypeDef  FSMC_NANDInitStructure;
316
      and fill the FSMC_NANDInitStructure variable with the allowed values of
317
      the structure member.
318
      
319
  (#) Initialize the NAND Controller by calling the function
320
      FSMC_NANDInit(&FSMC_NANDInitStructure); 
321

322
  (#) Then enable the NAND Bank, for example:
323
      FSMC_NANDCmd(FSMC_Bank3_NAND, ENABLE);  
324

325
  (#) At this stage you can read/write from/to the memory connected to the NAND Bank. 
326
   
327
 [..]
328
  (@) To enable the Error Correction Code (ECC), you have to use the function
329
      FSMC_NANDECCCmd(FSMC_Bank3_NAND, ENABLE);  
330
 [..]
331
  (@) and to get the current ECC value you have to use the function
332
      ECCval = FSMC_GetECC(FSMC_Bank3_NAND); 
333

334
@endverbatim
335
  * @{
336
  */
337
  
338
/**
339
  * @brief  De-initializes the FSMC NAND Banks registers to their default reset values.
340
  * @param  FSMC_Bank: specifies the FSMC Bank to be used
341
  *          This parameter can be one of the following values:
342
  *            @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
343
  *            @arg FSMC_Bank3_NAND: FSMC Bank3 NAND 
344
  * @retval None
345
  */
346
void FSMC_NANDDeInit(uint32_t FSMC_Bank)
347
{
348
  /* Check the parameter */
349
  assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
350
  
351
  if(FSMC_Bank == FSMC_Bank2_NAND)
352
  {
353
    /* Set the FSMC_Bank2 registers to their reset values */
354
    FSMC_Bank2->PCR2 = 0x00000018;
355
    FSMC_Bank2->SR2 = 0x00000040;
356
    FSMC_Bank2->PMEM2 = 0xFCFCFCFC;
357
    FSMC_Bank2->PATT2 = 0xFCFCFCFC;  
358
  }
359
  /* FSMC_Bank3_NAND */  
360
  else
361
  {
362
    /* Set the FSMC_Bank3 registers to their reset values */
363
    FSMC_Bank3->PCR3 = 0x00000018;
364
    FSMC_Bank3->SR3 = 0x00000040;
365
    FSMC_Bank3->PMEM3 = 0xFCFCFCFC;
366
    FSMC_Bank3->PATT3 = 0xFCFCFCFC; 
367
  }  
368
}
369

    
370
/**
371
  * @brief  Initializes the FSMC NAND Banks according to the specified parameters
372
  *         in the FSMC_NANDInitStruct.
373
  * @param  FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef structure that
374
  *         contains the configuration information for the FSMC NAND specified Banks.                       
375
  * @retval None
376
  */
377
void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
378
{
379
  uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; 
380
    
381
  /* Check the parameters */
382
  assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank));
383
  assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature));
384
  assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth));
385
  assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC));
386
  assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize));
387
  assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime));
388
  assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime));
389
  assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
390
  assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
391
  assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
392
  assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
393
  assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
394
  assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
395
  assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
396
  assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
397
  
398
  /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */
399
  tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature |
400
            PCR_MEMORYTYPE_NAND |
401
            FSMC_NANDInitStruct->FSMC_MemoryDataWidth |
402
            FSMC_NANDInitStruct->FSMC_ECC |
403
            FSMC_NANDInitStruct->FSMC_ECCPageSize |
404
            (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )|
405
            (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);
406
            
407
  /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */
408
  tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
409
            (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
410
            (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
411
            (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); 
412
            
413
  /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */
414
  tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
415
            (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
416
            (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
417
            (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
418
  
419
  if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
420
  {
421
    /* FSMC_Bank2_NAND registers configuration */
422
    FSMC_Bank2->PCR2 = tmppcr;
423
    FSMC_Bank2->PMEM2 = tmppmem;
424
    FSMC_Bank2->PATT2 = tmppatt;
425
  }
426
  else
427
  {
428
    /* FSMC_Bank3_NAND registers configuration */
429
    FSMC_Bank3->PCR3 = tmppcr;
430
    FSMC_Bank3->PMEM3 = tmppmem;
431
    FSMC_Bank3->PATT3 = tmppatt;
432
  }
433
}
434

    
435

    
436
/**
437
  * @brief  Fills each FSMC_NANDInitStruct member with its default value.
438
  * @param  FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef structure which
439
  *         will be initialized.
440
  * @retval None
441
  */
442
void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
443
{ 
444
  /* Reset NAND Init structure parameters values */
445
  FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND;
446
  FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
447
  FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
448
  FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable;
449
  FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes;
450
  FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0;
451
  FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0;
452
  FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
453
  FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
454
  FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
455
  FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
456
  FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
457
  FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
458
  FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
459
  FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;          
460
}
461

    
462
/**
463
  * @brief  Enables or disables the specified NAND Memory Bank.
464
  * @param  FSMC_Bank: specifies the FSMC Bank to be used
465
  *          This parameter can be one of the following values:
466
  *            @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
467
  *            @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
468
  * @param  NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
469
  * @retval None
470
  */
471
void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState)
472
{
473
  assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
474
  assert_param(IS_FUNCTIONAL_STATE(NewState));
475
  
476
  if (NewState != DISABLE)
477
  {
478
    /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */
479
    if(FSMC_Bank == FSMC_Bank2_NAND)
480
    {
481
      FSMC_Bank2->PCR2 |= PCR_PBKEN_SET;
482
    }
483
    else
484
    {
485
      FSMC_Bank3->PCR3 |= PCR_PBKEN_SET;
486
    }
487
  }
488
  else
489
  {
490
    /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */
491
    if(FSMC_Bank == FSMC_Bank2_NAND)
492
    {
493
      FSMC_Bank2->PCR2 &= PCR_PBKEN_RESET;
494
    }
495
    else
496
    {
497
      FSMC_Bank3->PCR3 &= PCR_PBKEN_RESET;
498
    }
499
  }
500
}
501
/**
502
  * @brief  Enables or disables the FSMC NAND ECC feature.
503
  * @param  FSMC_Bank: specifies the FSMC Bank to be used
504
  *          This parameter can be one of the following values:
505
  *            @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
506
  *            @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
507
  * @param  NewState: new state of the FSMC NAND ECC feature.  
508
  *          This parameter can be: ENABLE or DISABLE.
509
  * @retval None
510
  */
511
void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState)
512
{
513
  assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
514
  assert_param(IS_FUNCTIONAL_STATE(NewState));
515
  
516
  if (NewState != DISABLE)
517
  {
518
    /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */
519
    if(FSMC_Bank == FSMC_Bank2_NAND)
520
    {
521
      FSMC_Bank2->PCR2 |= PCR_ECCEN_SET;
522
    }
523
    else
524
    {
525
      FSMC_Bank3->PCR3 |= PCR_ECCEN_SET;
526
    }
527
  }
528
  else
529
  {
530
    /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */
531
    if(FSMC_Bank == FSMC_Bank2_NAND)
532
    {
533
      FSMC_Bank2->PCR2 &= PCR_ECCEN_RESET;
534
    }
535
    else
536
    {
537
      FSMC_Bank3->PCR3 &= PCR_ECCEN_RESET;
538
    }
539
  }
540
}
541

    
542
/**
543
  * @brief  Returns the error correction code register value.
544
  * @param  FSMC_Bank: specifies the FSMC Bank to be used
545
  *          This parameter can be one of the following values:
546
  *            @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
547
  *            @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
548
  * @retval The Error Correction Code (ECC) value.
549
  */
550
uint32_t FSMC_GetECC(uint32_t FSMC_Bank)
551
{
552
  uint32_t eccval = 0x00000000;
553
  
554
  if(FSMC_Bank == FSMC_Bank2_NAND)
555
  {
556
    /* Get the ECCR2 register value */
557
    eccval = FSMC_Bank2->ECCR2;
558
  }
559
  else
560
  {
561
    /* Get the ECCR3 register value */
562
    eccval = FSMC_Bank3->ECCR3;
563
  }
564
  /* Return the error correction code value */
565
  return(eccval);
566
}
567
/**
568
  * @}
569
  */
570

    
571
/** @defgroup FSMC_Group3 PCCARD Controller functions
572
 *  @brief   PCCARD Controller functions 
573
 *
574
@verbatim   
575
 ===============================================================================
576
                    ##### PCCARD Controller functions #####
577
 ===============================================================================  
578

579
 [..]  he following sequence should be followed to configure the FSMC to interface 
580
       with 16-bit PC Card compatible memory connected to the PCCARD Bank:
581
 
582
  (#)  Enable the clock for the FSMC and associated GPIOs using the following functions:
583
       (++)  RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE);
584
       (++)  RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
585

586
  (#) FSMC pins configuration 
587
       (++) Connect the involved FSMC pins to AF12 using the following function 
588
            GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC); 
589
       (++) Configure these FSMC pins in alternate function mode by calling the function
590
            GPIO_Init();    
591
       
592
  (#) Declare a FSMC_PCCARDInitTypeDef structure, for example:
593
      FSMC_PCCARDInitTypeDef  FSMC_PCCARDInitStructure;
594
      and fill the FSMC_PCCARDInitStructure variable with the allowed values of
595
      the structure member.
596
      
597
  (#) Initialize the PCCARD Controller by calling the function
598
      FSMC_PCCARDInit(&FSMC_PCCARDInitStructure); 
599

600
  (#) Then enable the PCCARD Bank:
601
      FSMC_PCCARDCmd(ENABLE);  
602

603
  (#) At this stage you can read/write from/to the memory connected to the PCCARD Bank. 
604
 
605
@endverbatim
606
  * @{
607
  */
608

    
609
/**
610
  * @brief  De-initializes the FSMC PCCARD Bank registers to their default reset values.
611
  * @param  None                       
612
  * @retval None
613
  */
614
void FSMC_PCCARDDeInit(void)
615
{
616
  /* Set the FSMC_Bank4 registers to their reset values */
617
  FSMC_Bank4->PCR4 = 0x00000018; 
618
  FSMC_Bank4->SR4 = 0x00000000;        
619
  FSMC_Bank4->PMEM4 = 0xFCFCFCFC;
620
  FSMC_Bank4->PATT4 = 0xFCFCFCFC;
621
  FSMC_Bank4->PIO4 = 0xFCFCFCFC;
622
}
623

    
624
/**
625
  * @brief  Initializes the FSMC PCCARD Bank according to the specified parameters
626
  *         in the FSMC_PCCARDInitStruct.
627
  * @param  FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef structure
628
  *         that contains the configuration information for the FSMC PCCARD Bank.                       
629
  * @retval None
630
  */
631
void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
632
{
633
  /* Check the parameters */
634
  assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature));
635
  assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime));
636
  assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime));
637
 
638
  assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
639
  assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
640
  assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
641
  assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
642
  
643
  assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
644
  assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
645
  assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
646
  assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
647
  assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime));
648
  assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime));
649
  assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime));
650
  assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime));
651
  
652
  /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */
653
  FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature |
654
                     FSMC_MemoryDataWidth_16b |  
655
                     (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) |
656
                     (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13);
657
            
658
  /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */
659
  FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
660
                      (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
661
                      (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
662
                      (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); 
663
            
664
  /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */
665
  FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
666
                      (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
667
                      (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
668
                      (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);        
669
            
670
  /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */
671
  FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime |
672
                     (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
673
                     (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
674
                     (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24);             
675
}
676

    
677
/**
678
  * @brief  Fills each FSMC_PCCARDInitStruct member with its default value.
679
  * @param  FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef structure
680
  *         which will be initialized.
681
  * @retval None
682
  */
683
void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
684
{
685
  /* Reset PCCARD Init structure parameters values */
686
  FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
687
  FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0;
688
  FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0;
689
  FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
690
  FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
691
  FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
692
  FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
693
  FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
694
  FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
695
  FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
696
  FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;        
697
  FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC;
698
  FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
699
  FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
700
  FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
701
}
702

    
703
/**
704
  * @brief  Enables or disables the PCCARD Memory Bank.
705
  * @param  NewState: new state of the PCCARD Memory Bank.  
706
  *          This parameter can be: ENABLE or DISABLE.
707
  * @retval None
708
  */
709
void FSMC_PCCARDCmd(FunctionalState NewState)
710
{
711
  assert_param(IS_FUNCTIONAL_STATE(NewState));
712
  
713
  if (NewState != DISABLE)
714
  {
715
    /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */
716
    FSMC_Bank4->PCR4 |= PCR_PBKEN_SET;
717
  }
718
  else
719
  {
720
    /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */
721
    FSMC_Bank4->PCR4 &= PCR_PBKEN_RESET;
722
  }
723
}
724
/**
725
  * @}
726
  */
727

    
728
/** @defgroup FSMC_Group4  Interrupts and flags management functions
729
 *  @brief    Interrupts and flags management functions
730
 *
731
@verbatim   
732
 ===============================================================================
733
             ##### Interrupts and flags management functions #####
734
 ===============================================================================   
735

736
@endverbatim
737
  * @{
738
  */
739

    
740
/**
741
  * @brief  Enables or disables the specified FSMC interrupts.
742
  * @param  FSMC_Bank: specifies the FSMC Bank to be used
743
  *          This parameter can be one of the following values:
744
  *            @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
745
  *            @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
746
  *            @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
747
  * @param  FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled.
748
  *          This parameter can be any combination of the following values:
749
  *            @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. 
750
  *            @arg FSMC_IT_Level: Level edge detection interrupt.
751
  *            @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
752
  * @param  NewState: new state of the specified FSMC interrupts.
753
  *          This parameter can be: ENABLE or DISABLE.
754
  * @retval None
755
  */
756
void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)
757
{
758
  assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
759
  assert_param(IS_FSMC_IT(FSMC_IT));        
760
  assert_param(IS_FUNCTIONAL_STATE(NewState));
761
  
762
  if (NewState != DISABLE)
763
  {
764
    /* Enable the selected FSMC_Bank2 interrupts */
765
    if(FSMC_Bank == FSMC_Bank2_NAND)
766
    {
767
      FSMC_Bank2->SR2 |= FSMC_IT;
768
    }
769
    /* Enable the selected FSMC_Bank3 interrupts */
770
    else if (FSMC_Bank == FSMC_Bank3_NAND)
771
    {
772
      FSMC_Bank3->SR3 |= FSMC_IT;
773
    }
774
    /* Enable the selected FSMC_Bank4 interrupts */
775
    else
776
    {
777
      FSMC_Bank4->SR4 |= FSMC_IT;    
778
    }
779
  }
780
  else
781
  {
782
    /* Disable the selected FSMC_Bank2 interrupts */
783
    if(FSMC_Bank == FSMC_Bank2_NAND)
784
    {
785
      
786
      FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT;
787
    }
788
    /* Disable the selected FSMC_Bank3 interrupts */
789
    else if (FSMC_Bank == FSMC_Bank3_NAND)
790
    {
791
      FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT;
792
    }
793
    /* Disable the selected FSMC_Bank4 interrupts */
794
    else
795
    {
796
      FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT;    
797
    }
798
  }
799
}
800

    
801
/**
802
  * @brief  Checks whether the specified FSMC flag is set or not.
803
  * @param  FSMC_Bank: specifies the FSMC Bank to be used
804
  *          This parameter can be one of the following values:
805
  *            @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
806
  *            @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
807
  *            @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
808
  * @param  FSMC_FLAG: specifies the flag to check.
809
  *          This parameter can be one of the following values:
810
  *            @arg FSMC_FLAG_RisingEdge: Rising edge detection Flag.
811
  *            @arg FSMC_FLAG_Level: Level detection Flag.
812
  *            @arg FSMC_FLAG_FallingEdge: Falling edge detection Flag.
813
  *            @arg FSMC_FLAG_FEMPT: Fifo empty Flag. 
814
  * @retval The new state of FSMC_FLAG (SET or RESET).
815
  */
816
FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
817
{
818
  FlagStatus bitstatus = RESET;
819
  uint32_t tmpsr = 0x00000000;
820
  
821
  /* Check the parameters */
822
  assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
823
  assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG));
824
  
825
  if(FSMC_Bank == FSMC_Bank2_NAND)
826
  {
827
    tmpsr = FSMC_Bank2->SR2;
828
  }  
829
  else if(FSMC_Bank == FSMC_Bank3_NAND)
830
  {
831
    tmpsr = FSMC_Bank3->SR3;
832
  }
833
  /* FSMC_Bank4_PCCARD*/
834
  else
835
  {
836
    tmpsr = FSMC_Bank4->SR4;
837
  } 
838
  
839
  /* Get the flag status */
840
  if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET )
841
  {
842
    bitstatus = SET;
843
  }
844
  else
845
  {
846
    bitstatus = RESET;
847
  }
848
  /* Return the flag status */
849
  return bitstatus;
850
}
851

    
852
/**
853
  * @brief  Clears the FSMC's pending flags.
854
  * @param  FSMC_Bank: specifies the FSMC Bank to be used
855
  *          This parameter can be one of the following values:
856
  *            @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
857
  *            @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
858
  *            @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
859
  * @param  FSMC_FLAG: specifies the flag to clear.
860
  *          This parameter can be any combination of the following values:
861
  *            @arg FSMC_FLAG_RisingEdge: Rising edge detection Flag.
862
  *            @arg FSMC_FLAG_Level: Level detection Flag.
863
  *            @arg FSMC_FLAG_FallingEdge: Falling edge detection Flag.
864
  * @retval None
865
  */
866
void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
867
{
868
 /* Check the parameters */
869
  assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
870
  assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ;
871
    
872
  if(FSMC_Bank == FSMC_Bank2_NAND)
873
  {
874
    FSMC_Bank2->SR2 &= ~FSMC_FLAG; 
875
  }  
876
  else if(FSMC_Bank == FSMC_Bank3_NAND)
877
  {
878
    FSMC_Bank3->SR3 &= ~FSMC_FLAG;
879
  }
880
  /* FSMC_Bank4_PCCARD*/
881
  else
882
  {
883
    FSMC_Bank4->SR4 &= ~FSMC_FLAG;
884
  }
885
}
886

    
887
/**
888
  * @brief  Checks whether the specified FSMC interrupt has occurred or not.
889
  * @param  FSMC_Bank: specifies the FSMC Bank to be used
890
  *          This parameter can be one of the following values:
891
  *            @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
892
  *            @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
893
  *            @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
894
  * @param  FSMC_IT: specifies the FSMC interrupt source to check.
895
  *          This parameter can be one of the following values:
896
  *            @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. 
897
  *            @arg FSMC_IT_Level: Level edge detection interrupt.
898
  *            @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. 
899
  * @retval The new state of FSMC_IT (SET or RESET).
900
  */
901
ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT)
902
{
903
  ITStatus bitstatus = RESET;
904
  uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0; 
905
  
906
  /* Check the parameters */
907
  assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
908
  assert_param(IS_FSMC_GET_IT(FSMC_IT));
909
  
910
  if(FSMC_Bank == FSMC_Bank2_NAND)
911
  {
912
    tmpsr = FSMC_Bank2->SR2;
913
  }  
914
  else if(FSMC_Bank == FSMC_Bank3_NAND)
915
  {
916
    tmpsr = FSMC_Bank3->SR3;
917
  }
918
  /* FSMC_Bank4_PCCARD*/
919
  else
920
  {
921
    tmpsr = FSMC_Bank4->SR4;
922
  } 
923
  
924
  itstatus = tmpsr & FSMC_IT;
925
  
926
  itenable = tmpsr & (FSMC_IT >> 3);
927
  if ((itstatus != (uint32_t)RESET)  && (itenable != (uint32_t)RESET))
928
  {
929
    bitstatus = SET;
930
  }
931
  else
932
  {
933
    bitstatus = RESET;
934
  }
935
  return bitstatus; 
936
}
937

    
938
/**
939
  * @brief  Clears the FSMC's interrupt pending bits.
940
  * @param  FSMC_Bank: specifies the FSMC Bank to be used
941
  *          This parameter can be one of the following values:
942
  *            @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
943
  *            @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
944
  *            @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
945
  * @param  FSMC_IT: specifies the interrupt pending bit to clear.
946
  *          This parameter can be any combination of the following values:
947
  *            @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. 
948
  *            @arg FSMC_IT_Level: Level edge detection interrupt.
949
  *            @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
950
  * @retval None
951
  */
952
void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT)
953
{
954
  /* Check the parameters */
955
  assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
956
  assert_param(IS_FSMC_IT(FSMC_IT));
957
    
958
  if(FSMC_Bank == FSMC_Bank2_NAND)
959
  {
960
    FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3); 
961
  }  
962
  else if(FSMC_Bank == FSMC_Bank3_NAND)
963
  {
964
    FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3);
965
  }
966
  /* FSMC_Bank4_PCCARD*/
967
  else
968
  {
969
    FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3);
970
  }
971
}
972

    
973
/**
974
  * @}
975
  */ 
976

    
977
/**
978
  * @}
979
  */ 
980

    
981
/**
982
  * @}
983
  */
984

    
985
/**
986
  * @}
987
  */
988

    
989
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/