AMiRo-OS

/************************************************************************************//**

* \file         Demo\ARMCM3_STM32_Olimex_STM32P103_GCC\Boot\main.c

* \brief        Bootloader application source file.

* \ingroup      Boot_ARMCM3_STM32_Olimex_STM32P103_GCC

* \internal

*----------------------------------------------------------------------------------------

*                          C O P Y R I G H T

*----------------------------------------------------------------------------------------

*   Copyright (c) 2012  by Feaser    http://www.feaser.com    All rights reserved

*

*----------------------------------------------------------------------------------------

*                            L I C E N S E

*----------------------------------------------------------------------------------------

* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or

* modify it under the terms of the GNU General Public License as published by the Free

* Software Foundation, either version 3 of the License, or (at your option) any later

* version.

*

* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;

* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR

* PURPOSE. See the GNU General Public License for more details.

*

* You should have received a copy of the GNU General Public License along with OpenBLT.

* If not, see <http://www.gnu.org/licenses/>.

*

* A special exception to the GPL is included to allow you to distribute a combined work

* that includes OpenBLT without being obliged to provide the source code for any

* proprietary components. The exception text is included at the bottom of the license

* file <license.html>.

*

* \endinternal

****************************************************************************************/

/****************************************************************************************

* Include files

****************************************************************************************/

#include "boot.h"                                /* bootloader generic header          */

#include "timer.h"

#include "ARMCM3_STM32/types.h"

#include "AMiRo/amiroblt.h"

#include "helper.h"

#include "iodef.h"

/****************************************************************************************

* Defines

****************************************************************************************/

/****************************************************************************************

* Function prototypes and static variables

****************************************************************************************/

static void Init(void);

static void initGpio();

static void initExti();

void configGpioForShutdown();

ErrorStatus handleWarmReset();

ErrorStatus shutdownDisambiguationProcedure(const uint8_t type);

void shutdownToTransportation(const blt_bool exec_disambiguation);

void shutdownToDeepsleep(const blt_bool exec_disambiguation);

void shutdownToHibernate(const blt_bool exec_disambiguation);

void shutdownAndRestart(const blt_bool exec_disambiguation);

volatile blBackupRegister_t backup_reg;

/****************************************************************************************

* Callback configuration

****************************************************************************************/

void blCallbackShutdownTransportation(void);

void blCallbackShutdownDeepsleep(void);

void blCallbackShutdownHibernate(void);

void blCallbackShutdownRestart(void);

void blCallbackHandleShutdownRequest(void);

const blCallbackTable_t cbtable __attribute__ ((section ("_callback_table"))) = {

  .magicNumber = BL_MAGIC_NUMBER,

  .vBootloader = {BL_VERSION_ID_AMiRoBLT_Release, BL_VERSION_MAJOR, BL_VERSION_MINOR, 0},

  .vSSSP = {BL_VERSION_ID_SSSP, BL_SSSP_VERSION_MAJOR, BL_SSSP_VERSION_MINOR, 0},

  .vCompiler = {BL_VERSION_ID_GCC, __GNUC__, __GNUC_MINOR__, __GNUC_PATCHLEVEL__},  // currently only GCC is supported

  .cbShutdownHibernate = blCallbackShutdownHibernate,

  .cbShutdownDeepsleep = blCallbackShutdownDeepsleep,

  .cbShutdownTransportation = blCallbackShutdownTransportation,

  .cbShutdownRestart = blCallbackShutdownRestart,

  .cbHandleShutdownRequest = blCallbackHandleShutdownRequest,

  .cb5 = (void*)0,

  .cb6 = (void*)0,

  .cb7 = (void*)0,

  .cb8 = (void*)0,

  .cb9 = (void*)0,

  .cb10 = (void*)0,

  .cb11 = (void*)0

};

/************************************************************************************//**

** \brief     This is the entry point for the bootloader application and is called

**            by the reset interrupt vector after the C-startup routines executed.

** \return    Program return code.

**

****************************************************************************************/

int main(void)

{

  /* initialize the microcontroller */

  Init();

  /* activate some required clocks */

  RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);

  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOD, ENABLE);

  /* initialize GPIOs and EXTI lines */

  initGpio();

  setLed(BLT_TRUE);

  initExti();

  /* initialize the timer */

  TimerInit();

  /* detect the primary reason for this wakeup/restart */

  backup_reg.wakeup_pri_reason =

      ((RCC_GetFlagStatus(RCC_FLAG_LPWRRST) == SET) ? BL_WAKEUP_PRI_RSN_LPWRRST : 0) |

      ((RCC_GetFlagStatus(RCC_FLAG_WWDGRST) == SET) ? BL_WAKEUP_PRI_RSN_WWDGRST : 0) |

      ((RCC_GetFlagStatus(RCC_FLAG_IWDGRST) == SET) ? BL_WAKEUP_PRI_RSN_IWDGRST : 0) |

      ((RCC_GetFlagStatus(RCC_FLAG_SFTRST) == SET) ? BL_WAKEUP_PRI_RSN_SFTRST : 0)   |

      ((RCC_GetFlagStatus(RCC_FLAG_PORRST) == SET) ? BL_WAKEUP_PRI_RSN_PORRST : 0)   |

      ((RCC_GetFlagStatus(RCC_FLAG_PINRST) == SET) ? BL_WAKEUP_PRI_RSN_PINRST : 0)   |

      ((PWR_GetFlagStatus(PWR_FLAG_WU) == SET) ? BL_WAKEUP_PRI_RSN_WKUP : 0);

  /* for this module there is no secondary wakeup reason */

  backup_reg.wakeup_sec_reason = BL_WAKEUP_SEC_RSN_UNKNOWN;

  /* clear the flags */

  RCC_ClearFlag();

  PWR_ClearFlag(PWR_FLAG_WU);

  setLed(BLT_FALSE);

  /* handle different wakeup/reset reasons */

  ErrorStatus status = ERROR;

  if (backup_reg.wakeup_pri_reason & BL_WAKEUP_PRI_RSN_PINRST) {

    /* system was woken via NRST pin */

    status = handleWarmReset();

  } else {

    /* system was woken/reset for an unexpected reason */

    blinkSOS(1);

    status = handleWarmReset();

  }

  /* if something went wrong, signal this failure */

  if (status != SUCCESS) {

    blinkSOSinf();

  }

  return 0;

} /*** end of main ***/

/************************************************************************************//**

** \brief     Initializes the microcontroller.

** \return    none.

**

****************************************************************************************/

static void Init(void)

{

  volatile blt_int32u StartUpCounter = 0, HSEStatus = 0;

  blt_int32u pll_multiplier;

#if (BOOT_FILE_LOGGING_ENABLE > 0) && (BOOT_COM_UART_ENABLE == 0) && (BOOT_GATE_UART_ENABLE == 0)

  GPIO_InitTypeDef  GPIO_InitStruct;

  USART_InitTypeDef USART_InitStruct;

#endif

  /* reset the RCC clock configuration to the default reset state (for debug purpose) */

  /* set HSION bit */

  RCC->CR |= (blt_int32u)0x00000001;

  /* reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */

  RCC->CFGR &= (blt_int32u)0xF8FF0000;

  /* reset HSEON, CSSON and PLLON bits */

  RCC->CR &= (blt_int32u)0xFEF6FFFF;

  /* reset HSEBYP bit */

  RCC->CR &= (blt_int32u)0xFFFBFFFF;

  /* reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */

  RCC->CFGR &= (blt_int32u)0xFF80FFFF;

  /* disable all interrupts and clear pending bits  */

  RCC->CIR = 0x009F0000;

  /* enable HSE */

  RCC->CR |= ((blt_int32u)RCC_CR_HSEON);

  /* wait till HSE is ready and if Time out is reached exit */

  do

  {

    HSEStatus = RCC->CR & RCC_CR_HSERDY;

    StartUpCounter++;

  }

  while((HSEStatus == 0) && (StartUpCounter != 1500));

  /* check if time out was reached */

  if ((RCC->CR & RCC_CR_HSERDY) == RESET)

  {

    /* cannot continue when HSE is not ready */

    ASSERT_RT(BLT_FALSE);

  }

  /* enable flash prefetch buffer */

  FLASH->ACR |= FLASH_ACR_PRFTBE;

  /* reset flash wait state configuration to default 0 wait states */

  FLASH->ACR &= (blt_int32u)((blt_int32u)~FLASH_ACR_LATENCY);

#if (BOOT_CPU_SYSTEM_SPEED_KHZ > 48000)

  /* configure 2 flash wait states */

  FLASH->ACR |= (blt_int32u)FLASH_ACR_LATENCY_2;

#elif (BOOT_CPU_SYSTEM_SPEED_KHZ > 24000)

  /* configure 1 flash wait states */

  FLASH->ACR |= (blt_int32u)FLASH_ACR_LATENCY_1;

#endif

  /* HCLK = SYSCLK */

  RCC->CFGR |= (blt_int32u)RCC_CFGR_HPRE_DIV1;

  /* PCLK2 = HCLK/2 */

  RCC->CFGR |= (blt_int32u)RCC_CFGR_PPRE2_DIV2;

  /* PCLK1 = HCLK/2 */

  RCC->CFGR |= (blt_int32u)RCC_CFGR_PPRE1_DIV2;

  /* reset PLL configuration */

  RCC->CFGR &= (blt_int32u)((blt_int32u)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | \

                                          RCC_CFGR_PLLMULL));

  /* assert that the pll_multiplier is between 2 and 16 */

  ASSERT_CT((BOOT_CPU_SYSTEM_SPEED_KHZ/BOOT_CPU_XTAL_SPEED_KHZ) >= 2);

  ASSERT_CT((BOOT_CPU_SYSTEM_SPEED_KHZ/BOOT_CPU_XTAL_SPEED_KHZ) <= 16);

  /* calculate multiplier value */

  pll_multiplier = BOOT_CPU_SYSTEM_SPEED_KHZ/BOOT_CPU_XTAL_SPEED_KHZ;

  /* convert to register value */

  pll_multiplier = (blt_int32u)((pll_multiplier - 2) << 18);

  /* set the PLL multiplier and clock source */

  RCC->CFGR |= (blt_int32u)(RCC_CFGR_PLLSRC_HSE | pll_multiplier);

  /* enable PLL */

  RCC->CR |= RCC_CR_PLLON;

  /* wait till PLL is ready */

  while((RCC->CR & RCC_CR_PLLRDY) == 0)

  {

  }

  /* select PLL as system clock source */

  RCC->CFGR &= (blt_int32u)((blt_int32u)~(RCC_CFGR_SW));

  RCC->CFGR |= (blt_int32u)RCC_CFGR_SW_PLL;

  /* wait till PLL is used as system clock source */

  while ((RCC->CFGR & (blt_int32u)RCC_CFGR_SWS) != (blt_int32u)0x08)

  {

  }

#if (BOOT_COM_CAN_ENABLE > 0 || BOOT_GATE_CAN_ENABLE > 0)

  /* enable clocks for CAN transmitter and receiver pins (GPIOB and AFIO) */

  RCC->APB2ENR |= (blt_int32u)(0x00000004 | 0x00000001);