Revision 470d0567 Target/Demo/ARMCM3_STM32F103_LightRing_GCC/Boot/main.c

View differences:

Target/Demo/ARMCM3_STM32F103_LightRing_GCC/Boot/main.c
23 23
* You should have received a copy of the GNU General Public License along with OpenBLT.
24 24
* If not, see <http://www.gnu.org/licenses/>.
25 25
*
26
* A special exception to the GPL is included to allow you to distribute a combined work 
27
* that includes OpenBLT without being obliged to provide the source code for any 
26
* A special exception to the GPL is included to allow you to distribute a combined work
27
* that includes OpenBLT without being obliged to provide the source code for any
28 28
* proprietary components. The exception text is included at the bottom of the license
29 29
* file <license.html>.
30
* 
30
*
31 31
* \endinternal
32 32
****************************************************************************************/
33 33

  
......
39 39
#include "stm32f10x_conf.h"                      /* STM32 peripheral drivers           */
40 40
#include "timer.h"
41 41
#include "ARMCM3_STM32/types.h"
42
#include "AMiRo/interfaces.h"
42
#include "AMiRo/amiroblt.h"
43 43
#include "AMiRo/helper.h"
44 44

  
45 45

  
......
127 127
void shutdownToHibernate(const blt_bool exec_disambiguation);
128 128
void shutdownAndRestart(const blt_bool exec_disambiguation);
129 129

  
130
volatile BlBackupRegister backup_reg;
130
volatile blBackupRegister_t backup_reg;
131 131

  
132 132
/****************************************************************************************
133 133
* Callback configuration
......
138 138
void blCallbackShutdownRestart(void);
139 139
void blCallbackHandleShutdownRequest(void);
140 140

  
141
const BlCallbackTable cbtable __attribute__ ((section ("_callback_table"))) = {
141
const blCallbackTable_t cbtable __attribute__ ((section ("_callback_table"))) = {
142 142
  .magicNumber = BL_MAGIC_NUMBER,
143
  .versionMajor = BL_VERSION_MAJOR,
144
  .versionMinor = BL_VERSION_MINOR,
145
  .versionHotfix = 0,
143
  .vBootloader = {BL_VERSION_ID_AMiRoBLT_Release, BL_VERSION_MAJOR, BL_VERSION_MINOR, 0},
144
  .vSSSP = {BL_VERSION_ID_SSSP, SSSP_VERSION_MAJOR, SSSP_VERSION_MINOR, 0},
145
  .vCompiler = {BL_VERSION_ID_GCC, __GNUC__, __GNUC_MINOR__, __GNUC_PATCHLEVEL__},  // currently only GCC is supported
146 146
  .cbShutdownHibernate = blCallbackShutdownHibernate,
147 147
  .cbShutdownDeepsleep = blCallbackShutdownDeepsleep,
148 148
  .cbShutdownTransportation = blCallbackShutdownTransportation,
......
158 158
};
159 159

  
160 160
/************************************************************************************//**
161
** \brief     This is the entry point for the bootloader application and is called 
161
** \brief     This is the entry point for the bootloader application and is called
162 162
**            by the reset interrupt vector after the C-startup routines executed.
163 163
** \return    Program return code.
164 164
**
......
219 219

  
220 220

  
221 221
/************************************************************************************//**
222
** \brief     Initializes the microcontroller. 
222
** \brief     Initializes the microcontroller.
223 223
** \return    none.
224 224
**
225 225
****************************************************************************************/
......
229 229
  blt_int32u pll_multiplier;
230 230
#if (BOOT_FILE_LOGGING_ENABLE > 0) && (BOOT_COM_UART_ENABLE == 0) && (BOOT_GATE_UART_ENABLE == 0)
231 231
  GPIO_InitTypeDef  GPIO_InitStruct;
232
  USART_InitTypeDef USART_InitStruct;  
233
#endif  
232
  USART_InitTypeDef USART_InitStruct;
233
#endif
234 234

  
235 235
  /* reset the RCC clock configuration to the default reset state (for debug purpose) */
236 236
  /* set HSION bit */
......
245 245
  RCC->CFGR &= (blt_int32u)0xFF80FFFF;
246 246
  /* disable all interrupts and clear pending bits  */
247 247
  RCC->CIR = 0x009F0000;
248
  /* enable HSE */    
248
  /* enable HSE */
249 249
  RCC->CR |= ((blt_int32u)RCC_CR_HSEON);
250 250
  /* wait till HSE is ready and if Time out is reached exit */
251 251
  do
252 252
  {
253 253
    HSEStatus = RCC->CR & RCC_CR_HSERDY;
254
    StartUpCounter++;  
255
  } 
254
    StartUpCounter++;
255
  }
256 256
  while((HSEStatus == 0) && (StartUpCounter != 1500));
257 257
  /* check if time out was reached */
258 258
  if ((RCC->CR & RCC_CR_HSERDY) == RESET)
......
266 266
  FLASH->ACR &= (blt_int32u)((blt_int32u)~FLASH_ACR_LATENCY);
267 267
#if (BOOT_CPU_SYSTEM_SPEED_KHZ > 48000)
268 268
  /* configure 2 flash wait states */
269
  FLASH->ACR |= (blt_int32u)FLASH_ACR_LATENCY_2;    
270
#elif (BOOT_CPU_SYSTEM_SPEED_KHZ > 24000)  
269
  FLASH->ACR |= (blt_int32u)FLASH_ACR_LATENCY_2;
270
#elif (BOOT_CPU_SYSTEM_SPEED_KHZ > 24000)
271 271
  /* configure 1 flash wait states */
272
  FLASH->ACR |= (blt_int32u)FLASH_ACR_LATENCY_1;    
272
  FLASH->ACR |= (blt_int32u)FLASH_ACR_LATENCY_1;
273 273
#endif
274 274
  /* HCLK = SYSCLK */
275 275
  RCC->CFGR |= (blt_int32u)RCC_CFGR_HPRE_DIV1;
......
297 297
  }
298 298
  /* select PLL as system clock source */
299 299
  RCC->CFGR &= (blt_int32u)((blt_int32u)~(RCC_CFGR_SW));
300
  RCC->CFGR |= (blt_int32u)RCC_CFGR_SW_PLL;    
300
  RCC->CFGR |= (blt_int32u)RCC_CFGR_SW_PLL;
301 301
  /* wait till PLL is used as system clock source */
302 302
  while ((RCC->CFGR & (blt_int32u)RCC_CFGR_SWS) != (blt_int32u)0x08)
303 303
  {
......
365 365
  GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
366 366
  GPIO_InitStruct.GPIO_Pin = GPIO_Pin_3;
367 367
  GPIO_Init(GPIOA, &GPIO_InitStruct);
368
  /* configure UART communcation parameters */  
368
  /* configure UART communcation parameters */
369 369
  USART_InitStruct.USART_BaudRate = BOOT_COM_UART_BAUDRATE;
370 370
  USART_InitStruct.USART_WordLength = USART_WordLength_8b;
371 371
  USART_InitStruct.USART_StopBits = USART_StopBits_1;

Also available in: Unified diff