amiro-blt / Target / Demo / ARMCM3_STM32F103_DiWheelDrive_GCC / Boot / lib / CMSIS / CM3 / DeviceSupport / ST / STM32F10x / system_stm32f10x.c @ 69661903
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1 | 69661903 | Thomas Schöpping | /**
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2 | ******************************************************************************
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3 | * @file system_stm32f10x.c
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4 | * @author MCD Application Team
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5 | * @version V3.5.0
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6 | * @date 11-March-2011
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7 | * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
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8 | *
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9 | * 1. This file provides two functions and one global variable to be called from
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10 | * user application:
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11 | * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
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12 | * factors, AHB/APBx prescalers and Flash settings).
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13 | * This function is called at startup just after reset and
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14 | * before branch to main program. This call is made inside
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15 | * the "startup_stm32f10x_xx.s" file.
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16 | *
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17 | * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
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18 | * by the user application to setup the SysTick
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19 | * timer or configure other parameters.
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20 | *
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21 | * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
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22 | * be called whenever the core clock is changed
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23 | * during program execution.
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24 | *
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25 | * 2. After each device reset the HSI (8 MHz) is used as system clock source.
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26 | * Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
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27 | * configure the system clock before to branch to main program.
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28 | *
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29 | * 3. If the system clock source selected by user fails to startup, the SystemInit()
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30 | * function will do nothing and HSI still used as system clock source. User can
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31 | * add some code to deal with this issue inside the SetSysClock() function.
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32 | *
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33 | * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
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34 | * the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
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35 | * When HSE is used as system clock source, directly or through PLL, and you
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36 | * are using different crystal you have to adapt the HSE value to your own
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37 | * configuration.
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38 | *
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39 | ******************************************************************************
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40 | * @attention
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41 | *
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42 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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43 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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44 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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45 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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46 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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47 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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48 | *
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49 | * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
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50 | ******************************************************************************
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51 | */
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52 | |||
53 | /** @addtogroup CMSIS
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54 | * @{
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55 | */
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56 | |||
57 | /** @addtogroup stm32f10x_system
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58 | * @{
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59 | */
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60 | |||
61 | /** @addtogroup STM32F10x_System_Private_Includes
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62 | * @{
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63 | */
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64 | |||
65 | #include "stm32f10x.h" |
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66 | |||
67 | /**
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68 | * @}
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69 | */
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70 | |||
71 | /** @addtogroup STM32F10x_System_Private_TypesDefinitions
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72 | * @{
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73 | */
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74 | |||
75 | /**
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76 | * @}
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77 | */
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78 | |||
79 | /** @addtogroup STM32F10x_System_Private_Defines
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80 | * @{
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81 | */
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82 | |||
83 | /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
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84 | frequency (after reset the HSI is used as SYSCLK source)
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85 |
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86 | IMPORTANT NOTE:
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87 | ==============
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88 | 1. After each device reset the HSI is used as System clock source.
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89 | |||
90 | 2. Please make sure that the selected System clock doesn't exceed your device's
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91 | maximum frequency.
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92 |
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93 | 3. If none of the define below is enabled, the HSI is used as System clock
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94 | source.
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95 | |||
96 | 4. The System clock configuration functions provided within this file assume that:
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97 | - For Low, Medium and High density Value line devices an external 8MHz
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98 | crystal is used to drive the System clock.
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99 | - For Low, Medium and High density devices an external 8MHz crystal is
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100 | used to drive the System clock.
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101 | - For Connectivity line devices an external 25MHz crystal is used to drive
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102 | the System clock.
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103 | If you are using different crystal you have to adapt those functions accordingly.
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104 | */
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105 | |||
106 | #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
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107 | /* #define SYSCLK_FREQ_HSE HSE_VALUE */
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108 | #define SYSCLK_FREQ_24MHz 24000000 |
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109 | #else
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110 | /* #define SYSCLK_FREQ_HSE HSE_VALUE */
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111 | /* #define SYSCLK_FREQ_24MHz 24000000 */
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112 | /* #define SYSCLK_FREQ_36MHz 36000000 */
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113 | /* #define SYSCLK_FREQ_48MHz 48000000 */
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114 | /* #define SYSCLK_FREQ_56MHz 56000000 */
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115 | #define SYSCLK_FREQ_72MHz 72000000 |
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116 | #endif
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117 | |||
118 | /*!< Uncomment the following line if you need to use external SRAM mounted
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119 | on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
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120 | STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
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121 | #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
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122 | /* #define DATA_IN_ExtSRAM */
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123 | #endif
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124 | |||
125 | /*!< Uncomment the following line if you need to relocate your vector Table in
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126 | Internal SRAM. */
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127 | /* #define VECT_TAB_SRAM */
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128 | #define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. |
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129 | This value must be a multiple of 0x200. */
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130 | |||
131 | |||
132 | /**
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133 | * @}
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134 | */
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135 | |||
136 | /** @addtogroup STM32F10x_System_Private_Macros
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137 | * @{
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138 | */
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139 | |||
140 | /**
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141 | * @}
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142 | */
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143 | |||
144 | /** @addtogroup STM32F10x_System_Private_Variables
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145 | * @{
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146 | */
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147 | |||
148 | /*******************************************************************************
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149 | * Clock Definitions
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150 | *******************************************************************************/
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151 | #ifdef SYSCLK_FREQ_HSE
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152 | uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */
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153 | #elif defined SYSCLK_FREQ_24MHz
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154 | uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */
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155 | #elif defined SYSCLK_FREQ_36MHz
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156 | uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */
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157 | #elif defined SYSCLK_FREQ_48MHz
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158 | uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */
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159 | #elif defined SYSCLK_FREQ_56MHz
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160 | uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */
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161 | #elif defined SYSCLK_FREQ_72MHz
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162 | uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */
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163 | #else /*!< HSI Selected as System Clock source */ |
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164 | uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */
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165 | #endif
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166 | |||
167 | __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; |
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168 | /**
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169 | * @}
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170 | */
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171 | |||
172 | /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
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173 | * @{
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174 | */
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175 | |||
176 | static void SetSysClock(void); |
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177 | |||
178 | #ifdef SYSCLK_FREQ_HSE
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179 | static void SetSysClockToHSE(void); |
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180 | #elif defined SYSCLK_FREQ_24MHz
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181 | static void SetSysClockTo24(void); |
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182 | #elif defined SYSCLK_FREQ_36MHz
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183 | static void SetSysClockTo36(void); |
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184 | #elif defined SYSCLK_FREQ_48MHz
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185 | static void SetSysClockTo48(void); |
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186 | #elif defined SYSCLK_FREQ_56MHz
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187 | static void SetSysClockTo56(void); |
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188 | #elif defined SYSCLK_FREQ_72MHz
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189 | static void SetSysClockTo72(void); |
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190 | #endif
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191 | |||
192 | #ifdef DATA_IN_ExtSRAM
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193 | static void SystemInit_ExtMemCtl(void); |
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194 | #endif /* DATA_IN_ExtSRAM */ |
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195 | |||
196 | /**
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197 | * @}
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198 | */
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199 | |||
200 | /** @addtogroup STM32F10x_System_Private_Functions
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201 | * @{
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202 | */
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203 | |||
204 | /**
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205 | * @brief Setup the microcontroller system
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206 | * Initialize the Embedded Flash Interface, the PLL and update the
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207 | * SystemCoreClock variable.
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208 | * @note This function should be used only after reset.
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209 | * @param None
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210 | * @retval None
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211 | */
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212 | void SystemInit (void) |
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213 | { |
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214 | /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
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215 | /* Set HSION bit */
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216 | RCC->CR |= (uint32_t)0x00000001;
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217 | |||
218 | /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
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219 | #ifndef STM32F10X_CL
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220 | RCC->CFGR &= (uint32_t)0xF8FF0000;
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221 | #else
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222 | RCC->CFGR &= (uint32_t)0xF0FF0000;
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223 | #endif /* STM32F10X_CL */ |
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224 | |||
225 | /* Reset HSEON, CSSON and PLLON bits */
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226 | RCC->CR &= (uint32_t)0xFEF6FFFF;
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227 | |||
228 | /* Reset HSEBYP bit */
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229 | RCC->CR &= (uint32_t)0xFFFBFFFF;
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230 | |||
231 | /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
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232 | RCC->CFGR &= (uint32_t)0xFF80FFFF;
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233 | |||
234 | #ifdef STM32F10X_CL
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235 | /* Reset PLL2ON and PLL3ON bits */
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236 | RCC->CR &= (uint32_t)0xEBFFFFFF;
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237 | |||
238 | /* Disable all interrupts and clear pending bits */
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239 | RCC->CIR = 0x00FF0000;
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240 | |||
241 | /* Reset CFGR2 register */
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242 | RCC->CFGR2 = 0x00000000;
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243 | #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
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244 | /* Disable all interrupts and clear pending bits */
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245 | RCC->CIR = 0x009F0000;
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246 | |||
247 | /* Reset CFGR2 register */
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248 | RCC->CFGR2 = 0x00000000;
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249 | #else
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250 | /* Disable all interrupts and clear pending bits */
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251 | RCC->CIR = 0x009F0000;
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252 | #endif /* STM32F10X_CL */ |
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253 | |||
254 | #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
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255 | #ifdef DATA_IN_ExtSRAM
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256 | SystemInit_ExtMemCtl(); |
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257 | #endif /* DATA_IN_ExtSRAM */ |
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258 | #endif
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259 | |||
260 | /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
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261 | /* Configure the Flash Latency cycles and enable prefetch buffer */
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262 | SetSysClock(); |
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263 | |||
264 | #ifdef VECT_TAB_SRAM
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265 | SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
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266 | #else
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267 | SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
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268 | #endif
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269 | } |
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270 | |||
271 | /**
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272 | * @brief Update SystemCoreClock variable according to Clock Register Values.
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273 | * The SystemCoreClock variable contains the core clock (HCLK), it can
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274 | * be used by the user application to setup the SysTick timer or configure
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275 | * other parameters.
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276 | *
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277 | * @note Each time the core clock (HCLK) changes, this function must be called
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278 | * to update SystemCoreClock variable value. Otherwise, any configuration
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279 | * based on this variable will be incorrect.
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280 | *
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281 | * @note - The system frequency computed by this function is not the real
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282 | * frequency in the chip. It is calculated based on the predefined
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283 | * constant and the selected clock source:
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284 | *
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285 | * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
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286 | *
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287 | * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
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288 | *
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289 | * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
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290 | * or HSI_VALUE(*) multiplied by the PLL factors.
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291 | *
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292 | * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
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293 | * 8 MHz) but the real value may vary depending on the variations
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294 | * in voltage and temperature.
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295 | *
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296 | * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
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297 | * 8 MHz or 25 MHz, depedning on the product used), user has to ensure
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298 | * that HSE_VALUE is same as the real frequency of the crystal used.
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299 | * Otherwise, this function may have wrong result.
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300 | *
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301 | * - The result of this function could be not correct when using fractional
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302 | * value for HSE crystal.
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303 | * @param None
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304 | * @retval None
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305 | */
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306 | void SystemCoreClockUpdate (void) |
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307 | { |
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308 | uint32_t tmp = 0, pllmull = 0, pllsource = 0; |
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309 | |||
310 | #ifdef STM32F10X_CL
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311 | uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; |
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312 | #endif /* STM32F10X_CL */ |
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313 | |||
314 | #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
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315 | uint32_t prediv1factor = 0;
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316 | #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */ |
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317 | |||
318 | /* Get SYSCLK source -------------------------------------------------------*/
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319 | tmp = RCC->CFGR & RCC_CFGR_SWS; |
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320 | |||
321 | switch (tmp)
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322 | { |
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323 | case 0x00: /* HSI used as system clock */ |
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324 | SystemCoreClock = HSI_VALUE; |
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325 | break;
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326 | case 0x04: /* HSE used as system clock */ |
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327 | SystemCoreClock = HSE_VALUE; |
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328 | break;
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329 | case 0x08: /* PLL used as system clock */ |
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330 | |||
331 | /* Get PLL clock source and multiplication factor ----------------------*/
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332 | pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; |
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333 | pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; |
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334 | |||
335 | #ifndef STM32F10X_CL
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336 | pllmull = ( pllmull >> 18) + 2; |
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337 | |||
338 | if (pllsource == 0x00) |
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339 | { |
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340 | /* HSI oscillator clock divided by 2 selected as PLL clock entry */
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341 | SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
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342 | } |
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343 | else
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344 | { |
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345 | #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
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346 | prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
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347 | /* HSE oscillator clock selected as PREDIV1 clock entry */
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348 | SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; |
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349 | #else
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350 | /* HSE selected as PLL clock entry */
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351 | if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
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352 | {/* HSE oscillator clock divided by 2 */
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353 | SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
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354 | } |
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355 | else
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356 | { |
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357 | SystemCoreClock = HSE_VALUE * pllmull; |
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358 | } |
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359 | #endif
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360 | } |
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361 | #else
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362 | pllmull = pllmull >> 18;
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363 | |||
364 | if (pllmull != 0x0D) |
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365 | { |
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366 | pllmull += 2;
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367 | } |
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368 | else
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369 | { /* PLL multiplication factor = PLL input clock * 6.5 */
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370 | pllmull = 13 / 2; |
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371 | } |
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372 | |||
373 | if (pllsource == 0x00) |
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374 | { |
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375 | /* HSI oscillator clock divided by 2 selected as PLL clock entry */
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376 | SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
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377 | } |
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378 | else
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379 | {/* PREDIV1 selected as PLL clock entry */
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380 | |||
381 | /* Get PREDIV1 clock source and division factor */
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382 | prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; |
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383 | prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
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384 | |||
385 | if (prediv1source == 0) |
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386 | { |
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387 | /* HSE oscillator clock selected as PREDIV1 clock entry */
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388 | SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; |
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389 | } |
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390 | else
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391 | {/* PLL2 clock selected as PREDIV1 clock entry */
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392 | |||
393 | /* Get PREDIV2 division factor and PLL2 multiplication factor */
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394 | prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1; |
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395 | pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; |
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396 | SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; |
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397 | } |
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398 | } |
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399 | #endif /* STM32F10X_CL */ |
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400 | break;
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401 | |||
402 | default:
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403 | SystemCoreClock = HSI_VALUE; |
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404 | break;
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405 | } |
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406 | |||
407 | /* Compute HCLK clock frequency ----------------*/
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408 | /* Get HCLK prescaler */
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409 | tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
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410 | /* HCLK clock frequency */
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411 | SystemCoreClock >>= tmp; |
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412 | } |
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413 | |||
414 | /**
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415 | * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
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416 | * @param None
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417 | * @retval None
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418 | */
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419 | static void SetSysClock(void) |
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420 | { |
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421 | #ifdef SYSCLK_FREQ_HSE
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422 | SetSysClockToHSE(); |
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423 | #elif defined SYSCLK_FREQ_24MHz
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424 | SetSysClockTo24(); |
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425 | #elif defined SYSCLK_FREQ_36MHz
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426 | SetSysClockTo36(); |
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427 | #elif defined SYSCLK_FREQ_48MHz
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428 | SetSysClockTo48(); |
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429 | #elif defined SYSCLK_FREQ_56MHz
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430 | SetSysClockTo56(); |
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431 | #elif defined SYSCLK_FREQ_72MHz
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432 | SetSysClockTo72(); |
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433 | #endif
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434 | |||
435 | /* If none of the define above is enabled, the HSI is used as System clock
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436 | source (default after reset) */
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437 | } |
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438 | |||
439 | /**
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440 | * @brief Setup the external memory controller. Called in startup_stm32f10x.s
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441 | * before jump to __main
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442 | * @param None
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443 | * @retval None
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444 | */
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445 | #ifdef DATA_IN_ExtSRAM
|
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446 | /**
|
||
447 | * @brief Setup the external memory controller.
|
||
448 | * Called in startup_stm32f10x_xx.s/.c before jump to main.
|
||
449 | * This function configures the external SRAM mounted on STM3210E-EVAL
|
||
450 | * board (STM32 High density devices). This SRAM will be used as program
|
||
451 | * data memory (including heap and stack).
|
||
452 | * @param None
|
||
453 | * @retval None
|
||
454 | */
|
||
455 | void SystemInit_ExtMemCtl(void) |
||
456 | { |
||
457 | /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
|
||
458 | required, then adjust the Register Addresses */
|
||
459 | |||
460 | /* Enable FSMC clock */
|
||
461 | RCC->AHBENR = 0x00000114;
|
||
462 | |||
463 | /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
|
||
464 | RCC->APB2ENR = 0x000001E0;
|
||
465 | |||
466 | /* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
|
||
467 | /*---------------- SRAM Address lines configuration -------------------------*/
|
||
468 | /*---------------- NOE and NWE configuration --------------------------------*/
|
||
469 | /*---------------- NE3 configuration ----------------------------------------*/
|
||
470 | /*---------------- NBL0, NBL1 configuration ---------------------------------*/
|
||
471 | |||
472 | GPIOD->CRL = 0x44BB44BB;
|
||
473 | GPIOD->CRH = 0xBBBBBBBB;
|
||
474 | |||
475 | GPIOE->CRL = 0xB44444BB;
|
||
476 | GPIOE->CRH = 0xBBBBBBBB;
|
||
477 | |||
478 | GPIOF->CRL = 0x44BBBBBB;
|
||
479 | GPIOF->CRH = 0xBBBB4444;
|
||
480 | |||
481 | GPIOG->CRL = 0x44BBBBBB;
|
||
482 | GPIOG->CRH = 0x44444B44;
|
||
483 | |||
484 | /*---------------- FSMC Configuration ---------------------------------------*/
|
||
485 | /*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/
|
||
486 | |||
487 | FSMC_Bank1->BTCR[4] = 0x00001011; |
||
488 | FSMC_Bank1->BTCR[5] = 0x00000200; |
||
489 | } |
||
490 | #endif /* DATA_IN_ExtSRAM */ |
||
491 | |||
492 | #ifdef SYSCLK_FREQ_HSE
|
||
493 | /**
|
||
494 | * @brief Selects HSE as System clock source and configure HCLK, PCLK2
|
||
495 | * and PCLK1 prescalers.
|
||
496 | * @note This function should be used only after reset.
|
||
497 | * @param None
|
||
498 | * @retval None
|
||
499 | */
|
||
500 | static void SetSysClockToHSE(void) |
||
501 | { |
||
502 | __IO uint32_t StartUpCounter = 0, HSEStatus = 0; |
||
503 | |||
504 | /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
|
||
505 | /* Enable HSE */
|
||
506 | RCC->CR |= ((uint32_t)RCC_CR_HSEON); |
||
507 | |||
508 | /* Wait till HSE is ready and if Time out is reached exit */
|
||
509 | do
|
||
510 | { |
||
511 | HSEStatus = RCC->CR & RCC_CR_HSERDY; |
||
512 | StartUpCounter++; |
||
513 | } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); |
||
514 | |||
515 | if ((RCC->CR & RCC_CR_HSERDY) != RESET)
|
||
516 | { |
||
517 | HSEStatus = (uint32_t)0x01;
|
||
518 | } |
||
519 | else
|
||
520 | { |
||
521 | HSEStatus = (uint32_t)0x00;
|
||
522 | } |
||
523 | |||
524 | if (HSEStatus == (uint32_t)0x01) |
||
525 | { |
||
526 | |||
527 | #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
|
||
528 | /* Enable Prefetch Buffer */
|
||
529 | FLASH->ACR |= FLASH_ACR_PRFTBE; |
||
530 | |||
531 | /* Flash 0 wait state */
|
||
532 | FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); |
||
533 | |||
534 | #ifndef STM32F10X_CL
|
||
535 | FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; |
||
536 | #else
|
||
537 | if (HSE_VALUE <= 24000000) |
||
538 | { |
||
539 | FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; |
||
540 | } |
||
541 | else
|
||
542 | { |
||
543 | FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; |
||
544 | } |
||
545 | #endif /* STM32F10X_CL */ |
||
546 | #endif
|
||
547 | |||
548 | /* HCLK = SYSCLK */
|
||
549 | RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; |
||
550 | |||
551 | /* PCLK2 = HCLK */
|
||
552 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; |
||
553 | |||
554 | /* PCLK1 = HCLK */
|
||
555 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; |
||
556 | |||
557 | /* Select HSE as system clock source */
|
||
558 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); |
||
559 | RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE; |
||
560 | |||
561 | /* Wait till HSE is used as system clock source */
|
||
562 | while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04) |
||
563 | { |
||
564 | } |
||
565 | } |
||
566 | else
|
||
567 | { /* If HSE fails to start-up, the application will have wrong clock
|
||
568 | configuration. User can add here some code to deal with this error */
|
||
569 | } |
||
570 | } |
||
571 | #elif defined SYSCLK_FREQ_24MHz
|
||
572 | /**
|
||
573 | * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2
|
||
574 | * and PCLK1 prescalers.
|
||
575 | * @note This function should be used only after reset.
|
||
576 | * @param None
|
||
577 | * @retval None
|
||
578 | */
|
||
579 | static void SetSysClockTo24(void) |
||
580 | { |
||
581 | __IO uint32_t StartUpCounter = 0, HSEStatus = 0; |
||
582 | |||
583 | /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
|
||
584 | /* Enable HSE */
|
||
585 | RCC->CR |= ((uint32_t)RCC_CR_HSEON); |
||
586 | |||
587 | /* Wait till HSE is ready and if Time out is reached exit */
|
||
588 | do
|
||
589 | { |
||
590 | HSEStatus = RCC->CR & RCC_CR_HSERDY; |
||
591 | StartUpCounter++; |
||
592 | } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); |
||
593 | |||
594 | if ((RCC->CR & RCC_CR_HSERDY) != RESET)
|
||
595 | { |
||
596 | HSEStatus = (uint32_t)0x01;
|
||
597 | } |
||
598 | else
|
||
599 | { |
||
600 | HSEStatus = (uint32_t)0x00;
|
||
601 | } |
||
602 | |||
603 | if (HSEStatus == (uint32_t)0x01) |
||
604 | { |
||
605 | #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
|
||
606 | /* Enable Prefetch Buffer */
|
||
607 | FLASH->ACR |= FLASH_ACR_PRFTBE; |
||
608 | |||
609 | /* Flash 0 wait state */
|
||
610 | FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); |
||
611 | FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; |
||
612 | #endif
|
||
613 | |||
614 | /* HCLK = SYSCLK */
|
||
615 | RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; |
||
616 | |||
617 | /* PCLK2 = HCLK */
|
||
618 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; |
||
619 | |||
620 | /* PCLK1 = HCLK */
|
||
621 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; |
||
622 | |||
623 | #ifdef STM32F10X_CL
|
||
624 | /* Configure PLLs ------------------------------------------------------*/
|
||
625 | /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
|
||
626 | RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); |
||
627 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | |
||
628 | RCC_CFGR_PLLMULL6); |
||
629 | |||
630 | /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
|
||
631 | /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
|
||
632 | RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | |
||
633 | RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); |
||
634 | RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | |
||
635 | RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); |
||
636 | |||
637 | /* Enable PLL2 */
|
||
638 | RCC->CR |= RCC_CR_PLL2ON; |
||
639 | /* Wait till PLL2 is ready */
|
||
640 | while((RCC->CR & RCC_CR_PLL2RDY) == 0) |
||
641 | { |
||
642 | } |
||
643 | #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
|
||
644 | /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
|
||
645 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); |
||
646 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6); |
||
647 | #else
|
||
648 | /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
|
||
649 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); |
||
650 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6); |
||
651 | #endif /* STM32F10X_CL */ |
||
652 | |||
653 | /* Enable PLL */
|
||
654 | RCC->CR |= RCC_CR_PLLON; |
||
655 | |||
656 | /* Wait till PLL is ready */
|
||
657 | while((RCC->CR & RCC_CR_PLLRDY) == 0) |
||
658 | { |
||
659 | } |
||
660 | |||
661 | /* Select PLL as system clock source */
|
||
662 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); |
||
663 | RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; |
||
664 | |||
665 | /* Wait till PLL is used as system clock source */
|
||
666 | while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) |
||
667 | { |
||
668 | } |
||
669 | } |
||
670 | else
|
||
671 | { /* If HSE fails to start-up, the application will have wrong clock
|
||
672 | configuration. User can add here some code to deal with this error */
|
||
673 | } |
||
674 | } |
||
675 | #elif defined SYSCLK_FREQ_36MHz
|
||
676 | /**
|
||
677 | * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2
|
||
678 | * and PCLK1 prescalers.
|
||
679 | * @note This function should be used only after reset.
|
||
680 | * @param None
|
||
681 | * @retval None
|
||
682 | */
|
||
683 | static void SetSysClockTo36(void) |
||
684 | { |
||
685 | __IO uint32_t StartUpCounter = 0, HSEStatus = 0; |
||
686 | |||
687 | /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
|
||
688 | /* Enable HSE */
|
||
689 | RCC->CR |= ((uint32_t)RCC_CR_HSEON); |
||
690 | |||
691 | /* Wait till HSE is ready and if Time out is reached exit */
|
||
692 | do
|
||
693 | { |
||
694 | HSEStatus = RCC->CR & RCC_CR_HSERDY; |
||
695 | StartUpCounter++; |
||
696 | } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); |
||
697 | |||
698 | if ((RCC->CR & RCC_CR_HSERDY) != RESET)
|
||
699 | { |
||
700 | HSEStatus = (uint32_t)0x01;
|
||
701 | } |
||
702 | else
|
||
703 | { |
||
704 | HSEStatus = (uint32_t)0x00;
|
||
705 | } |
||
706 | |||
707 | if (HSEStatus == (uint32_t)0x01) |
||
708 | { |
||
709 | /* Enable Prefetch Buffer */
|
||
710 | FLASH->ACR |= FLASH_ACR_PRFTBE; |
||
711 | |||
712 | /* Flash 1 wait state */
|
||
713 | FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); |
||
714 | FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; |
||
715 | |||
716 | /* HCLK = SYSCLK */
|
||
717 | RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; |
||
718 | |||
719 | /* PCLK2 = HCLK */
|
||
720 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; |
||
721 | |||
722 | /* PCLK1 = HCLK */
|
||
723 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; |
||
724 | |||
725 | #ifdef STM32F10X_CL
|
||
726 | /* Configure PLLs ------------------------------------------------------*/
|
||
727 | |||
728 | /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
|
||
729 | RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); |
||
730 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | |
||
731 | RCC_CFGR_PLLMULL9); |
||
732 | |||
733 | /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
|
||
734 | /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
|
||
735 | |||
736 | RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | |
||
737 | RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); |
||
738 | RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | |
||
739 | RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); |
||
740 | |||
741 | /* Enable PLL2 */
|
||
742 | RCC->CR |= RCC_CR_PLL2ON; |
||
743 | /* Wait till PLL2 is ready */
|
||
744 | while((RCC->CR & RCC_CR_PLL2RDY) == 0) |
||
745 | { |
||
746 | } |
||
747 | |||
748 | #else
|
||
749 | /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
|
||
750 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); |
||
751 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9); |
||
752 | #endif /* STM32F10X_CL */ |
||
753 | |||
754 | /* Enable PLL */
|
||
755 | RCC->CR |= RCC_CR_PLLON; |
||
756 | |||
757 | /* Wait till PLL is ready */
|
||
758 | while((RCC->CR & RCC_CR_PLLRDY) == 0) |
||
759 | { |
||
760 | } |
||
761 | |||
762 | /* Select PLL as system clock source */
|
||
763 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); |
||
764 | RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; |
||
765 | |||
766 | /* Wait till PLL is used as system clock source */
|
||
767 | while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) |
||
768 | { |
||
769 | } |
||
770 | } |
||
771 | else
|
||
772 | { /* If HSE fails to start-up, the application will have wrong clock
|
||
773 | configuration. User can add here some code to deal with this error */
|
||
774 | } |
||
775 | } |
||
776 | #elif defined SYSCLK_FREQ_48MHz
|
||
777 | /**
|
||
778 | * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2
|
||
779 | * and PCLK1 prescalers.
|
||
780 | * @note This function should be used only after reset.
|
||
781 | * @param None
|
||
782 | * @retval None
|
||
783 | */
|
||
784 | static void SetSysClockTo48(void) |
||
785 | { |
||
786 | __IO uint32_t StartUpCounter = 0, HSEStatus = 0; |
||
787 | |||
788 | /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
|
||
789 | /* Enable HSE */
|
||
790 | RCC->CR |= ((uint32_t)RCC_CR_HSEON); |
||
791 | |||
792 | /* Wait till HSE is ready and if Time out is reached exit */
|
||
793 | do
|
||
794 | { |
||
795 | HSEStatus = RCC->CR & RCC_CR_HSERDY; |
||
796 | StartUpCounter++; |
||
797 | } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); |
||
798 | |||
799 | if ((RCC->CR & RCC_CR_HSERDY) != RESET)
|
||
800 | { |
||
801 | HSEStatus = (uint32_t)0x01;
|
||
802 | } |
||
803 | else
|
||
804 | { |
||
805 | HSEStatus = (uint32_t)0x00;
|
||
806 | } |
||
807 | |||
808 | if (HSEStatus == (uint32_t)0x01) |
||
809 | { |
||
810 | /* Enable Prefetch Buffer */
|
||
811 | FLASH->ACR |= FLASH_ACR_PRFTBE; |
||
812 | |||
813 | /* Flash 1 wait state */
|
||
814 | FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); |
||
815 | FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; |
||
816 | |||
817 | /* HCLK = SYSCLK */
|
||
818 | RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; |
||
819 | |||
820 | /* PCLK2 = HCLK */
|
||
821 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; |
||
822 | |||
823 | /* PCLK1 = HCLK */
|
||
824 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; |
||
825 | |||
826 | #ifdef STM32F10X_CL
|
||
827 | /* Configure PLLs ------------------------------------------------------*/
|
||
828 | /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
|
||
829 | /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
|
||
830 | |||
831 | RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | |
||
832 | RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); |
||
833 | RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | |
||
834 | RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); |
||
835 | |||
836 | /* Enable PLL2 */
|
||
837 | RCC->CR |= RCC_CR_PLL2ON; |
||
838 | /* Wait till PLL2 is ready */
|
||
839 | while((RCC->CR & RCC_CR_PLL2RDY) == 0) |
||
840 | { |
||
841 | } |
||
842 | |||
843 | |||
844 | /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
|
||
845 | RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); |
||
846 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | |
||
847 | RCC_CFGR_PLLMULL6); |
||
848 | #else
|
||
849 | /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
|
||
850 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); |
||
851 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6); |
||
852 | #endif /* STM32F10X_CL */ |
||
853 | |||
854 | /* Enable PLL */
|
||
855 | RCC->CR |= RCC_CR_PLLON; |
||
856 | |||
857 | /* Wait till PLL is ready */
|
||
858 | while((RCC->CR & RCC_CR_PLLRDY) == 0) |
||
859 | { |
||
860 | } |
||
861 | |||
862 | /* Select PLL as system clock source */
|
||
863 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); |
||
864 | RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; |
||
865 | |||
866 | /* Wait till PLL is used as system clock source */
|
||
867 | while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) |
||
868 | { |
||
869 | } |
||
870 | } |
||
871 | else
|
||
872 | { /* If HSE fails to start-up, the application will have wrong clock
|
||
873 | configuration. User can add here some code to deal with this error */
|
||
874 | } |
||
875 | } |
||
876 | |||
877 | #elif defined SYSCLK_FREQ_56MHz
|
||
878 | /**
|
||
879 | * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2
|
||
880 | * and PCLK1 prescalers.
|
||
881 | * @note This function should be used only after reset.
|
||
882 | * @param None
|
||
883 | * @retval None
|
||
884 | */
|
||
885 | static void SetSysClockTo56(void) |
||
886 | { |
||
887 | __IO uint32_t StartUpCounter = 0, HSEStatus = 0; |
||
888 | |||
889 | /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
|
||
890 | /* Enable HSE */
|
||
891 | RCC->CR |= ((uint32_t)RCC_CR_HSEON); |
||
892 | |||
893 | /* Wait till HSE is ready and if Time out is reached exit */
|
||
894 | do
|
||
895 | { |
||
896 | HSEStatus = RCC->CR & RCC_CR_HSERDY; |
||
897 | StartUpCounter++; |
||
898 | } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); |
||
899 | |||
900 | if ((RCC->CR & RCC_CR_HSERDY) != RESET)
|
||
901 | { |
||
902 | HSEStatus = (uint32_t)0x01;
|
||
903 | } |
||
904 | else
|
||
905 | { |
||
906 | HSEStatus = (uint32_t)0x00;
|
||
907 | } |
||
908 | |||
909 | if (HSEStatus == (uint32_t)0x01) |
||
910 | { |
||
911 | /* Enable Prefetch Buffer */
|
||
912 | FLASH->ACR |= FLASH_ACR_PRFTBE; |
||
913 | |||
914 | /* Flash 2 wait state */
|
||
915 | FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); |
||
916 | FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; |
||
917 | |||
918 | /* HCLK = SYSCLK */
|
||
919 | RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; |
||
920 | |||
921 | /* PCLK2 = HCLK */
|
||
922 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; |
||
923 | |||
924 | /* PCLK1 = HCLK */
|
||
925 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; |
||
926 | |||
927 | #ifdef STM32F10X_CL
|
||
928 | /* Configure PLLs ------------------------------------------------------*/
|
||
929 | /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
|
||
930 | /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
|
||
931 | |||
932 | RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | |
||
933 | RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); |
||
934 | RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | |
||
935 | RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); |
||
936 | |||
937 | /* Enable PLL2 */
|
||
938 | RCC->CR |= RCC_CR_PLL2ON; |
||
939 | /* Wait till PLL2 is ready */
|
||
940 | while((RCC->CR & RCC_CR_PLL2RDY) == 0) |
||
941 | { |
||
942 | } |
||
943 | |||
944 | |||
945 | /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
|
||
946 | RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); |
||
947 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | |
||
948 | RCC_CFGR_PLLMULL7); |
||
949 | #else
|
||
950 | /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
|
||
951 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); |
||
952 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7); |
||
953 | |||
954 | #endif /* STM32F10X_CL */ |
||
955 | |||
956 | /* Enable PLL */
|
||
957 | RCC->CR |= RCC_CR_PLLON; |
||
958 | |||
959 | /* Wait till PLL is ready */
|
||
960 | while((RCC->CR & RCC_CR_PLLRDY) == 0) |
||
961 | { |
||
962 | } |
||
963 | |||
964 | /* Select PLL as system clock source */
|
||
965 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); |
||
966 | RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; |
||
967 | |||
968 | /* Wait till PLL is used as system clock source */
|
||
969 | while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) |
||
970 | { |
||
971 | } |
||
972 | } |
||
973 | else
|
||
974 | { /* If HSE fails to start-up, the application will have wrong clock
|
||
975 | configuration. User can add here some code to deal with this error */
|
||
976 | } |
||
977 | } |
||
978 | |||
979 | #elif defined SYSCLK_FREQ_72MHz
|
||
980 | /**
|
||
981 | * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2
|
||
982 | * and PCLK1 prescalers.
|
||
983 | * @note This function should be used only after reset.
|
||
984 | * @param None
|
||
985 | * @retval None
|
||
986 | */
|
||
987 | static void SetSysClockTo72(void) |
||
988 | { |
||
989 | __IO uint32_t StartUpCounter = 0, HSEStatus = 0; |
||
990 | |||
991 | /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
|
||
992 | /* Enable HSE */
|
||
993 | RCC->CR |= ((uint32_t)RCC_CR_HSEON); |
||
994 | |||
995 | /* Wait till HSE is ready and if Time out is reached exit */
|
||
996 | do
|
||
997 | { |
||
998 | HSEStatus = RCC->CR & RCC_CR_HSERDY; |
||
999 | StartUpCounter++; |
||
1000 | } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); |
||
1001 | |||
1002 | if ((RCC->CR & RCC_CR_HSERDY) != RESET)
|
||
1003 | { |
||
1004 | HSEStatus = (uint32_t)0x01;
|
||
1005 | } |
||
1006 | else
|
||
1007 | { |
||
1008 | HSEStatus = (uint32_t)0x00;
|
||
1009 | } |
||
1010 | |||
1011 | if (HSEStatus == (uint32_t)0x01) |
||
1012 | { |
||
1013 | /* Enable Prefetch Buffer */
|
||
1014 | FLASH->ACR |= FLASH_ACR_PRFTBE; |
||
1015 | |||
1016 | /* Flash 2 wait state */
|
||
1017 | FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); |
||
1018 | FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; |
||
1019 | |||
1020 | |||
1021 | /* HCLK = SYSCLK */
|
||
1022 | RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; |
||
1023 | |||
1024 | /* PCLK2 = HCLK */
|
||
1025 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; |
||
1026 | |||
1027 | /* PCLK1 = HCLK */
|
||
1028 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; |
||
1029 | |||
1030 | #ifdef STM32F10X_CL
|
||
1031 | /* Configure PLLs ------------------------------------------------------*/
|
||
1032 | /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
|
||
1033 | /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
|
||
1034 | |||
1035 | RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | |
||
1036 | RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); |
||
1037 | RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | |
||
1038 | RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); |
||
1039 | |||
1040 | /* Enable PLL2 */
|
||
1041 | RCC->CR |= RCC_CR_PLL2ON; |
||
1042 | /* Wait till PLL2 is ready */
|
||
1043 | while((RCC->CR & RCC_CR_PLL2RDY) == 0) |
||
1044 | { |
||
1045 | } |
||
1046 | |||
1047 | |||
1048 | /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
|
||
1049 | RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); |
||
1050 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | |
||
1051 | RCC_CFGR_PLLMULL9); |
||
1052 | #else
|
||
1053 | /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
|
||
1054 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | |
||
1055 | RCC_CFGR_PLLMULL)); |
||
1056 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9); |
||
1057 | #endif /* STM32F10X_CL */ |
||
1058 | |||
1059 | /* Enable PLL */
|
||
1060 | RCC->CR |= RCC_CR_PLLON; |
||
1061 | |||
1062 | /* Wait till PLL is ready */
|
||
1063 | while((RCC->CR & RCC_CR_PLLRDY) == 0) |
||
1064 | { |
||
1065 | } |
||
1066 | |||
1067 | /* Select PLL as system clock source */
|
||
1068 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); |
||
1069 | RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; |
||
1070 | |||
1071 | /* Wait till PLL is used as system clock source */
|
||
1072 | while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) |
||
1073 | { |
||
1074 | } |
||
1075 | } |
||
1076 | else
|
||
1077 | { /* If HSE fails to start-up, the application will have wrong clock
|
||
1078 | configuration. User can add here some code to deal with this error */
|
||
1079 | } |
||
1080 | } |
||
1081 | #endif
|
||
1082 | |||
1083 | /**
|
||
1084 | * @}
|
||
1085 | */
|
||
1086 | |||
1087 | /**
|
||
1088 | * @}
|
||
1089 | */
|
||
1090 | |||
1091 | /**
|
||
1092 | * @}
|
||
1093 | */
|
||
1094 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|