amiro-blt / Target / Demo / ARMCM3_STM32F103_DiWheelDrive_GCC / Boot / lib / STM32F10x_StdPeriph_Driver / src / stm32f10x_fsmc.c @ 69661903
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1 | 69661903 | Thomas Schöpping | /**
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2 | ******************************************************************************
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3 | * @file stm32f10x_fsmc.c
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4 | * @author MCD Application Team
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5 | * @version V3.5.0
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6 | * @date 11-March-2011
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7 | * @brief This file provides all the FSMC firmware functions.
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8 | ******************************************************************************
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9 | * @attention
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10 | *
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11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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17 | *
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18 | * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
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19 | ******************************************************************************
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20 | */
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21 | |||
22 | /* Includes ------------------------------------------------------------------*/
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23 | #include "stm32f10x_fsmc.h" |
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24 | #include "stm32f10x_rcc.h" |
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25 | |||
26 | /** @addtogroup STM32F10x_StdPeriph_Driver
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27 | * @{
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28 | */
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29 | |||
30 | /** @defgroup FSMC
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31 | * @brief FSMC driver modules
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32 | * @{
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33 | */
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34 | |||
35 | /** @defgroup FSMC_Private_TypesDefinitions
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36 | * @{
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37 | */
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38 | /**
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39 | * @}
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40 | */
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41 | |||
42 | /** @defgroup FSMC_Private_Defines
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43 | * @{
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44 | */
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45 | |||
46 | /* --------------------- FSMC registers bit mask ---------------------------- */
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47 | |||
48 | /* FSMC BCRx Mask */
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49 | #define BCR_MBKEN_Set ((uint32_t)0x00000001) |
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50 | #define BCR_MBKEN_Reset ((uint32_t)0x000FFFFE) |
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51 | #define BCR_FACCEN_Set ((uint32_t)0x00000040) |
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52 | |||
53 | /* FSMC PCRx Mask */
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54 | #define PCR_PBKEN_Set ((uint32_t)0x00000004) |
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55 | #define PCR_PBKEN_Reset ((uint32_t)0x000FFFFB) |
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56 | #define PCR_ECCEN_Set ((uint32_t)0x00000040) |
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57 | #define PCR_ECCEN_Reset ((uint32_t)0x000FFFBF) |
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58 | #define PCR_MemoryType_NAND ((uint32_t)0x00000008) |
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59 | /**
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60 | * @}
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61 | */
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62 | |||
63 | /** @defgroup FSMC_Private_Macros
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64 | * @{
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65 | */
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66 | |||
67 | /**
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68 | * @}
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69 | */
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70 | |||
71 | /** @defgroup FSMC_Private_Variables
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72 | * @{
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73 | */
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74 | |||
75 | /**
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76 | * @}
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77 | */
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78 | |||
79 | /** @defgroup FSMC_Private_FunctionPrototypes
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80 | * @{
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81 | */
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82 | |||
83 | /**
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84 | * @}
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85 | */
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86 | |||
87 | /** @defgroup FSMC_Private_Functions
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88 | * @{
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89 | */
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90 | |||
91 | /**
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92 | * @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default
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93 | * reset values.
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94 | * @param FSMC_Bank: specifies the FSMC Bank to be used
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95 | * This parameter can be one of the following values:
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96 | * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
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97 | * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
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98 | * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
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99 | * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
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100 | * @retval None
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101 | */
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102 | void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)
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103 | { |
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104 | /* Check the parameter */
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105 | assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); |
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106 | |||
107 | /* FSMC_Bank1_NORSRAM1 */
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108 | if(FSMC_Bank == FSMC_Bank1_NORSRAM1)
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109 | { |
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110 | FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;
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111 | } |
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112 | /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */
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113 | else
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114 | { |
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115 | FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2;
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116 | } |
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117 | FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF; |
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118 | FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;
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119 | } |
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120 | |||
121 | /**
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122 | * @brief Deinitializes the FSMC NAND Banks registers to their default reset values.
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123 | * @param FSMC_Bank: specifies the FSMC Bank to be used
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124 | * This parameter can be one of the following values:
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125 | * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
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126 | * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
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127 | * @retval None
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128 | */
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129 | void FSMC_NANDDeInit(uint32_t FSMC_Bank)
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130 | { |
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131 | /* Check the parameter */
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132 | assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); |
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133 | |||
134 | if(FSMC_Bank == FSMC_Bank2_NAND)
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135 | { |
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136 | /* Set the FSMC_Bank2 registers to their reset values */
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137 | FSMC_Bank2->PCR2 = 0x00000018;
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138 | FSMC_Bank2->SR2 = 0x00000040;
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139 | FSMC_Bank2->PMEM2 = 0xFCFCFCFC;
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140 | FSMC_Bank2->PATT2 = 0xFCFCFCFC;
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141 | } |
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142 | /* FSMC_Bank3_NAND */
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143 | else
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144 | { |
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145 | /* Set the FSMC_Bank3 registers to their reset values */
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146 | FSMC_Bank3->PCR3 = 0x00000018;
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147 | FSMC_Bank3->SR3 = 0x00000040;
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148 | FSMC_Bank3->PMEM3 = 0xFCFCFCFC;
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149 | FSMC_Bank3->PATT3 = 0xFCFCFCFC;
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150 | } |
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151 | } |
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152 | |||
153 | /**
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154 | * @brief Deinitializes the FSMC PCCARD Bank registers to their default reset values.
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155 | * @param None
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156 | * @retval None
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157 | */
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158 | void FSMC_PCCARDDeInit(void) |
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159 | { |
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160 | /* Set the FSMC_Bank4 registers to their reset values */
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161 | FSMC_Bank4->PCR4 = 0x00000018;
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162 | FSMC_Bank4->SR4 = 0x00000000;
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163 | FSMC_Bank4->PMEM4 = 0xFCFCFCFC;
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164 | FSMC_Bank4->PATT4 = 0xFCFCFCFC;
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165 | FSMC_Bank4->PIO4 = 0xFCFCFCFC;
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166 | } |
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167 | |||
168 | /**
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169 | * @brief Initializes the FSMC NOR/SRAM Banks according to the specified
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170 | * parameters in the FSMC_NORSRAMInitStruct.
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171 | * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef
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172 | * structure that contains the configuration information for
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173 | * the FSMC NOR/SRAM specified Banks.
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174 | * @retval None
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175 | */
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176 | void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
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177 | { |
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178 | /* Check the parameters */
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179 | assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank)); |
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180 | assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux)); |
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181 | assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType)); |
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182 | assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth)); |
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183 | assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode)); |
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184 | assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait)); |
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185 | assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity)); |
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186 | assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode)); |
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187 | assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive)); |
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188 | assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation)); |
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189 | assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal)); |
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190 | assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode)); |
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191 | assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst)); |
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192 | assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime)); |
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193 | assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime)); |
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194 | assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime)); |
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195 | assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration)); |
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196 | assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision)); |
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197 | assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency)); |
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198 | assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode)); |
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199 | |||
200 | /* Bank1 NOR/SRAM control register configuration */
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201 | FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = |
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202 | (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux | |
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203 | FSMC_NORSRAMInitStruct->FSMC_MemoryType | |
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204 | FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth | |
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205 | FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode | |
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206 | FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait | |
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207 | FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity | |
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208 | FSMC_NORSRAMInitStruct->FSMC_WrapMode | |
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209 | FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive | |
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210 | FSMC_NORSRAMInitStruct->FSMC_WriteOperation | |
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211 | FSMC_NORSRAMInitStruct->FSMC_WaitSignal | |
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212 | FSMC_NORSRAMInitStruct->FSMC_ExtendedMode | |
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213 | FSMC_NORSRAMInitStruct->FSMC_WriteBurst; |
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214 | |||
215 | if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
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216 | { |
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217 | FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set; |
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218 | } |
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219 | |||
220 | /* Bank1 NOR/SRAM timing register configuration */
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221 | FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] =
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222 | (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime | |
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223 | (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
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224 | (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
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225 | (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
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226 | (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
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227 | (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
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228 | FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode; |
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229 | |||
230 | |||
231 | /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
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232 | if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
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233 | { |
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234 | assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime)); |
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235 | assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime)); |
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236 | assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime)); |
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237 | assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision)); |
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238 | assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency)); |
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239 | assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode)); |
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240 | FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = |
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241 | (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime | |
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242 | (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
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243 | (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
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244 | (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
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245 | (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
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246 | FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode; |
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247 | } |
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248 | else
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249 | { |
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250 | FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
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251 | } |
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252 | } |
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253 | |||
254 | /**
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255 | * @brief Initializes the FSMC NAND Banks according to the specified
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256 | * parameters in the FSMC_NANDInitStruct.
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257 | * @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef
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258 | * structure that contains the configuration information for the FSMC
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259 | * NAND specified Banks.
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260 | * @retval None
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261 | */
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262 | void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
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263 | { |
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264 | uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; |
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265 | |||
266 | /* Check the parameters */
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267 | assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank)); |
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268 | assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature)); |
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269 | assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth)); |
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270 | assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC)); |
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271 | assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize)); |
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272 | assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime)); |
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273 | assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime)); |
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274 | assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); |
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275 | assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); |
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276 | assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); |
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277 | assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); |
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278 | assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); |
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279 | assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); |
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280 | assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); |
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281 | assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); |
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282 | |||
283 | /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */
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284 | tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature | |
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285 | PCR_MemoryType_NAND | |
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286 | FSMC_NANDInitStruct->FSMC_MemoryDataWidth | |
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287 | FSMC_NANDInitStruct->FSMC_ECC | |
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288 | FSMC_NANDInitStruct->FSMC_ECCPageSize | |
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289 | (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )|
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290 | (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);
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291 | |||
292 | /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */
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293 | tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | |
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294 | (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
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295 | (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
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296 | (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
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297 | |||
298 | /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */
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299 | tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | |
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300 | (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
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301 | (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
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302 | (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
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303 | |||
304 | if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
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305 | { |
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306 | /* FSMC_Bank2_NAND registers configuration */
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307 | FSMC_Bank2->PCR2 = tmppcr; |
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308 | FSMC_Bank2->PMEM2 = tmppmem; |
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309 | FSMC_Bank2->PATT2 = tmppatt; |
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310 | } |
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311 | else
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312 | { |
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313 | /* FSMC_Bank3_NAND registers configuration */
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314 | FSMC_Bank3->PCR3 = tmppcr; |
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315 | FSMC_Bank3->PMEM3 = tmppmem; |
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316 | FSMC_Bank3->PATT3 = tmppatt; |
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317 | } |
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318 | } |
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319 | |||
320 | /**
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321 | * @brief Initializes the FSMC PCCARD Bank according to the specified
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322 | * parameters in the FSMC_PCCARDInitStruct.
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323 | * @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef
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324 | * structure that contains the configuration information for the FSMC
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325 | * PCCARD Bank.
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326 | * @retval None
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327 | */
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328 | void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
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329 | { |
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330 | /* Check the parameters */
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331 | assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature)); |
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332 | assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime)); |
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333 | assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime)); |
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334 | |||
335 | assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); |
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336 | assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); |
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337 | assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); |
||
338 | assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); |
||
339 | |||
340 | assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); |
||
341 | assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); |
||
342 | assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); |
||
343 | assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); |
||
344 | assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime)); |
||
345 | assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime)); |
||
346 | assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime)); |
||
347 | assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime)); |
||
348 | |||
349 | /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */
|
||
350 | FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature | |
||
351 | FSMC_MemoryDataWidth_16b | |
||
352 | (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) |
|
||
353 | (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13);
|
||
354 | |||
355 | /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */
|
||
356 | FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | |
||
357 | (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
|
||
358 | (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
|
||
359 | (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
|
||
360 | |||
361 | /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */
|
||
362 | FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | |
||
363 | (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
|
||
364 | (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
|
||
365 | (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
|
||
366 | |||
367 | /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */
|
||
368 | FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime | |
||
369 | (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
|
||
370 | (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
|
||
371 | (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24);
|
||
372 | } |
||
373 | |||
374 | /**
|
||
375 | * @brief Fills each FSMC_NORSRAMInitStruct member with its default value.
|
||
376 | * @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef
|
||
377 | * structure which will be initialized.
|
||
378 | * @retval None
|
||
379 | */
|
||
380 | void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
|
||
381 | { |
||
382 | /* Reset NOR/SRAM Init structure parameters values */
|
||
383 | FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1; |
||
384 | FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable; |
||
385 | FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM; |
||
386 | FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; |
||
387 | FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; |
||
388 | FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; |
||
389 | FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; |
||
390 | FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable; |
||
391 | FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; |
||
392 | FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable; |
||
393 | FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable; |
||
394 | FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; |
||
395 | FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable; |
||
396 | FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;
|
||
397 | FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;
|
||
398 | FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;
|
||
399 | FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
|
||
400 | FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;
|
||
401 | FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;
|
||
402 | FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; |
||
403 | FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;
|
||
404 | FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;
|
||
405 | FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;
|
||
406 | FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
|
||
407 | FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;
|
||
408 | FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;
|
||
409 | FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; |
||
410 | } |
||
411 | |||
412 | /**
|
||
413 | * @brief Fills each FSMC_NANDInitStruct member with its default value.
|
||
414 | * @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef
|
||
415 | * structure which will be initialized.
|
||
416 | * @retval None
|
||
417 | */
|
||
418 | void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
|
||
419 | { |
||
420 | /* Reset NAND Init structure parameters values */
|
||
421 | FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND; |
||
422 | FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; |
||
423 | FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; |
||
424 | FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable; |
||
425 | FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes; |
||
426 | FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0;
|
||
427 | FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0;
|
||
428 | FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
|
||
429 | FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
|
||
430 | FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
|
||
431 | FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
|
||
432 | FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
|
||
433 | FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
|
||
434 | FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
|
||
435 | FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
|
||
436 | } |
||
437 | |||
438 | /**
|
||
439 | * @brief Fills each FSMC_PCCARDInitStruct member with its default value.
|
||
440 | * @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef
|
||
441 | * structure which will be initialized.
|
||
442 | * @retval None
|
||
443 | */
|
||
444 | void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
|
||
445 | { |
||
446 | /* Reset PCCARD Init structure parameters values */
|
||
447 | FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; |
||
448 | FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0;
|
||
449 | FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0;
|
||
450 | FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
|
||
451 | FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
|
||
452 | FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
|
||
453 | FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
|
||
454 | FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
|
||
455 | FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
|
||
456 | FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
|
||
457 | FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
|
||
458 | FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC;
|
||
459 | FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
|
||
460 | FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
|
||
461 | FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
|
||
462 | } |
||
463 | |||
464 | /**
|
||
465 | * @brief Enables or disables the specified NOR/SRAM Memory Bank.
|
||
466 | * @param FSMC_Bank: specifies the FSMC Bank to be used
|
||
467 | * This parameter can be one of the following values:
|
||
468 | * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
|
||
469 | * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
|
||
470 | * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
|
||
471 | * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
|
||
472 | * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
|
||
473 | * @retval None
|
||
474 | */
|
||
475 | void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)
|
||
476 | { |
||
477 | assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); |
||
478 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
||
479 | |||
480 | if (NewState != DISABLE)
|
||
481 | { |
||
482 | /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */
|
||
483 | FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set; |
||
484 | } |
||
485 | else
|
||
486 | { |
||
487 | /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */
|
||
488 | FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset; |
||
489 | } |
||
490 | } |
||
491 | |||
492 | /**
|
||
493 | * @brief Enables or disables the specified NAND Memory Bank.
|
||
494 | * @param FSMC_Bank: specifies the FSMC Bank to be used
|
||
495 | * This parameter can be one of the following values:
|
||
496 | * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
|
||
497 | * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
|
||
498 | * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
|
||
499 | * @retval None
|
||
500 | */
|
||
501 | void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState)
|
||
502 | { |
||
503 | assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); |
||
504 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
||
505 | |||
506 | if (NewState != DISABLE)
|
||
507 | { |
||
508 | /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */
|
||
509 | if(FSMC_Bank == FSMC_Bank2_NAND)
|
||
510 | { |
||
511 | FSMC_Bank2->PCR2 |= PCR_PBKEN_Set; |
||
512 | } |
||
513 | else
|
||
514 | { |
||
515 | FSMC_Bank3->PCR3 |= PCR_PBKEN_Set; |
||
516 | } |
||
517 | } |
||
518 | else
|
||
519 | { |
||
520 | /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */
|
||
521 | if(FSMC_Bank == FSMC_Bank2_NAND)
|
||
522 | { |
||
523 | FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset; |
||
524 | } |
||
525 | else
|
||
526 | { |
||
527 | FSMC_Bank3->PCR3 &= PCR_PBKEN_Reset; |
||
528 | } |
||
529 | } |
||
530 | } |
||
531 | |||
532 | /**
|
||
533 | * @brief Enables or disables the PCCARD Memory Bank.
|
||
534 | * @param NewState: new state of the PCCARD Memory Bank.
|
||
535 | * This parameter can be: ENABLE or DISABLE.
|
||
536 | * @retval None
|
||
537 | */
|
||
538 | void FSMC_PCCARDCmd(FunctionalState NewState)
|
||
539 | { |
||
540 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
||
541 | |||
542 | if (NewState != DISABLE)
|
||
543 | { |
||
544 | /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */
|
||
545 | FSMC_Bank4->PCR4 |= PCR_PBKEN_Set; |
||
546 | } |
||
547 | else
|
||
548 | { |
||
549 | /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */
|
||
550 | FSMC_Bank4->PCR4 &= PCR_PBKEN_Reset; |
||
551 | } |
||
552 | } |
||
553 | |||
554 | /**
|
||
555 | * @brief Enables or disables the FSMC NAND ECC feature.
|
||
556 | * @param FSMC_Bank: specifies the FSMC Bank to be used
|
||
557 | * This parameter can be one of the following values:
|
||
558 | * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
|
||
559 | * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
|
||
560 | * @param NewState: new state of the FSMC NAND ECC feature.
|
||
561 | * This parameter can be: ENABLE or DISABLE.
|
||
562 | * @retval None
|
||
563 | */
|
||
564 | void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState)
|
||
565 | { |
||
566 | assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); |
||
567 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
||
568 | |||
569 | if (NewState != DISABLE)
|
||
570 | { |
||
571 | /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */
|
||
572 | if(FSMC_Bank == FSMC_Bank2_NAND)
|
||
573 | { |
||
574 | FSMC_Bank2->PCR2 |= PCR_ECCEN_Set; |
||
575 | } |
||
576 | else
|
||
577 | { |
||
578 | FSMC_Bank3->PCR3 |= PCR_ECCEN_Set; |
||
579 | } |
||
580 | } |
||
581 | else
|
||
582 | { |
||
583 | /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */
|
||
584 | if(FSMC_Bank == FSMC_Bank2_NAND)
|
||
585 | { |
||
586 | FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset; |
||
587 | } |
||
588 | else
|
||
589 | { |
||
590 | FSMC_Bank3->PCR3 &= PCR_ECCEN_Reset; |
||
591 | } |
||
592 | } |
||
593 | } |
||
594 | |||
595 | /**
|
||
596 | * @brief Returns the error correction code register value.
|
||
597 | * @param FSMC_Bank: specifies the FSMC Bank to be used
|
||
598 | * This parameter can be one of the following values:
|
||
599 | * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
|
||
600 | * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
|
||
601 | * @retval The Error Correction Code (ECC) value.
|
||
602 | */
|
||
603 | uint32_t FSMC_GetECC(uint32_t FSMC_Bank) |
||
604 | { |
||
605 | uint32_t eccval = 0x00000000;
|
||
606 | |||
607 | if(FSMC_Bank == FSMC_Bank2_NAND)
|
||
608 | { |
||
609 | /* Get the ECCR2 register value */
|
||
610 | eccval = FSMC_Bank2->ECCR2; |
||
611 | } |
||
612 | else
|
||
613 | { |
||
614 | /* Get the ECCR3 register value */
|
||
615 | eccval = FSMC_Bank3->ECCR3; |
||
616 | } |
||
617 | /* Return the error correction code value */
|
||
618 | return(eccval);
|
||
619 | } |
||
620 | |||
621 | /**
|
||
622 | * @brief Enables or disables the specified FSMC interrupts.
|
||
623 | * @param FSMC_Bank: specifies the FSMC Bank to be used
|
||
624 | * This parameter can be one of the following values:
|
||
625 | * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
|
||
626 | * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
|
||
627 | * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
|
||
628 | * @param FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled.
|
||
629 | * This parameter can be any combination of the following values:
|
||
630 | * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
|
||
631 | * @arg FSMC_IT_Level: Level edge detection interrupt.
|
||
632 | * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
|
||
633 | * @param NewState: new state of the specified FSMC interrupts.
|
||
634 | * This parameter can be: ENABLE or DISABLE.
|
||
635 | * @retval None
|
||
636 | */
|
||
637 | void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)
|
||
638 | { |
||
639 | assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); |
||
640 | assert_param(IS_FSMC_IT(FSMC_IT)); |
||
641 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
||
642 | |||
643 | if (NewState != DISABLE)
|
||
644 | { |
||
645 | /* Enable the selected FSMC_Bank2 interrupts */
|
||
646 | if(FSMC_Bank == FSMC_Bank2_NAND)
|
||
647 | { |
||
648 | FSMC_Bank2->SR2 |= FSMC_IT; |
||
649 | } |
||
650 | /* Enable the selected FSMC_Bank3 interrupts */
|
||
651 | else if (FSMC_Bank == FSMC_Bank3_NAND) |
||
652 | { |
||
653 | FSMC_Bank3->SR3 |= FSMC_IT; |
||
654 | } |
||
655 | /* Enable the selected FSMC_Bank4 interrupts */
|
||
656 | else
|
||
657 | { |
||
658 | FSMC_Bank4->SR4 |= FSMC_IT; |
||
659 | } |
||
660 | } |
||
661 | else
|
||
662 | { |
||
663 | /* Disable the selected FSMC_Bank2 interrupts */
|
||
664 | if(FSMC_Bank == FSMC_Bank2_NAND)
|
||
665 | { |
||
666 | |||
667 | FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT; |
||
668 | } |
||
669 | /* Disable the selected FSMC_Bank3 interrupts */
|
||
670 | else if (FSMC_Bank == FSMC_Bank3_NAND) |
||
671 | { |
||
672 | FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT; |
||
673 | } |
||
674 | /* Disable the selected FSMC_Bank4 interrupts */
|
||
675 | else
|
||
676 | { |
||
677 | FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT; |
||
678 | } |
||
679 | } |
||
680 | } |
||
681 | |||
682 | /**
|
||
683 | * @brief Checks whether the specified FSMC flag is set or not.
|
||
684 | * @param FSMC_Bank: specifies the FSMC Bank to be used
|
||
685 | * This parameter can be one of the following values:
|
||
686 | * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
|
||
687 | * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
|
||
688 | * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
|
||
689 | * @param FSMC_FLAG: specifies the flag to check.
|
||
690 | * This parameter can be one of the following values:
|
||
691 | * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.
|
||
692 | * @arg FSMC_FLAG_Level: Level detection Flag.
|
||
693 | * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.
|
||
694 | * @arg FSMC_FLAG_FEMPT: Fifo empty Flag.
|
||
695 | * @retval The new state of FSMC_FLAG (SET or RESET).
|
||
696 | */
|
||
697 | FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) |
||
698 | { |
||
699 | FlagStatus bitstatus = RESET; |
||
700 | uint32_t tmpsr = 0x00000000;
|
||
701 | |||
702 | /* Check the parameters */
|
||
703 | assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); |
||
704 | assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG)); |
||
705 | |||
706 | if(FSMC_Bank == FSMC_Bank2_NAND)
|
||
707 | { |
||
708 | tmpsr = FSMC_Bank2->SR2; |
||
709 | } |
||
710 | else if(FSMC_Bank == FSMC_Bank3_NAND) |
||
711 | { |
||
712 | tmpsr = FSMC_Bank3->SR3; |
||
713 | } |
||
714 | /* FSMC_Bank4_PCCARD*/
|
||
715 | else
|
||
716 | { |
||
717 | tmpsr = FSMC_Bank4->SR4; |
||
718 | } |
||
719 | |||
720 | /* Get the flag status */
|
||
721 | if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET )
|
||
722 | { |
||
723 | bitstatus = SET; |
||
724 | } |
||
725 | else
|
||
726 | { |
||
727 | bitstatus = RESET; |
||
728 | } |
||
729 | /* Return the flag status */
|
||
730 | return bitstatus;
|
||
731 | } |
||
732 | |||
733 | /**
|
||
734 | * @brief Clears the FSMC's pending flags.
|
||
735 | * @param FSMC_Bank: specifies the FSMC Bank to be used
|
||
736 | * This parameter can be one of the following values:
|
||
737 | * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
|
||
738 | * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
|
||
739 | * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
|
||
740 | * @param FSMC_FLAG: specifies the flag to clear.
|
||
741 | * This parameter can be any combination of the following values:
|
||
742 | * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag.
|
||
743 | * @arg FSMC_FLAG_Level: Level detection Flag.
|
||
744 | * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag.
|
||
745 | * @retval None
|
||
746 | */
|
||
747 | void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
|
||
748 | { |
||
749 | /* Check the parameters */
|
||
750 | assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); |
||
751 | assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ; |
||
752 | |||
753 | if(FSMC_Bank == FSMC_Bank2_NAND)
|
||
754 | { |
||
755 | FSMC_Bank2->SR2 &= ~FSMC_FLAG; |
||
756 | } |
||
757 | else if(FSMC_Bank == FSMC_Bank3_NAND) |
||
758 | { |
||
759 | FSMC_Bank3->SR3 &= ~FSMC_FLAG; |
||
760 | } |
||
761 | /* FSMC_Bank4_PCCARD*/
|
||
762 | else
|
||
763 | { |
||
764 | FSMC_Bank4->SR4 &= ~FSMC_FLAG; |
||
765 | } |
||
766 | } |
||
767 | |||
768 | /**
|
||
769 | * @brief Checks whether the specified FSMC interrupt has occurred or not.
|
||
770 | * @param FSMC_Bank: specifies the FSMC Bank to be used
|
||
771 | * This parameter can be one of the following values:
|
||
772 | * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
|
||
773 | * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
|
||
774 | * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
|
||
775 | * @param FSMC_IT: specifies the FSMC interrupt source to check.
|
||
776 | * This parameter can be one of the following values:
|
||
777 | * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
|
||
778 | * @arg FSMC_IT_Level: Level edge detection interrupt.
|
||
779 | * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
|
||
780 | * @retval The new state of FSMC_IT (SET or RESET).
|
||
781 | */
|
||
782 | ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT) |
||
783 | { |
||
784 | ITStatus bitstatus = RESET; |
||
785 | uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0; |
||
786 | |||
787 | /* Check the parameters */
|
||
788 | assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); |
||
789 | assert_param(IS_FSMC_GET_IT(FSMC_IT)); |
||
790 | |||
791 | if(FSMC_Bank == FSMC_Bank2_NAND)
|
||
792 | { |
||
793 | tmpsr = FSMC_Bank2->SR2; |
||
794 | } |
||
795 | else if(FSMC_Bank == FSMC_Bank3_NAND) |
||
796 | { |
||
797 | tmpsr = FSMC_Bank3->SR3; |
||
798 | } |
||
799 | /* FSMC_Bank4_PCCARD*/
|
||
800 | else
|
||
801 | { |
||
802 | tmpsr = FSMC_Bank4->SR4; |
||
803 | } |
||
804 | |||
805 | itstatus = tmpsr & FSMC_IT; |
||
806 | |||
807 | itenable = tmpsr & (FSMC_IT >> 3);
|
||
808 | if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET))
|
||
809 | { |
||
810 | bitstatus = SET; |
||
811 | } |
||
812 | else
|
||
813 | { |
||
814 | bitstatus = RESET; |
||
815 | } |
||
816 | return bitstatus;
|
||
817 | } |
||
818 | |||
819 | /**
|
||
820 | * @brief Clears the FSMC's interrupt pending bits.
|
||
821 | * @param FSMC_Bank: specifies the FSMC Bank to be used
|
||
822 | * This parameter can be one of the following values:
|
||
823 | * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND
|
||
824 | * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
|
||
825 | * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
|
||
826 | * @param FSMC_IT: specifies the interrupt pending bit to clear.
|
||
827 | * This parameter can be any combination of the following values:
|
||
828 | * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt.
|
||
829 | * @arg FSMC_IT_Level: Level edge detection interrupt.
|
||
830 | * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
|
||
831 | * @retval None
|
||
832 | */
|
||
833 | void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT)
|
||
834 | { |
||
835 | /* Check the parameters */
|
||
836 | assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); |
||
837 | assert_param(IS_FSMC_IT(FSMC_IT)); |
||
838 | |||
839 | if(FSMC_Bank == FSMC_Bank2_NAND)
|
||
840 | { |
||
841 | FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3);
|
||
842 | } |
||
843 | else if(FSMC_Bank == FSMC_Bank3_NAND) |
||
844 | { |
||
845 | FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3);
|
||
846 | } |
||
847 | /* FSMC_Bank4_PCCARD*/
|
||
848 | else
|
||
849 | { |
||
850 | FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3);
|
||
851 | } |
||
852 | } |
||
853 | |||
854 | /**
|
||
855 | * @}
|
||
856 | */
|
||
857 | |||
858 | /**
|
||
859 | * @}
|
||
860 | */
|
||
861 | |||
862 | /**
|
||
863 | * @}
|
||
864 | */
|
||
865 | |||
866 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|