amiro-blt / Target / Demo / ARMCM4_STM32F405_Power_Management_GCC / Boot / lib / stdperiphlib / STM32F4xx_StdPeriph_Driver / inc / stm32f4xx_rcc.h @ 69661903
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1 | 69661903 | Thomas Schöpping | /**
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2 | ******************************************************************************
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3 | * @file stm32f4xx_rcc.h
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4 | * @author MCD Application Team
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5 | * @version V1.1.0
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6 | * @date 11-January-2013
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7 | * @brief This file contains all the functions prototypes for the RCC firmware library.
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8 | ******************************************************************************
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9 | * @attention
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10 | *
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11 | * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
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12 | *
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13 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
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14 | * You may not use this file except in compliance with the License.
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15 | * You may obtain a copy of the License at:
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16 | *
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17 | * http://www.st.com/software_license_agreement_liberty_v2
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18 | *
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19 | * Unless required by applicable law or agreed to in writing, software
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20 | * distributed under the License is distributed on an "AS IS" BASIS,
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21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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22 | * See the License for the specific language governing permissions and
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23 | * limitations under the License.
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24 | *
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25 | ******************************************************************************
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26 | */
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27 | |||
28 | /* Define to prevent recursive inclusion -------------------------------------*/
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29 | #ifndef __STM32F4xx_RCC_H
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30 | #define __STM32F4xx_RCC_H
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31 | |||
32 | #ifdef __cplusplus
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33 | extern "C" { |
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34 | #endif
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35 | |||
36 | /* Includes ------------------------------------------------------------------*/
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37 | #include "stm32f4xx.h" |
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38 | |||
39 | /** @addtogroup STM32F4xx_StdPeriph_Driver
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40 | * @{
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41 | */
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42 | |||
43 | /** @addtogroup RCC
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44 | * @{
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45 | */
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46 | |||
47 | /* Exported types ------------------------------------------------------------*/
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48 | typedef struct |
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49 | { |
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50 | uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency expressed in Hz */
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51 | uint32_t HCLK_Frequency; /*!< HCLK clock frequency expressed in Hz */
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52 | uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency expressed in Hz */
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53 | uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency expressed in Hz */
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54 | }RCC_ClocksTypeDef; |
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55 | |||
56 | /* Exported constants --------------------------------------------------------*/
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57 | |||
58 | /** @defgroup RCC_Exported_Constants
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59 | * @{
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60 | */
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61 | |||
62 | /** @defgroup RCC_HSE_configuration
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63 | * @{
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64 | */
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65 | #define RCC_HSE_OFF ((uint8_t)0x00) |
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66 | #define RCC_HSE_ON ((uint8_t)0x01) |
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67 | #define RCC_HSE_Bypass ((uint8_t)0x05) |
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68 | #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
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69 | ((HSE) == RCC_HSE_Bypass)) |
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70 | /**
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71 | * @}
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72 | */
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73 | |||
74 | /** @defgroup RCC_PLL_Clock_Source
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75 | * @{
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76 | */
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77 | #define RCC_PLLSource_HSI ((uint32_t)0x00000000) |
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78 | #define RCC_PLLSource_HSE ((uint32_t)0x00400000) |
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79 | #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \
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80 | ((SOURCE) == RCC_PLLSource_HSE)) |
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81 | #define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63) |
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82 | #define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432)) |
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83 | #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8)) |
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84 | #define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15)) |
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85 | |||
86 | #define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432)) |
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87 | #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) |
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88 | |||
89 | /**
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90 | * @}
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91 | */
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92 | |||
93 | /** @defgroup RCC_System_Clock_Source
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94 | * @{
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95 | */
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96 | #define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) |
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97 | #define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) |
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98 | #define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) |
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99 | #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
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100 | ((SOURCE) == RCC_SYSCLKSource_HSE) || \ |
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101 | ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) |
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102 | /**
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103 | * @}
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104 | */
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105 | |||
106 | /** @defgroup RCC_AHB_Clock_Source
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107 | * @{
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108 | */
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109 | #define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) |
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110 | #define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) |
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111 | #define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) |
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112 | #define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) |
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113 | #define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) |
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114 | #define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) |
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115 | #define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) |
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116 | #define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) |
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117 | #define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) |
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118 | #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
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119 | ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ |
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120 | ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ |
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121 | ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ |
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122 | ((HCLK) == RCC_SYSCLK_Div512)) |
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123 | /**
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124 | * @}
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125 | */
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126 | |||
127 | /** @defgroup RCC_APB1_APB2_Clock_Source
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128 | * @{
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129 | */
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130 | #define RCC_HCLK_Div1 ((uint32_t)0x00000000) |
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131 | #define RCC_HCLK_Div2 ((uint32_t)0x00001000) |
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132 | #define RCC_HCLK_Div4 ((uint32_t)0x00001400) |
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133 | #define RCC_HCLK_Div8 ((uint32_t)0x00001800) |
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134 | #define RCC_HCLK_Div16 ((uint32_t)0x00001C00) |
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135 | #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
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136 | ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ |
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137 | ((PCLK) == RCC_HCLK_Div16)) |
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138 | /**
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139 | * @}
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140 | */
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141 | |||
142 | /** @defgroup RCC_Interrupt_Source
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143 | * @{
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144 | */
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145 | #define RCC_IT_LSIRDY ((uint8_t)0x01) |
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146 | #define RCC_IT_LSERDY ((uint8_t)0x02) |
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147 | #define RCC_IT_HSIRDY ((uint8_t)0x04) |
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148 | #define RCC_IT_HSERDY ((uint8_t)0x08) |
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149 | #define RCC_IT_PLLRDY ((uint8_t)0x10) |
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150 | #define RCC_IT_PLLI2SRDY ((uint8_t)0x20) |
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151 | #define RCC_IT_CSS ((uint8_t)0x80) |
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152 | |||
153 | #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00)) |
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154 | #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
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155 | ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ |
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156 | ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \ |
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157 | ((IT) == RCC_IT_PLLI2SRDY)) |
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158 | #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00)) |
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159 | |||
160 | /**
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161 | * @}
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162 | */
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163 | |||
164 | /** @defgroup RCC_LSE_Configuration
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165 | * @{
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166 | */
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167 | #define RCC_LSE_OFF ((uint8_t)0x00) |
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168 | #define RCC_LSE_ON ((uint8_t)0x01) |
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169 | #define RCC_LSE_Bypass ((uint8_t)0x04) |
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170 | #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
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171 | ((LSE) == RCC_LSE_Bypass)) |
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172 | /**
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173 | * @}
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174 | */
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175 | |||
176 | /** @defgroup RCC_RTC_Clock_Source
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177 | * @{
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178 | */
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179 | #define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) |
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180 | #define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) |
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181 | #define RCC_RTCCLKSource_HSE_Div2 ((uint32_t)0x00020300) |
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182 | #define RCC_RTCCLKSource_HSE_Div3 ((uint32_t)0x00030300) |
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183 | #define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)0x00040300) |
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184 | #define RCC_RTCCLKSource_HSE_Div5 ((uint32_t)0x00050300) |
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185 | #define RCC_RTCCLKSource_HSE_Div6 ((uint32_t)0x00060300) |
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186 | #define RCC_RTCCLKSource_HSE_Div7 ((uint32_t)0x00070300) |
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187 | #define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)0x00080300) |
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188 | #define RCC_RTCCLKSource_HSE_Div9 ((uint32_t)0x00090300) |
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189 | #define RCC_RTCCLKSource_HSE_Div10 ((uint32_t)0x000A0300) |
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190 | #define RCC_RTCCLKSource_HSE_Div11 ((uint32_t)0x000B0300) |
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191 | #define RCC_RTCCLKSource_HSE_Div12 ((uint32_t)0x000C0300) |
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192 | #define RCC_RTCCLKSource_HSE_Div13 ((uint32_t)0x000D0300) |
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193 | #define RCC_RTCCLKSource_HSE_Div14 ((uint32_t)0x000E0300) |
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194 | #define RCC_RTCCLKSource_HSE_Div15 ((uint32_t)0x000F0300) |
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195 | #define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)0x00100300) |
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196 | #define RCC_RTCCLKSource_HSE_Div17 ((uint32_t)0x00110300) |
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197 | #define RCC_RTCCLKSource_HSE_Div18 ((uint32_t)0x00120300) |
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198 | #define RCC_RTCCLKSource_HSE_Div19 ((uint32_t)0x00130300) |
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199 | #define RCC_RTCCLKSource_HSE_Div20 ((uint32_t)0x00140300) |
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200 | #define RCC_RTCCLKSource_HSE_Div21 ((uint32_t)0x00150300) |
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201 | #define RCC_RTCCLKSource_HSE_Div22 ((uint32_t)0x00160300) |
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202 | #define RCC_RTCCLKSource_HSE_Div23 ((uint32_t)0x00170300) |
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203 | #define RCC_RTCCLKSource_HSE_Div24 ((uint32_t)0x00180300) |
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204 | #define RCC_RTCCLKSource_HSE_Div25 ((uint32_t)0x00190300) |
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205 | #define RCC_RTCCLKSource_HSE_Div26 ((uint32_t)0x001A0300) |
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206 | #define RCC_RTCCLKSource_HSE_Div27 ((uint32_t)0x001B0300) |
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207 | #define RCC_RTCCLKSource_HSE_Div28 ((uint32_t)0x001C0300) |
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208 | #define RCC_RTCCLKSource_HSE_Div29 ((uint32_t)0x001D0300) |
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209 | #define RCC_RTCCLKSource_HSE_Div30 ((uint32_t)0x001E0300) |
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210 | #define RCC_RTCCLKSource_HSE_Div31 ((uint32_t)0x001F0300) |
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211 | #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
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212 | ((SOURCE) == RCC_RTCCLKSource_LSI) || \ |
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213 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \ |
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214 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div3) || \ |
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215 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \ |
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216 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div5) || \ |
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217 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div6) || \ |
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218 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div7) || \ |
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219 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \ |
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220 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div9) || \ |
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221 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div10) || \ |
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222 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div11) || \ |
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223 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div12) || \ |
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224 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div13) || \ |
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225 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div14) || \ |
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226 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div15) || \ |
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227 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div16) || \ |
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228 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div17) || \ |
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229 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div18) || \ |
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230 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div19) || \ |
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231 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div20) || \ |
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232 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div21) || \ |
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233 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div22) || \ |
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234 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div23) || \ |
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235 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div24) || \ |
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236 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div25) || \ |
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237 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div26) || \ |
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238 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div27) || \ |
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239 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div28) || \ |
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240 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div29) || \ |
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241 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div30) || \ |
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242 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div31)) |
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243 | /**
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244 | * @}
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245 | */
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246 | |||
247 | /** @defgroup RCC_I2S_Clock_Source
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248 | * @{
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249 | */
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250 | #define RCC_I2S2CLKSource_PLLI2S ((uint8_t)0x00) |
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251 | #define RCC_I2S2CLKSource_Ext ((uint8_t)0x01) |
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252 | |||
253 | #define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_PLLI2S) || ((SOURCE) == RCC_I2S2CLKSource_Ext))
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254 | /**
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255 | * @}
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256 | */
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257 | |||
258 | /** @defgroup RCC_TIM_PRescaler_Selection
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259 | * @{
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260 | */
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261 | #define RCC_TIMPrescDesactivated ((uint8_t)0x00) |
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262 | #define RCC_TIMPrescActivated ((uint8_t)0x01) |
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263 | |||
264 | #define IS_RCC_TIMCLK_PRESCALER(VALUE) (((VALUE) == RCC_TIMPrescDesactivated) || ((VALUE) == RCC_TIMPrescActivated))
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265 | /**
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266 | * @}
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267 | */
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268 | |||
269 | /** @defgroup RCC_AHB1_Peripherals
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270 | * @{
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271 | */
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272 | #define RCC_AHB1Periph_GPIOA ((uint32_t)0x00000001) |
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273 | #define RCC_AHB1Periph_GPIOB ((uint32_t)0x00000002) |
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274 | #define RCC_AHB1Periph_GPIOC ((uint32_t)0x00000004) |
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275 | #define RCC_AHB1Periph_GPIOD ((uint32_t)0x00000008) |
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276 | #define RCC_AHB1Periph_GPIOE ((uint32_t)0x00000010) |
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277 | #define RCC_AHB1Periph_GPIOF ((uint32_t)0x00000020) |
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278 | #define RCC_AHB1Periph_GPIOG ((uint32_t)0x00000040) |
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279 | #define RCC_AHB1Periph_GPIOH ((uint32_t)0x00000080) |
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280 | #define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100) |
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281 | #define RCC_AHB1Periph_CRC ((uint32_t)0x00001000) |
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282 | #define RCC_AHB1Periph_FLITF ((uint32_t)0x00008000) |
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283 | #define RCC_AHB1Periph_SRAM1 ((uint32_t)0x00010000) |
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284 | #define RCC_AHB1Periph_SRAM2 ((uint32_t)0x00020000) |
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285 | #define RCC_AHB1Periph_BKPSRAM ((uint32_t)0x00040000) |
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286 | #define RCC_AHB1Periph_SRAM3 ((uint32_t)0x00080000) |
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287 | #define RCC_AHB1Periph_CCMDATARAMEN ((uint32_t)0x00100000) |
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288 | #define RCC_AHB1Periph_DMA1 ((uint32_t)0x00200000) |
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289 | #define RCC_AHB1Periph_DMA2 ((uint32_t)0x00400000) |
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290 | #define RCC_AHB1Periph_ETH_MAC ((uint32_t)0x02000000) |
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291 | #define RCC_AHB1Periph_ETH_MAC_Tx ((uint32_t)0x04000000) |
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292 | #define RCC_AHB1Periph_ETH_MAC_Rx ((uint32_t)0x08000000) |
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293 | #define RCC_AHB1Periph_ETH_MAC_PTP ((uint32_t)0x10000000) |
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294 | #define RCC_AHB1Periph_OTG_HS ((uint32_t)0x20000000) |
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295 | #define RCC_AHB1Periph_OTG_HS_ULPI ((uint32_t)0x40000000) |
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296 | |||
297 | #define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x818BEE00) == 0x00) && ((PERIPH) != 0x00)) |
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298 | #define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xDD9FEE00) == 0x00) && ((PERIPH) != 0x00)) |
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299 | #define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x81906E00) == 0x00) && ((PERIPH) != 0x00)) |
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300 | |||
301 | |||
302 | /**
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303 | * @}
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304 | */
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305 | |||
306 | /** @defgroup RCC_AHB2_Peripherals
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307 | * @{
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308 | */
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309 | #define RCC_AHB2Periph_DCMI ((uint32_t)0x00000001) |
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310 | #define RCC_AHB2Periph_CRYP ((uint32_t)0x00000010) |
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311 | #define RCC_AHB2Periph_HASH ((uint32_t)0x00000020) |
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312 | #define RCC_AHB2Periph_RNG ((uint32_t)0x00000040) |
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313 | #define RCC_AHB2Periph_OTG_FS ((uint32_t)0x00000080) |
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314 | #define IS_RCC_AHB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFF0E) == 0x00) && ((PERIPH) != 0x00)) |
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315 | /**
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316 | * @}
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317 | */
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318 | |||
319 | /** @defgroup RCC_AHB3_Peripherals
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320 | * @{
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321 | */
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322 | #define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001) |
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323 | |||
324 | #define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00)) |
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325 | /**
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326 | * @}
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327 | */
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328 | |||
329 | /** @defgroup RCC_APB1_Peripherals
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330 | * @{
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331 | */
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332 | #define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) |
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333 | #define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) |
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334 | #define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) |
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335 | #define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) |
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336 | #define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) |
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337 | #define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) |
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338 | #define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040) |
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339 | #define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080) |
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340 | #define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100) |
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341 | #define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) |
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342 | #define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) |
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343 | #define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) |
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344 | #define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) |
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345 | #define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) |
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346 | #define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) |
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347 | #define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) |
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348 | #define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) |
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349 | #define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) |
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350 | #define RCC_APB1Periph_I2C3 ((uint32_t)0x00800000) |
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351 | #define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) |
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352 | #define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) |
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353 | #define RCC_APB1Periph_PWR ((uint32_t)0x10000000) |
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354 | #define RCC_APB1Periph_DAC ((uint32_t)0x20000000) |
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355 | #define RCC_APB1Periph_UART7 ((uint32_t)0x40000000) |
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356 | #define RCC_APB1Periph_UART8 ((uint32_t)0x80000000) |
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357 | #define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x09013600) == 0x00) && ((PERIPH) != 0x00)) |
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358 | /**
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359 | * @}
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360 | */
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361 | |||
362 | /** @defgroup RCC_APB2_Peripherals
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363 | * @{
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364 | */
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365 | #define RCC_APB2Periph_TIM1 ((uint32_t)0x00000001) |
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366 | #define RCC_APB2Periph_TIM8 ((uint32_t)0x00000002) |
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367 | #define RCC_APB2Periph_USART1 ((uint32_t)0x00000010) |
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368 | #define RCC_APB2Periph_USART6 ((uint32_t)0x00000020) |
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369 | #define RCC_APB2Periph_ADC ((uint32_t)0x00000100) |
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370 | #define RCC_APB2Periph_ADC1 ((uint32_t)0x00000100) |
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371 | #define RCC_APB2Periph_ADC2 ((uint32_t)0x00000200) |
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372 | #define RCC_APB2Periph_ADC3 ((uint32_t)0x00000400) |
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373 | #define RCC_APB2Periph_SDIO ((uint32_t)0x00000800) |
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374 | #define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) |
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375 | #define RCC_APB2Periph_SPI4 ((uint32_t)0x00002000) |
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376 | #define RCC_APB2Periph_SYSCFG ((uint32_t)0x00004000) |
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377 | #define RCC_APB2Periph_TIM9 ((uint32_t)0x00010000) |
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378 | #define RCC_APB2Periph_TIM10 ((uint32_t)0x00020000) |
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379 | #define RCC_APB2Periph_TIM11 ((uint32_t)0x00040000) |
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380 | #define RCC_APB2Periph_SPI5 ((uint32_t)0x00100000) |
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381 | #define RCC_APB2Periph_SPI6 ((uint32_t)0x00200000) |
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382 | |||
383 | #define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFC880CC) == 0x00) && ((PERIPH) != 0x00)) |
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384 | #define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xFFC886CC) == 0x00) && ((PERIPH) != 0x00)) |
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385 | |||
386 | |||
387 | /**
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388 | * @}
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389 | */
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390 | |||
391 | /** @defgroup RCC_MCO1_Clock_Source_Prescaler
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392 | * @{
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393 | */
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394 | #define RCC_MCO1Source_HSI ((uint32_t)0x00000000) |
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395 | #define RCC_MCO1Source_LSE ((uint32_t)0x00200000) |
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396 | #define RCC_MCO1Source_HSE ((uint32_t)0x00400000) |
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397 | #define RCC_MCO1Source_PLLCLK ((uint32_t)0x00600000) |
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398 | #define RCC_MCO1Div_1 ((uint32_t)0x00000000) |
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399 | #define RCC_MCO1Div_2 ((uint32_t)0x04000000) |
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400 | #define RCC_MCO1Div_3 ((uint32_t)0x05000000) |
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401 | #define RCC_MCO1Div_4 ((uint32_t)0x06000000) |
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402 | #define RCC_MCO1Div_5 ((uint32_t)0x07000000) |
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403 | #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1Source_HSI) || ((SOURCE) == RCC_MCO1Source_LSE) || \
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404 | ((SOURCE) == RCC_MCO1Source_HSE) || ((SOURCE) == RCC_MCO1Source_PLLCLK)) |
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405 | |||
406 | #define IS_RCC_MCO1DIV(DIV) (((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) || \
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407 | ((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) || \ |
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408 | ((DIV) == RCC_MCO1Div_5)) |
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409 | /**
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410 | * @}
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411 | */
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412 | |||
413 | /** @defgroup RCC_MCO2_Clock_Source_Prescaler
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414 | * @{
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415 | */
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416 | #define RCC_MCO2Source_SYSCLK ((uint32_t)0x00000000) |
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417 | #define RCC_MCO2Source_PLLI2SCLK ((uint32_t)0x40000000) |
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418 | #define RCC_MCO2Source_HSE ((uint32_t)0x80000000) |
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419 | #define RCC_MCO2Source_PLLCLK ((uint32_t)0xC0000000) |
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420 | #define RCC_MCO2Div_1 ((uint32_t)0x00000000) |
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421 | #define RCC_MCO2Div_2 ((uint32_t)0x20000000) |
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422 | #define RCC_MCO2Div_3 ((uint32_t)0x28000000) |
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423 | #define RCC_MCO2Div_4 ((uint32_t)0x30000000) |
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424 | #define RCC_MCO2Div_5 ((uint32_t)0x38000000) |
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425 | #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2Source_SYSCLK) || ((SOURCE) == RCC_MCO2Source_PLLI2SCLK)|| \
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426 | ((SOURCE) == RCC_MCO2Source_HSE) || ((SOURCE) == RCC_MCO2Source_PLLCLK)) |
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427 | |||
428 | #define IS_RCC_MCO2DIV(DIV) (((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) || \
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429 | ((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) || \ |
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430 | ((DIV) == RCC_MCO2Div_5)) |
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431 | /**
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432 | * @}
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433 | */
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434 | |||
435 | /** @defgroup RCC_Flag
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436 | * @{
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437 | */
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438 | #define RCC_FLAG_HSIRDY ((uint8_t)0x21) |
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439 | #define RCC_FLAG_HSERDY ((uint8_t)0x31) |
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440 | #define RCC_FLAG_PLLRDY ((uint8_t)0x39) |
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441 | #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B) |
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442 | #define RCC_FLAG_LSERDY ((uint8_t)0x41) |
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443 | #define RCC_FLAG_LSIRDY ((uint8_t)0x61) |
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444 | #define RCC_FLAG_BORRST ((uint8_t)0x79) |
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445 | #define RCC_FLAG_PINRST ((uint8_t)0x7A) |
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446 | #define RCC_FLAG_PORRST ((uint8_t)0x7B) |
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447 | #define RCC_FLAG_SFTRST ((uint8_t)0x7C) |
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448 | #define RCC_FLAG_IWDGRST ((uint8_t)0x7D) |
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449 | #define RCC_FLAG_WWDGRST ((uint8_t)0x7E) |
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450 | #define RCC_FLAG_LPWRRST ((uint8_t)0x7F) |
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451 | |||
452 | #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
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453 | ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ |
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454 | ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \ |
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455 | ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ |
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456 | ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \ |
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457 | ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \ |
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458 | ((FLAG) == RCC_FLAG_PLLI2SRDY)) |
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459 | |||
460 | #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) |
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461 | /**
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462 | * @}
|
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463 | */
|
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464 | |||
465 | /**
|
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466 | * @}
|
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467 | */
|
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468 | |||
469 | /* Exported macro ------------------------------------------------------------*/
|
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470 | /* Exported functions --------------------------------------------------------*/
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471 | |||
472 | /* Function used to set the RCC clock configuration to the default reset state */
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473 | void RCC_DeInit(void); |
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474 | |||
475 | /* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
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476 | void RCC_HSEConfig(uint8_t RCC_HSE);
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477 | ErrorStatus RCC_WaitForHSEStartUp(void);
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478 | void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
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479 | void RCC_HSICmd(FunctionalState NewState);
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480 | void RCC_LSEConfig(uint8_t RCC_LSE);
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481 | void RCC_LSICmd(FunctionalState NewState);
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482 | |||
483 | void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ);
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484 | void RCC_PLLCmd(FunctionalState NewState);
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485 | void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR);
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486 | void RCC_PLLI2SCmd(FunctionalState NewState);
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487 | void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
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488 | void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div);
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489 | void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div);
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490 | |||
491 | /* System, AHB and APB busses clocks configuration functions ******************/
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492 | void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
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493 | uint8_t RCC_GetSYSCLKSource(void);
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494 | void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
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495 | void RCC_PCLK1Config(uint32_t RCC_HCLK);
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496 | void RCC_PCLK2Config(uint32_t RCC_HCLK);
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497 | void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
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498 | |||
499 | /* Peripheral clocks configuration functions **********************************/
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||
500 | void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
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501 | void RCC_RTCCLKCmd(FunctionalState NewState);
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||
502 | void RCC_BackupResetCmd(FunctionalState NewState);
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503 | void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource);
|
||
504 | void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler);
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505 | |||
506 | void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
|
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507 | void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
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508 | void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
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509 | void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
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510 | void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
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511 | |||
512 | void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
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513 | void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
|
||
514 | void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
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515 | void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
|
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516 | void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
|
||
517 | |||
518 | void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
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519 | void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
|
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520 | void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
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521 | void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
|
||
522 | void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
|
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523 | |||
524 | /* Interrupts and flags management functions **********************************/
|
||
525 | void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
|
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526 | FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); |
||
527 | void RCC_ClearFlag(void); |
||
528 | ITStatus RCC_GetITStatus(uint8_t RCC_IT); |
||
529 | void RCC_ClearITPendingBit(uint8_t RCC_IT);
|
||
530 | |||
531 | #ifdef __cplusplus
|
||
532 | } |
||
533 | #endif
|
||
534 | |||
535 | #endif /* __STM32F4xx_RCC_H */ |
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536 | |||
537 | /**
|
||
538 | * @}
|
||
539 | */
|
||
540 | |||
541 | /**
|
||
542 | * @}
|
||
543 | */
|
||
544 | |||
545 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|