amiro-blt / Target / Demo / ARMCM4_STM32F405_Power_Management_GCC / Boot / lib / stdperiphlib / STM32F4xx_StdPeriph_Driver / src / stm32f4xx_i2c.c @ 69661903
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| 1 | 69661903 | Thomas Schöpping | /**
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| 2 | ******************************************************************************
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| 3 | * @file stm32f4xx_i2c.c
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| 4 | * @author MCD Application Team
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| 5 | * @version V1.1.0
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| 6 | * @date 11-January-2013
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| 7 | * @brief This file provides firmware functions to manage the following
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| 8 | * functionalities of the Inter-integrated circuit (I2C)
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| 9 | * + Initialization and Configuration
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| 10 | * + Data transfers
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| 11 | * + PEC management
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| 12 | * + DMA transfers management
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| 13 | * + Interrupts, events and flags management
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| 14 | *
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| 15 | @verbatim
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| 16 | ===============================================================================
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| 17 | ##### How to use this driver #####
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| 18 | ===============================================================================
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| 19 | [..]
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| 20 | (#) Enable peripheral clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2Cx, ENABLE)
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| 21 | function for I2C1, I2C2 or I2C3.
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| 22 |
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| 23 | (#) Enable SDA, SCL and SMBA (when used) GPIO clocks using
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| 24 | RCC_AHBPeriphClockCmd() function.
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| 25 |
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| 26 | (#) Peripherals alternate function:
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| 27 | (++) Connect the pin to the desired peripherals' Alternate
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| 28 | Function (AF) using GPIO_PinAFConfig() function
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| 29 | (++) Configure the desired pin in alternate function by:
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| 30 | GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
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| 31 | (++) Select the type, pull-up/pull-down and output speed via
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| 32 | GPIO_PuPd, GPIO_OType and GPIO_Speed members
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| 33 | (++) Call GPIO_Init() function
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| 34 | Recommended configuration is Push-Pull, Pull-up, Open-Drain.
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| 35 | Add an external pull up if necessary (typically 4.7 KOhm).
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| 36 |
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| 37 | (#) Program the Mode, duty cycle , Own address, Ack, Speed and Acknowledged
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| 38 | Address using the I2C_Init() function.
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| 39 |
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| 40 | (#) Optionally you can enable/configure the following parameters without
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| 41 | re-initialization (i.e there is no need to call again I2C_Init() function):
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| 42 | (++) Enable the acknowledge feature using I2C_AcknowledgeConfig() function
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| 43 | (++) Enable the dual addressing mode using I2C_DualAddressCmd() function
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| 44 | (++) Enable the general call using the I2C_GeneralCallCmd() function
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| 45 | (++) Enable the clock stretching using I2C_StretchClockCmd() function
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| 46 | (++) Enable the fast mode duty cycle using the I2C_FastModeDutyCycleConfig()
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| 47 | function.
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| 48 | (++) Configure the NACK position for Master Receiver mode in case of
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| 49 | 2 bytes reception using the function I2C_NACKPositionConfig().
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| 50 | (++) Enable the PEC Calculation using I2C_CalculatePEC() function
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| 51 | (++) For SMBus Mode:
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| 52 | (+++) Enable the Address Resolution Protocol (ARP) using I2C_ARPCmd() function
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| 53 | (+++) Configure the SMBusAlert pin using I2C_SMBusAlertConfig() function
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| 54 |
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| 55 | (#) Enable the NVIC and the corresponding interrupt using the function
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| 56 | I2C_ITConfig() if you need to use interrupt mode.
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| 57 |
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| 58 | (#) When using the DMA mode
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| 59 | (++) Configure the DMA using DMA_Init() function
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| 60 | (++) Active the needed channel Request using I2C_DMACmd() or
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| 61 | I2C_DMALastTransferCmd() function.
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| 62 | -@@- When using DMA mode, I2C interrupts may be used at the same time to
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| 63 | control the communication flow (Start/Stop/Ack... events and errors).
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| 64 |
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| 65 | (#) Enable the I2C using the I2C_Cmd() function.
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| 66 |
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| 67 | (#) Enable the DMA using the DMA_Cmd() function when using DMA mode in the
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| 68 | transfers.
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| 69 |
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| 70 | @endverbatim
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| 71 | ******************************************************************************
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| 72 | * @attention
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| 73 | *
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| 74 | * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
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| 75 | *
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| 76 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
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| 77 | * You may not use this file except in compliance with the License.
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| 78 | * You may obtain a copy of the License at:
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| 79 | *
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| 80 | * http://www.st.com/software_license_agreement_liberty_v2
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| 81 | *
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| 82 | * Unless required by applicable law or agreed to in writing, software
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| 83 | * distributed under the License is distributed on an "AS IS" BASIS,
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| 84 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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| 85 | * See the License for the specific language governing permissions and
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| 86 | * limitations under the License.
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| 87 | *
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| 88 | ******************************************************************************
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| 89 | */
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| 90 | |||
| 91 | /* Includes ------------------------------------------------------------------*/
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| 92 | #include "stm32f4xx_i2c.h" |
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| 93 | #include "stm32f4xx_rcc.h" |
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| 94 | |||
| 95 | /** @addtogroup STM32F4xx_StdPeriph_Driver
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| 96 | * @{
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| 97 | */
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| 98 | |||
| 99 | /** @defgroup I2C
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| 100 | * @brief I2C driver modules
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| 101 | * @{
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| 102 | */
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| 103 | |||
| 104 | /* Private typedef -----------------------------------------------------------*/
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| 105 | /* Private define ------------------------------------------------------------*/
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| 106 | |||
| 107 | #define CR1_CLEAR_MASK ((uint16_t)0xFBF5) /*<! I2C registers Masks */ |
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| 108 | #define FLAG_MASK ((uint32_t)0x00FFFFFF) /*<! I2C FLAG mask */ |
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| 109 | #define ITEN_MASK ((uint32_t)0x07000000) /*<! I2C Interrupt Enable mask */ |
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| 110 | |||
| 111 | /* Private macro -------------------------------------------------------------*/
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| 112 | /* Private variables ---------------------------------------------------------*/
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| 113 | /* Private function prototypes -----------------------------------------------*/
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| 114 | /* Private functions ---------------------------------------------------------*/
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| 115 | |||
| 116 | /** @defgroup I2C_Private_Functions
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| 117 | * @{
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| 118 | */
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| 119 | |||
| 120 | /** @defgroup I2C_Group1 Initialization and Configuration functions
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| 121 | * @brief Initialization and Configuration functions
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| 122 | *
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| 123 | @verbatim
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| 124 | ===============================================================================
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| 125 | ##### Initialization and Configuration functions #####
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| 126 | ===============================================================================
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| 127 | |||
| 128 | @endverbatim
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| 129 | * @{
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| 130 | */
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| 131 | |||
| 132 | /**
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| 133 | * @brief Deinitialize the I2Cx peripheral registers to their default reset values.
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| 134 | * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
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| 135 | * @retval None
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| 136 | */
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| 137 | void I2C_DeInit(I2C_TypeDef* I2Cx)
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| 138 | {
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| 139 | /* Check the parameters */
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| 140 | assert_param(IS_I2C_ALL_PERIPH(I2Cx)); |
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| 141 | |||
| 142 | if (I2Cx == I2C1)
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| 143 | {
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| 144 | /* Enable I2C1 reset state */
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| 145 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE); |
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| 146 | /* Release I2C1 from reset state */
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| 147 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE); |
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| 148 | } |
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| 149 | else if (I2Cx == I2C2) |
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| 150 | {
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| 151 | /* Enable I2C2 reset state */
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| 152 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE); |
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| 153 | /* Release I2C2 from reset state */
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| 154 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE); |
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| 155 | } |
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| 156 | else
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| 157 | {
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| 158 | if (I2Cx == I2C3)
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| 159 | {
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| 160 | /* Enable I2C3 reset state */
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| 161 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C3, ENABLE); |
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| 162 | /* Release I2C3 from reset state */
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| 163 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C3, DISABLE); |
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| 164 | } |
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| 165 | } |
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| 166 | } |
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| 167 | |||
| 168 | /**
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| 169 | * @brief Initializes the I2Cx peripheral according to the specified
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| 170 | * parameters in the I2C_InitStruct.
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| 171 | *
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| 172 | * @note To use the I2C at 400 KHz (in fast mode), the PCLK1 frequency
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| 173 | * (I2C peripheral input clock) must be a multiple of 10 MHz.
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| 174 | *
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| 175 | * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
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| 176 | * @param I2C_InitStruct: pointer to a I2C_InitTypeDef structure that contains
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| 177 | * the configuration information for the specified I2C peripheral.
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| 178 | * @retval None
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| 179 | */
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| 180 | void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)
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| 181 | {
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| 182 | uint16_t tmpreg = 0, freqrange = 0; |
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| 183 | uint16_t result = 0x04;
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| 184 | uint32_t pclk1 = 8000000;
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| 185 | RCC_ClocksTypeDef rcc_clocks; |
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| 186 | /* Check the parameters */
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| 187 | assert_param(IS_I2C_ALL_PERIPH(I2Cx)); |
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| 188 | assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed)); |
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| 189 | assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode)); |
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| 190 | assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle)); |
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| 191 | assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1)); |
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| 192 | assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack)); |
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| 193 | assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress)); |
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| 194 | |||
| 195 | /*---------------------------- I2Cx CR2 Configuration ------------------------*/
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| 196 | /* Get the I2Cx CR2 value */
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| 197 | tmpreg = I2Cx->CR2; |
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| 198 | /* Clear frequency FREQ[5:0] bits */
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| 199 | tmpreg &= (uint16_t)~((uint16_t)I2C_CR2_FREQ); |
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| 200 | /* Get pclk1 frequency value */
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| 201 | RCC_GetClocksFreq(&rcc_clocks); |
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| 202 | pclk1 = rcc_clocks.PCLK1_Frequency; |
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| 203 | /* Set frequency bits depending on pclk1 value */
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| 204 | freqrange = (uint16_t)(pclk1 / 1000000);
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| 205 | tmpreg |= freqrange; |
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| 206 | /* Write to I2Cx CR2 */
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| 207 | I2Cx->CR2 = tmpreg; |
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| 208 | |||
| 209 | /*---------------------------- I2Cx CCR Configuration ------------------------*/
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| 210 | /* Disable the selected I2C peripheral to configure TRISE */
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| 211 | I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PE); |
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| 212 | /* Reset tmpreg value */
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| 213 | /* Clear F/S, DUTY and CCR[11:0] bits */
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| 214 | tmpreg = 0;
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| 215 | |||
| 216 | /* Configure speed in standard mode */
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| 217 | if (I2C_InitStruct->I2C_ClockSpeed <= 100000) |
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| 218 | {
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| 219 | /* Standard mode speed calculate */
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| 220 | result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1));
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| 221 | /* Test if CCR value is under 0x4*/
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| 222 | if (result < 0x04) |
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| 223 | {
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| 224 | /* Set minimum allowed value */
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| 225 | result = 0x04;
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| 226 | } |
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| 227 | /* Set speed value for standard mode */
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| 228 | tmpreg |= result; |
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| 229 | /* Set Maximum Rise Time for standard mode */
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| 230 | I2Cx->TRISE = freqrange + 1;
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| 231 | } |
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| 232 | /* Configure speed in fast mode */
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| 233 | /* To use the I2C at 400 KHz (in fast mode), the PCLK1 frequency (I2C peripheral
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| 234 | input clock) must be a multiple of 10 MHz */
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| 235 | else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/ |
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| 236 | {
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| 237 | if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2)
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| 238 | {
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| 239 | /* Fast mode speed calculate: Tlow/Thigh = 2 */
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| 240 | result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3));
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| 241 | } |
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| 242 | else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/ |
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| 243 | {
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| 244 | /* Fast mode speed calculate: Tlow/Thigh = 16/9 */
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| 245 | result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25));
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| 246 | /* Set DUTY bit */
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| 247 | result |= I2C_DutyCycle_16_9; |
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| 248 | } |
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| 249 | |||
| 250 | /* Test if CCR value is under 0x1*/
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| 251 | if ((result & I2C_CCR_CCR) == 0) |
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| 252 | {
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| 253 | /* Set minimum allowed value */
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| 254 | result |= (uint16_t)0x0001;
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| 255 | } |
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| 256 | /* Set speed value and set F/S bit for fast mode */
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| 257 | tmpreg |= (uint16_t)(result | I2C_CCR_FS); |
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| 258 | /* Set Maximum Rise Time for fast mode */
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| 259 | I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1); |
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| 260 | } |
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| 261 | |||
| 262 | /* Write to I2Cx CCR */
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| 263 | I2Cx->CCR = tmpreg; |
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| 264 | /* Enable the selected I2C peripheral */
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| 265 | I2Cx->CR1 |= I2C_CR1_PE; |
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| 266 | |||
| 267 | /*---------------------------- I2Cx CR1 Configuration ------------------------*/
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| 268 | /* Get the I2Cx CR1 value */
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| 269 | tmpreg = I2Cx->CR1; |
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| 270 | /* Clear ACK, SMBTYPE and SMBUS bits */
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| 271 | tmpreg &= CR1_CLEAR_MASK; |
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| 272 | /* Configure I2Cx: mode and acknowledgement */
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| 273 | /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */
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| 274 | /* Set ACK bit according to I2C_Ack value */
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| 275 | tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack); |
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| 276 | /* Write to I2Cx CR1 */
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| 277 | I2Cx->CR1 = tmpreg; |
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| 278 | |||
| 279 | /*---------------------------- I2Cx OAR1 Configuration -----------------------*/
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| 280 | /* Set I2Cx Own Address1 and acknowledged address */
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| 281 | I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1); |
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| 282 | } |
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| 283 | |||
| 284 | /**
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| 285 | * @brief Fills each I2C_InitStruct member with its default value.
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| 286 | * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized.
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| 287 | * @retval None
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| 288 | */
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| 289 | void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)
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| 290 | {
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| 291 | /*---------------- Reset I2C init structure parameters values ----------------*/
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| 292 | /* initialize the I2C_ClockSpeed member */
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| 293 | I2C_InitStruct->I2C_ClockSpeed = 5000;
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| 294 | /* Initialize the I2C_Mode member */
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| 295 | I2C_InitStruct->I2C_Mode = I2C_Mode_I2C; |
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| 296 | /* Initialize the I2C_DutyCycle member */
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| 297 | I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2; |
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| 298 | /* Initialize the I2C_OwnAddress1 member */
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| 299 | I2C_InitStruct->I2C_OwnAddress1 = 0;
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| 300 | /* Initialize the I2C_Ack member */
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| 301 | I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; |
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| 302 | /* Initialize the I2C_AcknowledgedAddress member */
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| 303 | I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; |
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| 304 | } |
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| 305 | |||
| 306 | /**
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| 307 | * @brief Enables or disables the specified I2C peripheral.
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| 308 | * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
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| 309 | * @param NewState: new state of the I2Cx peripheral.
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| 310 | * This parameter can be: ENABLE or DISABLE.
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| 311 | * @retval None
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| 312 | */
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| 313 | void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
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| 314 | {
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| 315 | /* Check the parameters */
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| 316 | assert_param(IS_I2C_ALL_PERIPH(I2Cx)); |
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| 317 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
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| 318 | if (NewState != DISABLE)
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| 319 | {
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| 320 | /* Enable the selected I2C peripheral */
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| 321 | I2Cx->CR1 |= I2C_CR1_PE; |
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| 322 | } |
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| 323 | else
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| 324 | {
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| 325 | /* Disable the selected I2C peripheral */
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| 326 | I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PE); |
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| 327 | } |
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| 328 | } |
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| 329 | |||
| 330 | /**
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| 331 | * @brief Enables or disables the Analog filter of I2C peripheral.
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| 332 | * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
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| 333 | * @param NewState: new state of the Analog filter.
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| 334 | * This parameter can be: ENABLE or DISABLE.
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| 335 | * @note This function should be called before initializing and enabling
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| 336 | the I2C Peripheral.
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| 337 | * @retval None
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| 338 | */
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| 339 | void I2C_AnalogFilterCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
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| 340 | {
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| 341 | /* Check the parameters */
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| 342 | assert_param(IS_I2C_ALL_PERIPH(I2Cx)); |
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| 343 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
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| 344 | if (NewState != DISABLE)
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| 345 | {
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| 346 | /* Enable the analog filter */
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| 347 | I2Cx->FLTR &= (uint16_t)~((uint16_t)I2C_FLTR_ANOFF); |
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| 348 | } |
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| 349 | else
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| 350 | {
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| 351 | /* Disable the analog filter */
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| 352 | I2Cx->FLTR |= I2C_FLTR_ANOFF; |
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| 353 | } |
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| 354 | } |
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| 355 | |||
| 356 | /**
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| 357 | * @brief Configures the Digital noise filter of I2C peripheral.
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| 358 | * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
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| 359 | * @param I2C_DigitalFilter: Coefficient of digital noise filter.
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| 360 | * This parameter can be a number between 0x00 and 0x0F.
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| 361 | * @note This function should be called before initializing and enabling
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| 362 | the I2C Peripheral.
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| 363 | * @retval None
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| 364 | */
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| 365 | void I2C_DigitalFilterConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DigitalFilter)
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| 366 | {
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| 367 | uint16_t tmpreg = 0;
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| 368 | |||
| 369 | /* Check the parameters */
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| 370 | assert_param(IS_I2C_ALL_PERIPH(I2Cx)); |
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| 371 | assert_param(IS_I2C_DIGITAL_FILTER(I2C_DigitalFilter)); |
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| 372 | |||
| 373 | /* Get the old register value */
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| 374 | tmpreg = I2Cx->FLTR; |
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| 375 | |||
| 376 | /* Reset I2Cx DNF bit [3:0] */
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| 377 | tmpreg &= (uint16_t)~((uint16_t)I2C_FLTR_DNF); |
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| 378 | |||
| 379 | /* Set I2Cx DNF coefficient */
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| 380 | tmpreg |= (uint16_t)((uint16_t)I2C_DigitalFilter & I2C_FLTR_DNF); |
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| 381 | |||
| 382 | /* Store the new register value */
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| 383 | I2Cx->FLTR = tmpreg; |
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| 384 | } |
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| 385 | |||
| 386 | /**
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| 387 | * @brief Generates I2Cx communication START condition.
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| 388 | * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
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| 389 | * @param NewState: new state of the I2C START condition generation.
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| 390 | * This parameter can be: ENABLE or DISABLE.
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| 391 | * @retval None.
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| 392 | */
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| 393 | void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState)
|
||
| 394 | {
|
||
| 395 | /* Check the parameters */
|
||
| 396 | assert_param(IS_I2C_ALL_PERIPH(I2Cx)); |
||
| 397 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
||
| 398 | if (NewState != DISABLE)
|
||
| 399 | {
|
||
| 400 | /* Generate a START condition */
|
||
| 401 | I2Cx->CR1 |= I2C_CR1_START; |
||
| 402 | } |
||
| 403 | else
|
||
| 404 | {
|
||
| 405 | /* Disable the START condition generation */
|
||
| 406 | I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_START); |
||
| 407 | } |
||
| 408 | } |
||
| 409 | |||
| 410 | /**
|
||
| 411 | * @brief Generates I2Cx communication STOP condition.
|
||
| 412 | * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
|
||
| 413 | * @param NewState: new state of the I2C STOP condition generation.
|
||
| 414 | * This parameter can be: ENABLE or DISABLE.
|
||
| 415 | * @retval None.
|
||
| 416 | */
|
||
| 417 | void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState)
|
||
| 418 | {
|
||
| 419 | /* Check the parameters */
|
||
| 420 | assert_param(IS_I2C_ALL_PERIPH(I2Cx)); |
||
| 421 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
||
| 422 | if (NewState != DISABLE)
|
||
| 423 | {
|
||
| 424 | /* Generate a STOP condition */
|
||
| 425 | I2Cx->CR1 |= I2C_CR1_STOP; |
||
| 426 | } |
||
| 427 | else
|
||
| 428 | {
|
||
| 429 | /* Disable the STOP condition generation */
|
||
| 430 | I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_STOP); |
||
| 431 | } |
||
| 432 | } |
||
| 433 | |||
| 434 | /**
|
||
| 435 | * @brief Transmits the address byte to select the slave device.
|
||
| 436 | * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
|
||
| 437 | * @param Address: specifies the slave address which will be transmitted
|
||
| 438 | * @param I2C_Direction: specifies whether the I2C device will be a Transmitter
|
||
| 439 | * or a Receiver.
|
||
| 440 | * This parameter can be one of the following values
|
||
| 441 | * @arg I2C_Direction_Transmitter: Transmitter mode
|
||
| 442 | * @arg I2C_Direction_Receiver: Receiver mode
|
||
| 443 | * @retval None.
|
||
| 444 | */
|
||
| 445 | void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction)
|
||
| 446 | {
|
||
| 447 | /* Check the parameters */
|
||
| 448 | assert_param(IS_I2C_ALL_PERIPH(I2Cx)); |
||
| 449 | assert_param(IS_I2C_DIRECTION(I2C_Direction)); |
||
| 450 | /* Test on the direction to set/reset the read/write bit */
|
||
| 451 | if (I2C_Direction != I2C_Direction_Transmitter)
|
||
| 452 | {
|
||
| 453 | /* Set the address bit0 for read */
|
||
| 454 | Address |= I2C_OAR1_ADD0; |
||
| 455 | } |
||
| 456 | else
|
||
| 457 | {
|
||
| 458 | /* Reset the address bit0 for write */
|
||
| 459 | Address &= (uint8_t)~((uint8_t)I2C_OAR1_ADD0); |
||
| 460 | } |
||
| 461 | /* Send the address */
|
||
| 462 | I2Cx->DR = Address; |
||
| 463 | } |
||
| 464 | |||
| 465 | /**
|
||
| 466 | * @brief Enables or disables the specified I2C acknowledge feature.
|
||
| 467 | * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
|
||
| 468 | * @param NewState: new state of the I2C Acknowledgement.
|
||
| 469 | * This parameter can be: ENABLE or DISABLE.
|
||
| 470 | * @retval None.
|
||
| 471 | */
|
||
| 472 | void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState)
|
||
| 473 | {
|
||
| 474 | /* Check the parameters */
|
||
| 475 | assert_param(IS_I2C_ALL_PERIPH(I2Cx)); |
||
| 476 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
||
| 477 | if (NewState != DISABLE)
|
||
| 478 | {
|
||
| 479 | /* Enable the acknowledgement */
|
||
| 480 | I2Cx->CR1 |= I2C_CR1_ACK; |
||
| 481 | } |
||
| 482 | else
|
||
| 483 | {
|
||
| 484 | /* Disable the acknowledgement */
|
||
| 485 | I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ACK); |
||
| 486 | } |
||
| 487 | } |
||
| 488 | |||
| 489 | /**
|
||
| 490 | * @brief Configures the specified I2C own address2.
|
||
| 491 | * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
|
||
| 492 | * @param Address: specifies the 7bit I2C own address2.
|
||
| 493 | * @retval None.
|
||
| 494 | */
|
||
| 495 | void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address)
|
||
| 496 | {
|
||
| 497 | uint16_t tmpreg = 0;
|
||
| 498 | |||
| 499 | /* Check the parameters */
|
||
| 500 | assert_param(IS_I2C_ALL_PERIPH(I2Cx)); |
||
| 501 | |||
| 502 | /* Get the old register value */
|
||
| 503 | tmpreg = I2Cx->OAR2; |
||
| 504 | |||
| 505 | /* Reset I2Cx Own address2 bit [7:1] */
|
||
| 506 | tmpreg &= (uint16_t)~((uint16_t)I2C_OAR2_ADD2); |
||
| 507 | |||
| 508 | /* Set I2Cx Own address2 */
|
||
| 509 | tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE);
|
||
| 510 | |||
| 511 | /* Store the new register value */
|
||
| 512 | I2Cx->OAR2 = tmpreg; |
||
| 513 | } |
||
| 514 | |||
| 515 | /**
|
||
| 516 | * @brief Enables or disables the specified I2C dual addressing mode.
|
||
| 517 | * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
|
||
| 518 | * @param NewState: new state of the I2C dual addressing mode.
|
||
| 519 | * This parameter can be: ENABLE or DISABLE.
|
||
| 520 | * @retval None
|
||
| 521 | */
|
||
| 522 | void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
|
||
| 523 | {
|
||
| 524 | /* Check the parameters */
|
||
| 525 | assert_param(IS_I2C_ALL_PERIPH(I2Cx)); |
||
| 526 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
||
| 527 | if (NewState != DISABLE)
|
||
| 528 | {
|
||
| 529 | /* Enable dual addressing mode */
|
||
| 530 | I2Cx->OAR2 |= I2C_OAR2_ENDUAL; |
||
| 531 | } |
||
| 532 | else
|
||
| 533 | {
|
||
| 534 | /* Disable dual addressing mode */
|
||
| 535 | I2Cx->OAR2 &= (uint16_t)~((uint16_t)I2C_OAR2_ENDUAL); |
||
| 536 | } |
||
| 537 | } |
||
| 538 | |||
| 539 | /**
|
||
| 540 | * @brief Enables or disables the specified I2C general call feature.
|
||
| 541 | * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
|
||
| 542 | * @param NewState: new state of the I2C General call.
|
||
| 543 | * This parameter can be: ENABLE or DISABLE.
|
||
| 544 | * @retval None
|
||
| 545 | */
|
||
| 546 | void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
|
||
| 547 | {
|
||
| 548 | /* Check the parameters */
|
||
| 549 | assert_param(IS_I2C_ALL_PERIPH(I2Cx)); |
||
| 550 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
||
| 551 | if (NewState != DISABLE)
|
||
| 552 | {
|
||
| 553 | /* Enable generall call */
|
||
| 554 | I2Cx->CR1 |= I2C_CR1_ENGC; |
||
| 555 | } |
||
| 556 | else
|
||
| 557 | {
|
||
| 558 | /* Disable generall call */
|
||
| 559 | I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENGC); |
||
| 560 | } |
||
| 561 | } |
||
| 562 | |||
| 563 | /**
|
||
| 564 | * @brief Enables or disables the specified I2C software reset.
|
||
| 565 | * @note When software reset is enabled, the I2C IOs are released (this can
|
||
| 566 | * be useful to recover from bus errors).
|
||
| 567 | * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
|
||
| 568 | * @param NewState: new state of the I2C software reset.
|
||
| 569 | * This parameter can be: ENABLE or DISABLE.
|
||
| 570 | * @retval None
|
||
| 571 | */
|
||
| 572 | void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
|
||
| 573 | {
|
||
| 574 | /* Check the parameters */
|
||
| 575 | assert_param(IS_I2C_ALL_PERIPH(I2Cx)); |
||
| 576 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
||
| 577 | if (NewState != DISABLE)
|
||
| 578 | {
|
||
| 579 | /* Peripheral under reset */
|
||
| 580 | I2Cx->CR1 |= I2C_CR1_SWRST; |
||
| 581 | } |
||
| 582 | else
|
||
| 583 | {
|
||
| 584 | /* Peripheral not under reset */
|
||
| 585 | I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_SWRST); |
||
| 586 | } |
||
| 587 | } |
||
| 588 | |||
| 589 | /**
|
||
| 590 | * @brief Enables or disables the specified I2C Clock stretching.
|
||
| 591 | * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
|
||
| 592 | * @param NewState: new state of the I2Cx Clock stretching.
|
||
| 593 | * This parameter can be: ENABLE or DISABLE.
|
||
| 594 | * @retval None
|
||
| 595 | */
|
||
| 596 | void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
|
||
| 597 | {
|
||
| 598 | /* Check the parameters */
|
||
| 599 | assert_param(IS_I2C_ALL_PERIPH(I2Cx)); |
||
| 600 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
||
| 601 | if (NewState == DISABLE)
|
||
| 602 | {
|
||
| 603 | /* Enable the selected I2C Clock stretching */
|
||
| 604 | I2Cx->CR1 |= I2C_CR1_NOSTRETCH; |
||
| 605 | } |
||
| 606 | else
|
||
| 607 | {
|
||
| 608 | /* Disable the selected I2C Clock stretching */
|
||
| 609 | I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_NOSTRETCH); |
||
| 610 | } |
||
| 611 | } |
||
| 612 | |||
| 613 | /**
|
||
| 614 | * @brief Selects the specified I2C fast mode duty cycle.
|
||
| 615 | * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
|
||
| 616 | * @param I2C_DutyCycle: specifies the fast mode duty cycle.
|
||
| 617 | * This parameter can be one of the following values:
|
||
| 618 | * @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2
|
||
| 619 | * @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9
|
||
| 620 | * @retval None
|
||
| 621 | */
|
||
| 622 | void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle)
|
||
| 623 | {
|
||
| 624 | /* Check the parameters */
|
||
| 625 | assert_param(IS_I2C_ALL_PERIPH(I2Cx)); |
||
| 626 | assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle)); |
||
| 627 | if (I2C_DutyCycle != I2C_DutyCycle_16_9)
|
||
| 628 | {
|
||
| 629 | /* I2C fast mode Tlow/Thigh=2 */
|
||
| 630 | I2Cx->CCR &= I2C_DutyCycle_2; |
||
| 631 | } |
||
| 632 | else
|
||
| 633 | {
|
||
| 634 | /* I2C fast mode Tlow/Thigh=16/9 */
|
||
| 635 | I2Cx->CCR |= I2C_DutyCycle_16_9; |
||
| 636 | } |
||
| 637 | } |
||
| 638 | |||
| 639 | /**
|
||
| 640 | * @brief Selects the specified I2C NACK position in master receiver mode.
|
||
| 641 | * @note This function is useful in I2C Master Receiver mode when the number
|
||
| 642 | * of data to be received is equal to 2. In this case, this function
|
||
| 643 | * should be called (with parameter I2C_NACKPosition_Next) before data
|
||
| 644 | * reception starts,as described in the 2-byte reception procedure
|
||
| 645 | * recommended in Reference Manual in Section: Master receiver.
|
||
| 646 | * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
|
||
| 647 | * @param I2C_NACKPosition: specifies the NACK position.
|
||
| 648 | * This parameter can be one of the following values:
|
||
| 649 | * @arg I2C_NACKPosition_Next: indicates that the next byte will be the last
|
||
| 650 | * received byte.
|
||
| 651 | * @arg I2C_NACKPosition_Current: indicates that current byte is the last
|
||
| 652 | * received byte.
|
||
| 653 | *
|
||
| 654 | * @note This function configures the same bit (POS) as I2C_PECPositionConfig()
|
||
| 655 | * but is intended to be used in I2C mode while I2C_PECPositionConfig()
|
||
| 656 | * is intended to used in SMBUS mode.
|
||
| 657 | *
|
||
| 658 | * @retval None
|
||
| 659 | */
|
||
| 660 | void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition)
|
||
| 661 | {
|
||
| 662 | /* Check the parameters */
|
||
| 663 | assert_param(IS_I2C_ALL_PERIPH(I2Cx)); |
||
| 664 | assert_param(IS_I2C_NACK_POSITION(I2C_NACKPosition)); |
||
| 665 | |||
| 666 | /* Check the input parameter */
|
||
| 667 | if (I2C_NACKPosition == I2C_NACKPosition_Next)
|
||
| 668 | {
|
||
| 669 | /* Next byte in shift register is the last received byte */
|
||
| 670 | I2Cx->CR1 |= I2C_NACKPosition_Next; |
||
| 671 | } |
||
| 672 | else
|
||
| 673 | {
|
||
| 674 | /* Current byte in shift register is the last received byte */
|
||
| 675 | I2Cx->CR1 &= I2C_NACKPosition_Current; |
||
| 676 | } |
||
| 677 | } |
||
| 678 | |||
| 679 | /**
|
||
| 680 | * @brief Drives the SMBusAlert pin high or low for the specified I2C.
|
||
| 681 | * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
|
||
| 682 | * @param I2C_SMBusAlert: specifies SMBAlert pin level.
|
||
| 683 | * This parameter can be one of the following values:
|
||
| 684 | * @arg I2C_SMBusAlert_Low: SMBAlert pin driven low
|
||
| 685 | * @arg I2C_SMBusAlert_High: SMBAlert pin driven high
|
||
| 686 | * @retval None
|
||
| 687 | */
|
||
| 688 | void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert)
|
||
| 689 | {
|
||
| 690 | /* Check the parameters */
|
||
| 691 | assert_param(IS_I2C_ALL_PERIPH(I2Cx)); |
||
| 692 | assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert)); |
||
| 693 | if (I2C_SMBusAlert == I2C_SMBusAlert_Low)
|
||
| 694 | {
|
||
| 695 | /* Drive the SMBusAlert pin Low */
|
||
| 696 | I2Cx->CR1 |= I2C_SMBusAlert_Low; |
||
| 697 | } |
||
| 698 | else
|
||
| 699 | {
|
||
| 700 | /* Drive the SMBusAlert pin High */
|
||
| 701 | I2Cx->CR1 &= I2C_SMBusAlert_High; |
||
| 702 | } |
||
| 703 | } |
||
| 704 | |||
| 705 | /**
|
||
| 706 | * @brief Enables or disables the specified I2C ARP.
|
||
| 707 | * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
|
||
| 708 | * @param NewState: new state of the I2Cx ARP.
|
||
| 709 | * This parameter can be: ENABLE or DISABLE.
|
||
| 710 | * @retval None
|
||
| 711 | */
|
||
| 712 | void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
|
||
| 713 | {
|
||
| 714 | /* Check the parameters */
|
||
| 715 | assert_param(IS_I2C_ALL_PERIPH(I2Cx)); |
||
| 716 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
||
| 717 | if (NewState != DISABLE)
|
||
| 718 | {
|
||
| 719 | /* Enable the selected I2C ARP */
|
||
| 720 | I2Cx->CR1 |= I2C_CR1_ENARP; |
||
| 721 | } |
||
| 722 | else
|
||
| 723 | {
|
||
| 724 | /* Disable the selected I2C ARP */
|
||
| 725 | I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENARP); |
||
| 726 | } |
||
| 727 | } |
||
| 728 | /**
|
||
| 729 | * @}
|
||
| 730 | */
|
||
| 731 | |||
| 732 | /** @defgroup I2C_Group2 Data transfers functions
|
||
| 733 | * @brief Data transfers functions
|
||
| 734 | *
|
||
| 735 | @verbatim
|
||
| 736 | ===============================================================================
|
||
| 737 | ##### Data transfers functions #####
|
||
| 738 | ===============================================================================
|
||
| 739 | |||
| 740 | @endverbatim
|
||
| 741 | * @{
|
||
| 742 | */
|
||
| 743 | |||
| 744 | /**
|
||
| 745 | * @brief Sends a data byte through the I2Cx peripheral.
|
||
| 746 | * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
|
||
| 747 | * @param Data: Byte to be transmitted..
|
||
| 748 | * @retval None
|
||
| 749 | */
|
||
| 750 | void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data)
|
||
| 751 | {
|
||
| 752 | /* Check the parameters */
|
||
| 753 | assert_param(IS_I2C_ALL_PERIPH(I2Cx)); |
||
| 754 | /* Write in the DR register the data to be sent */
|
||
| 755 | I2Cx->DR = Data; |
||
| 756 | } |
||
| 757 | |||
| 758 | /**
|
||
| 759 | * @brief Returns the most recent received data by the I2Cx peripheral.
|
||
| 760 | * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
|
||
| 761 | * @retval The value of the received data.
|
||
| 762 | */
|
||
| 763 | uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx) |
||
| 764 | {
|
||
| 765 | /* Check the parameters */
|
||
| 766 | assert_param(IS_I2C_ALL_PERIPH(I2Cx)); |
||
| 767 | /* Return the data in the DR register */
|
||
| 768 | return (uint8_t)I2Cx->DR;
|
||
| 769 | } |
||
| 770 | |||
| 771 | /**
|
||
| 772 | * @}
|
||
| 773 | */
|
||
| 774 | |||
| 775 | /** @defgroup I2C_Group3 PEC management functions
|
||
| 776 | * @brief PEC management functions
|
||
| 777 | *
|
||
| 778 | @verbatim
|
||
| 779 | ===============================================================================
|
||
| 780 | ##### PEC management functions #####
|
||
| 781 | ===============================================================================
|
||
| 782 | |||
| 783 | @endverbatim
|
||
| 784 | * @{
|
||
| 785 | */
|
||
| 786 | |||
| 787 | /**
|
||
| 788 | * @brief Enables or disables the specified I2C PEC transfer.
|
||
| 789 | * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
|
||
| 790 | * @param NewState: new state of the I2C PEC transmission.
|
||
| 791 | * This parameter can be: ENABLE or DISABLE.
|
||
| 792 | * @retval None
|
||
| 793 | */
|
||
| 794 | void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
|
||
| 795 | {
|
||
| 796 | /* Check the parameters */
|
||
| 797 | assert_param(IS_I2C_ALL_PERIPH(I2Cx)); |
||
| 798 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
||
| 799 | if (NewState != DISABLE)
|
||
| 800 | {
|
||
| 801 | /* Enable the selected I2C PEC transmission */
|
||
| 802 | I2Cx->CR1 |= I2C_CR1_PEC; |
||
| 803 | } |
||
| 804 | else
|
||
| 805 | {
|
||
| 806 | /* Disable the selected I2C PEC transmission */
|
||
| 807 | I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PEC); |
||
| 808 | } |
||
| 809 | } |
||
| 810 | |||
| 811 | /**
|
||
| 812 | * @brief Selects the specified I2C PEC position.
|
||
| 813 | * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
|
||
| 814 | * @param I2C_PECPosition: specifies the PEC position.
|
||
| 815 | * This parameter can be one of the following values:
|
||
| 816 | * @arg I2C_PECPosition_Next: indicates that the next byte is PEC
|
||
| 817 | * @arg I2C_PECPosition_Current: indicates that current byte is PEC
|
||
| 818 | *
|
||
| 819 | * @note This function configures the same bit (POS) as I2C_NACKPositionConfig()
|
||
| 820 | * but is intended to be used in SMBUS mode while I2C_NACKPositionConfig()
|
||
| 821 | * is intended to used in I2C mode.
|
||
| 822 | *
|
||
| 823 | * @retval None
|
||
| 824 | */
|
||
| 825 | void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition)
|
||
| 826 | {
|
||
| 827 | /* Check the parameters */
|
||
| 828 | assert_param(IS_I2C_ALL_PERIPH(I2Cx)); |
||
| 829 | assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition)); |
||
| 830 | if (I2C_PECPosition == I2C_PECPosition_Next)
|
||
| 831 | {
|
||
| 832 | /* Next byte in shift register is PEC */
|
||
| 833 | I2Cx->CR1 |= I2C_PECPosition_Next; |
||
| 834 | } |
||
| 835 | else
|
||
| 836 | {
|
||
| 837 | /* Current byte in shift register is PEC */
|
||
| 838 | I2Cx->CR1 &= I2C_PECPosition_Current; |
||
| 839 | } |
||
| 840 | } |
||
| 841 | |||
| 842 | /**
|
||
| 843 | * @brief Enables or disables the PEC value calculation of the transferred bytes.
|
||
| 844 | * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
|
||
| 845 | * @param NewState: new state of the I2Cx PEC value calculation.
|
||
| 846 | * This parameter can be: ENABLE or DISABLE.
|
||
| 847 | * @retval None
|
||
| 848 | */
|
||
| 849 | void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
|
||
| 850 | {
|
||
| 851 | /* Check the parameters */
|
||
| 852 | assert_param(IS_I2C_ALL_PERIPH(I2Cx)); |
||
| 853 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
||
| 854 | if (NewState != DISABLE)
|
||
| 855 | {
|
||
| 856 | /* Enable the selected I2C PEC calculation */
|
||
| 857 | I2Cx->CR1 |= I2C_CR1_ENPEC; |
||
| 858 | } |
||
| 859 | else
|
||
| 860 | {
|
||
| 861 | /* Disable the selected I2C PEC calculation */
|
||
| 862 | I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENPEC); |
||
| 863 | } |
||
| 864 | } |
||
| 865 | |||
| 866 | /**
|
||
| 867 | * @brief Returns the PEC value for the specified I2C.
|
||
| 868 | * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
|
||
| 869 | * @retval The PEC value.
|
||
| 870 | */
|
||
| 871 | uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx) |
||
| 872 | {
|
||
| 873 | /* Check the parameters */
|
||
| 874 | assert_param(IS_I2C_ALL_PERIPH(I2Cx)); |
||
| 875 | /* Return the selected I2C PEC value */
|
||
| 876 | return ((I2Cx->SR2) >> 8); |
||
| 877 | } |
||
| 878 | |||
| 879 | /**
|
||
| 880 | * @}
|
||
| 881 | */
|
||
| 882 | |||
| 883 | /** @defgroup I2C_Group4 DMA transfers management functions
|
||
| 884 | * @brief DMA transfers management functions
|
||
| 885 | *
|
||
| 886 | @verbatim
|
||
| 887 | ===============================================================================
|
||
| 888 | ##### DMA transfers management functions #####
|
||
| 889 | ===============================================================================
|
||
| 890 | This section provides functions allowing to configure the I2C DMA channels
|
||
| 891 | requests.
|
||
| 892 |
|
||
| 893 | @endverbatim
|
||
| 894 | * @{
|
||
| 895 | */
|
||
| 896 | |||
| 897 | /**
|
||
| 898 | * @brief Enables or disables the specified I2C DMA requests.
|
||
| 899 | * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
|
||
| 900 | * @param NewState: new state of the I2C DMA transfer.
|
||
| 901 | * This parameter can be: ENABLE or DISABLE.
|
||
| 902 | * @retval None
|
||
| 903 | */
|
||
| 904 | void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
|
||
| 905 | {
|
||
| 906 | /* Check the parameters */
|
||
| 907 | assert_param(IS_I2C_ALL_PERIPH(I2Cx)); |
||
| 908 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
||
| 909 | if (NewState != DISABLE)
|
||
| 910 | {
|
||
| 911 | /* Enable the selected I2C DMA requests */
|
||
| 912 | I2Cx->CR2 |= I2C_CR2_DMAEN; |
||
| 913 | } |
||
| 914 | else
|
||
| 915 | {
|
||
| 916 | /* Disable the selected I2C DMA requests */
|
||
| 917 | I2Cx->CR2 &= (uint16_t)~((uint16_t)I2C_CR2_DMAEN); |
||
| 918 | } |
||
| 919 | } |
||
| 920 | |||
| 921 | /**
|
||
| 922 | * @brief Specifies that the next DMA transfer is the last one.
|
||
| 923 | * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
|
||
| 924 | * @param NewState: new state of the I2C DMA last transfer.
|
||
| 925 | * This parameter can be: ENABLE or DISABLE.
|
||
| 926 | * @retval None
|
||
| 927 | */
|
||
| 928 | void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
|
||
| 929 | {
|
||
| 930 | /* Check the parameters */
|
||
| 931 | assert_param(IS_I2C_ALL_PERIPH(I2Cx)); |
||
| 932 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
||
| 933 | if (NewState != DISABLE)
|
||
| 934 | {
|
||
| 935 | /* Next DMA transfer is the last transfer */
|
||
| 936 | I2Cx->CR2 |= I2C_CR2_LAST; |
||
| 937 | } |
||
| 938 | else
|
||
| 939 | {
|
||
| 940 | /* Next DMA transfer is not the last transfer */
|
||
| 941 | I2Cx->CR2 &= (uint16_t)~((uint16_t)I2C_CR2_LAST); |
||
| 942 | } |
||
| 943 | } |
||
| 944 | |||
| 945 | /**
|
||
| 946 | * @}
|
||
| 947 | */
|
||
| 948 | |||
| 949 | /** @defgroup I2C_Group5 Interrupts events and flags management functions
|
||
| 950 | * @brief Interrupts, events and flags management functions
|
||
| 951 | *
|
||
| 952 | @verbatim
|
||
| 953 | ===============================================================================
|
||
| 954 | ##### Interrupts, events and flags management functions #####
|
||
| 955 | ===============================================================================
|
||
| 956 | [..]
|
||
| 957 | This section provides functions allowing to configure the I2C Interrupts
|
||
| 958 | sources and check or clear the flags or pending bits status.
|
||
| 959 | The user should identify which mode will be used in his application to manage
|
||
| 960 | the communication: Polling mode, Interrupt mode or DMA mode.
|
||
| 961 | |||
| 962 | |||
| 963 | ##### I2C State Monitoring Functions #####
|
||
| 964 | ===============================================================================
|
||
| 965 | [..]
|
||
| 966 | This I2C driver provides three different ways for I2C state monitoring
|
||
| 967 | depending on the application requirements and constraints:
|
||
| 968 |
|
||
| 969 |
|
||
| 970 | (#) Basic state monitoring (Using I2C_CheckEvent() function)
|
||
| 971 |
|
||
| 972 | It compares the status registers (SR1 and SR2) content to a given event
|
||
| 973 | (can be the combination of one or more flags).
|
||
| 974 | It returns SUCCESS if the current status includes the given flags
|
||
| 975 | and returns ERROR if one or more flags are missing in the current status.
|
||
| 976 | |||
| 977 | (++) When to use
|
||
| 978 | (+++) This function is suitable for most applications as well as for startup
|
||
| 979 | activity since the events are fully described in the product reference
|
||
| 980 | manual (RM0090).
|
||
| 981 | (+++) It is also suitable for users who need to define their own events.
|
||
| 982 | |||
| 983 | (++) Limitations
|
||
| 984 | If an error occurs (ie. error flags are set besides to the monitored
|
||
| 985 | flags), the I2C_CheckEvent() function may return SUCCESS despite
|
||
| 986 | the communication hold or corrupted real state.
|
||
| 987 | In this case, it is advised to use error interrupts to monitor
|
||
| 988 | the error events and handle them in the interrupt IRQ handler.
|
||
| 989 |
|
||
| 990 | -@@- For error management, it is advised to use the following functions:
|
||
| 991 | (+@@) I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
|
||
| 992 | (+@@) I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
|
||
| 993 | Where x is the peripheral instance (I2C1, I2C2 ...)
|
||
| 994 | (+@@) I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the
|
||
| 995 | I2Cx_ER_IRQHandler() function in order to determine which error occurred.
|
||
| 996 | (+@@) I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
|
||
| 997 | and/or I2C_GenerateStop() in order to clear the error flag and source
|
||
| 998 | and return to correct communication status.
|
||
| 999 |
|
||
| 1000 |
|
||
| 1001 | (#) Advanced state monitoring (Using the function I2C_GetLastEvent())
|
||
| 1002 | |||
| 1003 | Using the function I2C_GetLastEvent() which returns the image of both status
|
||
| 1004 | registers in a single word (uint32_t) (Status Register 2 value is shifted left
|
||
| 1005 | by 16 bits and concatenated to Status Register 1).
|
||
| 1006 | |||
| 1007 | (++) When to use
|
||
| 1008 | (+++) This function is suitable for the same applications above but it
|
||
| 1009 | allows to overcome the mentioned limitation of I2C_GetFlagStatus()
|
||
| 1010 | function.
|
||
| 1011 | (+++) The returned value could be compared to events already defined in
|
||
| 1012 | the library (stm32f4xx_i2c.h) or to custom values defined by user.
|
||
| 1013 | This function is suitable when multiple flags are monitored at the
|
||
| 1014 | same time.
|
||
| 1015 | (+++) At the opposite of I2C_CheckEvent() function, this function allows
|
||
| 1016 | user to choose when an event is accepted (when all events flags are
|
||
| 1017 | set and no other flags are set or just when the needed flags are set
|
||
| 1018 | like I2C_CheckEvent() function.
|
||
| 1019 | |||
| 1020 | (++) Limitations
|
||
| 1021 | (+++) User may need to define his own events.
|
||
| 1022 | (+++) Same remark concerning the error management is applicable for this
|
||
| 1023 | function if user decides to check only regular communication flags
|
||
| 1024 | (and ignores error flags).
|
||
| 1025 |
|
||
| 1026 |
|
||
| 1027 | (#) Flag-based state monitoring (Using the function I2C_GetFlagStatus())
|
||
| 1028 |
|
||
| 1029 | Using the function I2C_GetFlagStatus() which simply returns the status of
|
||
| 1030 | one single flag (ie. I2C_FLAG_RXNE ...).
|
||
| 1031 | |||
| 1032 | (++) When to use
|
||
| 1033 | (+++) This function could be used for specific applications or in debug
|
||
| 1034 | phase.
|
||
| 1035 | (+++) It is suitable when only one flag checking is needed (most I2C
|
||
| 1036 | events are monitored through multiple flags).
|
||
| 1037 | (++) Limitations:
|
||
| 1038 | (+++) When calling this function, the Status register is accessed.
|
||
| 1039 | Some flags are cleared when the status register is accessed.
|
||
| 1040 | So checking the status of one Flag, may clear other ones.
|
||
| 1041 | (+++) Function may need to be called twice or more in order to monitor
|
||
| 1042 | one single event.
|
||
| 1043 |
|
||
| 1044 | For detailed description of Events, please refer to section I2C_Events in
|
||
| 1045 | stm32f4xx_i2c.h file.
|
||
| 1046 |
|
||
| 1047 | @endverbatim
|
||
| 1048 | * @{
|
||
| 1049 | */
|
||
| 1050 | |||
| 1051 | /**
|
||
| 1052 | * @brief Reads the specified I2C register and returns its value.
|
||
| 1053 | * @param I2C_Register: specifies the register to read.
|
||
| 1054 | * This parameter can be one of the following values:
|
||
| 1055 | * @arg I2C_Register_CR1: CR1 register.
|
||
| 1056 | * @arg I2C_Register_CR2: CR2 register.
|
||
| 1057 | * @arg I2C_Register_OAR1: OAR1 register.
|
||
| 1058 | * @arg I2C_Register_OAR2: OAR2 register.
|
||
| 1059 | * @arg I2C_Register_DR: DR register.
|
||
| 1060 | * @arg I2C_Register_SR1: SR1 register.
|
||
| 1061 | * @arg I2C_Register_SR2: SR2 register.
|
||
| 1062 | * @arg I2C_Register_CCR: CCR register.
|
||
| 1063 | * @arg I2C_Register_TRISE: TRISE register.
|
||
| 1064 | * @retval The value of the read register.
|
||
| 1065 | */
|
||
| 1066 | uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register) |
||
| 1067 | {
|
||
| 1068 | __IO uint32_t tmp = 0;
|
||
| 1069 | |||
| 1070 | /* Check the parameters */
|
||
| 1071 | assert_param(IS_I2C_ALL_PERIPH(I2Cx)); |
||
| 1072 | assert_param(IS_I2C_REGISTER(I2C_Register)); |
||
| 1073 | |||
| 1074 | tmp = (uint32_t) I2Cx; |
||
| 1075 | tmp += I2C_Register; |
||
| 1076 | |||
| 1077 | /* Return the selected register value */
|
||
| 1078 | return (*(__IO uint16_t *) tmp);
|
||
| 1079 | } |
||
| 1080 | |||
| 1081 | /**
|
||
| 1082 | * @brief Enables or disables the specified I2C interrupts.
|
||
| 1083 | * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
|
||
| 1084 | * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled.
|
||
| 1085 | * This parameter can be any combination of the following values:
|
||
| 1086 | * @arg I2C_IT_BUF: Buffer interrupt mask
|
||
| 1087 | * @arg I2C_IT_EVT: Event interrupt mask
|
||
| 1088 | * @arg I2C_IT_ERR: Error interrupt mask
|
||
| 1089 | * @param NewState: new state of the specified I2C interrupts.
|
||
| 1090 | * This parameter can be: ENABLE or DISABLE.
|
||
| 1091 | * @retval None
|
||
| 1092 | */
|
||
| 1093 | void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState)
|
||
| 1094 | {
|
||
| 1095 | /* Check the parameters */
|
||
| 1096 | assert_param(IS_I2C_ALL_PERIPH(I2Cx)); |
||
| 1097 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
||
| 1098 | assert_param(IS_I2C_CONFIG_IT(I2C_IT)); |
||
| 1099 | |||
| 1100 | if (NewState != DISABLE)
|
||
| 1101 | {
|
||
| 1102 | /* Enable the selected I2C interrupts */
|
||
| 1103 | I2Cx->CR2 |= I2C_IT; |
||
| 1104 | } |
||
| 1105 | else
|
||
| 1106 | {
|
||
| 1107 | /* Disable the selected I2C interrupts */
|
||
| 1108 | I2Cx->CR2 &= (uint16_t)~I2C_IT; |
||
| 1109 | } |
||
| 1110 | } |
||
| 1111 | |||
| 1112 | /*
|
||
| 1113 | ===============================================================================
|
||
| 1114 | 1. Basic state monitoring
|
||
| 1115 | ===============================================================================
|
||
| 1116 | */
|
||
| 1117 | |||
| 1118 | /**
|
||
| 1119 | * @brief Checks whether the last I2Cx Event is equal to the one passed
|
||
| 1120 | * as parameter.
|
||
| 1121 | * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
|
||
| 1122 | * @param I2C_EVENT: specifies the event to be checked.
|
||
| 1123 | * This parameter can be one of the following values:
|
||
| 1124 | * @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED: EV1
|
||
| 1125 | * @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED: EV1
|
||
| 1126 | * @arg I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED: EV1
|
||
| 1127 | * @arg I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED: EV1
|
||
| 1128 | * @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED: EV1
|
||
| 1129 | * @arg I2C_EVENT_SLAVE_BYTE_RECEIVED: EV2
|
||
| 1130 | * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF): EV2
|
||
| 1131 | * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL): EV2
|
||
| 1132 | * @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED: EV3
|
||
| 1133 | * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF): EV3
|
||
| 1134 | * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL): EV3
|
||
| 1135 | * @arg I2C_EVENT_SLAVE_ACK_FAILURE: EV3_2
|
||
| 1136 | * @arg I2C_EVENT_SLAVE_STOP_DETECTED: EV4
|
||
| 1137 | * @arg I2C_EVENT_MASTER_MODE_SELECT: EV5
|
||
| 1138 | * @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED: EV6
|
||
| 1139 | * @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED: EV6
|
||
| 1140 | * @arg I2C_EVENT_MASTER_BYTE_RECEIVED: EV7
|
||
| 1141 | * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING: EV8
|
||
| 1142 | * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED: EV8_2
|
||
| 1143 | * @arg I2C_EVENT_MASTER_MODE_ADDRESS10: EV9
|
||
| 1144 | *
|
||
| 1145 | * @note For detailed description of Events, please refer to section I2C_Events
|
||
| 1146 | * in stm32f4xx_i2c.h file.
|
||
| 1147 | *
|
||
| 1148 | * @retval An ErrorStatus enumeration value:
|
||
| 1149 | * - SUCCESS: Last event is equal to the I2C_EVENT
|
||
| 1150 | * - ERROR: Last event is different from the I2C_EVENT
|
||
| 1151 | */
|
||
| 1152 | ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT) |
||
| 1153 | {
|
||
| 1154 | uint32_t lastevent = 0;
|
||
| 1155 | uint32_t flag1 = 0, flag2 = 0; |
||
| 1156 | ErrorStatus status = ERROR; |
||
| 1157 | |||
| 1158 | /* Check the parameters */
|
||
| 1159 | assert_param(IS_I2C_ALL_PERIPH(I2Cx)); |
||
| 1160 | assert_param(IS_I2C_EVENT(I2C_EVENT)); |
||
| 1161 | |||
| 1162 | /* Read the I2Cx status register */
|
||
| 1163 | flag1 = I2Cx->SR1; |
||
| 1164 | flag2 = I2Cx->SR2; |
||
| 1165 | flag2 = flag2 << 16;
|
||
| 1166 | |||
| 1167 | /* Get the last event value from I2C status register */
|
||
| 1168 | lastevent = (flag1 | flag2) & FLAG_MASK; |
||
| 1169 | |||
| 1170 | /* Check whether the last event contains the I2C_EVENT */
|
||
| 1171 | if ((lastevent & I2C_EVENT) == I2C_EVENT)
|
||
| 1172 | {
|
||
| 1173 | /* SUCCESS: last event is equal to I2C_EVENT */
|
||
| 1174 | status = SUCCESS; |
||
| 1175 | } |
||
| 1176 | else
|
||
| 1177 | {
|
||
| 1178 | /* ERROR: last event is different from I2C_EVENT */
|
||
| 1179 | status = ERROR; |
||
| 1180 | } |
||
| 1181 | /* Return status */
|
||
| 1182 | return status;
|
||
| 1183 | } |
||
| 1184 | |||
| 1185 | /*
|
||
| 1186 | ===============================================================================
|
||
| 1187 | 2. Advanced state monitoring
|
||
| 1188 | ===============================================================================
|
||
| 1189 | */
|
||
| 1190 | |||
| 1191 | /**
|
||
| 1192 | * @brief Returns the last I2Cx Event.
|
||
| 1193 | * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
|
||
| 1194 | *
|
||
| 1195 | * @note For detailed description of Events, please refer to section I2C_Events
|
||
| 1196 | * in stm32f4xx_i2c.h file.
|
||
| 1197 | *
|
||
| 1198 | * @retval The last event
|
||
| 1199 | */
|
||
| 1200 | uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx) |
||
| 1201 | {
|
||
| 1202 | uint32_t lastevent = 0;
|
||
| 1203 | uint32_t flag1 = 0, flag2 = 0; |
||
| 1204 | |||
| 1205 | /* Check the parameters */
|
||
| 1206 | assert_param(IS_I2C_ALL_PERIPH(I2Cx)); |
||
| 1207 | |||
| 1208 | /* Read the I2Cx status register */
|
||
| 1209 | flag1 = I2Cx->SR1; |
||
| 1210 | flag2 = I2Cx->SR2; |
||
| 1211 | flag2 = flag2 << 16;
|
||
| 1212 | |||
| 1213 | /* Get the last event value from I2C status register */
|
||
| 1214 | lastevent = (flag1 | flag2) & FLAG_MASK; |
||
| 1215 | |||
| 1216 | /* Return status */
|
||
| 1217 | return lastevent;
|
||
| 1218 | } |
||
| 1219 | |||
| 1220 | /*
|
||
| 1221 | ===============================================================================
|
||
| 1222 | 3. Flag-based state monitoring
|
||
| 1223 | ===============================================================================
|
||
| 1224 | */
|
||
| 1225 | |||
| 1226 | /**
|
||
| 1227 | * @brief Checks whether the specified I2C flag is set or not.
|
||
| 1228 | * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
|
||
| 1229 | * @param I2C_FLAG: specifies the flag to check.
|
||
| 1230 | * This parameter can be one of the following values:
|
||
| 1231 | * @arg I2C_FLAG_DUALF: Dual flag (Slave mode)
|
||
| 1232 | * @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode)
|
||
| 1233 | * @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode)
|
||
| 1234 | * @arg I2C_FLAG_GENCALL: General call header flag (Slave mode)
|
||
| 1235 | * @arg I2C_FLAG_TRA: Transmitter/Receiver flag
|
||
| 1236 | * @arg I2C_FLAG_BUSY: Bus busy flag
|
||
| 1237 | * @arg I2C_FLAG_MSL: Master/Slave flag
|
||
| 1238 | * @arg I2C_FLAG_SMBALERT: SMBus Alert flag
|
||
| 1239 | * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
|
||
| 1240 | * @arg I2C_FLAG_PECERR: PEC error in reception flag
|
||
| 1241 | * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
|
||
| 1242 | * @arg I2C_FLAG_AF: Acknowledge failure flag
|
||
| 1243 | * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
|
||
| 1244 | * @arg I2C_FLAG_BERR: Bus error flag
|
||
| 1245 | * @arg I2C_FLAG_TXE: Data register empty flag (Transmitter)
|
||
| 1246 | * @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag
|
||
| 1247 | * @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode)
|
||
| 1248 | * @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode)
|
||
| 1249 | * @arg I2C_FLAG_BTF: Byte transfer finished flag
|
||
| 1250 | * @arg I2C_FLAG_ADDR: Address sent flag (Master mode) "ADSL"
|
||
| 1251 | * Address matched flag (Slave mode)"ENDAD"
|
||
| 1252 | * @arg I2C_FLAG_SB: Start bit flag (Master mode)
|
||
| 1253 | * @retval The new state of I2C_FLAG (SET or RESET).
|
||
| 1254 | */
|
||
| 1255 | FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) |
||
| 1256 | {
|
||
| 1257 | FlagStatus bitstatus = RESET; |
||
| 1258 | __IO uint32_t i2creg = 0, i2cxbase = 0; |
||
| 1259 | |||
| 1260 | /* Check the parameters */
|
||
| 1261 | assert_param(IS_I2C_ALL_PERIPH(I2Cx)); |
||
| 1262 | assert_param(IS_I2C_GET_FLAG(I2C_FLAG)); |
||
| 1263 | |||
| 1264 | /* Get the I2Cx peripheral base address */
|
||
| 1265 | i2cxbase = (uint32_t)I2Cx; |
||
| 1266 | |||
| 1267 | /* Read flag register index */
|
||
| 1268 | i2creg = I2C_FLAG >> 28;
|
||
| 1269 | |||
| 1270 | /* Get bit[23:0] of the flag */
|
||
| 1271 | I2C_FLAG &= FLAG_MASK; |
||
| 1272 | |||
| 1273 | if(i2creg != 0) |
||
| 1274 | {
|
||
| 1275 | /* Get the I2Cx SR1 register address */
|
||
| 1276 | i2cxbase += 0x14;
|
||
| 1277 | } |
||
| 1278 | else
|
||
| 1279 | {
|
||
| 1280 | /* Flag in I2Cx SR2 Register */
|
||
| 1281 | I2C_FLAG = (uint32_t)(I2C_FLAG >> 16);
|
||
| 1282 | /* Get the I2Cx SR2 register address */
|
||
| 1283 | i2cxbase += 0x18;
|
||
| 1284 | } |
||
| 1285 | |||
| 1286 | if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET)
|
||
| 1287 | {
|
||
| 1288 | /* I2C_FLAG is set */
|
||
| 1289 | bitstatus = SET; |
||
| 1290 | } |
||
| 1291 | else
|
||
| 1292 | {
|
||
| 1293 | /* I2C_FLAG is reset */
|
||
| 1294 | bitstatus = RESET; |
||
| 1295 | } |
||
| 1296 | |||
| 1297 | /* Return the I2C_FLAG status */
|
||
| 1298 | return bitstatus;
|
||
| 1299 | } |
||
| 1300 | |||
| 1301 | /**
|
||
| 1302 | * @brief Clears the I2Cx's pending flags.
|
||
| 1303 | * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
|
||
| 1304 | * @param I2C_FLAG: specifies the flag to clear.
|
||
| 1305 | * This parameter can be any combination of the following values:
|
||
| 1306 | * @arg I2C_FLAG_SMBALERT: SMBus Alert flag
|
||
| 1307 | * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
|
||
| 1308 | * @arg I2C_FLAG_PECERR: PEC error in reception flag
|
||
| 1309 | * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
|
||
| 1310 | * @arg I2C_FLAG_AF: Acknowledge failure flag
|
||
| 1311 | * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
|
||
| 1312 | * @arg I2C_FLAG_BERR: Bus error flag
|
||
| 1313 | *
|
||
| 1314 | * @note STOPF (STOP detection) is cleared by software sequence: a read operation
|
||
| 1315 | * to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation
|
||
| 1316 | * to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).
|
||
| 1317 | * @note ADD10 (10-bit header sent) is cleared by software sequence: a read
|
||
| 1318 | * operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the
|
||
| 1319 | * second byte of the address in DR register.
|
||
| 1320 | * @note BTF (Byte Transfer Finished) is cleared by software sequence: a read
|
||
| 1321 | * operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a
|
||
| 1322 | * read/write to I2C_DR register (I2C_SendData()).
|
||
| 1323 | * @note ADDR (Address sent) is cleared by software sequence: a read operation to
|
||
| 1324 | * I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to
|
||
| 1325 | * I2C_SR2 register ((void)(I2Cx->SR2)).
|
||
| 1326 | * @note SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1
|
||
| 1327 | * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR
|
||
| 1328 | * register (I2C_SendData()).
|
||
| 1329 | *
|
||
| 1330 | * @retval None
|
||
| 1331 | */
|
||
| 1332 | void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
|
||
| 1333 | {
|
||
| 1334 | uint32_t flagpos = 0;
|
||
| 1335 | /* Check the parameters */
|
||
| 1336 | assert_param(IS_I2C_ALL_PERIPH(I2Cx)); |
||
| 1337 | assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG)); |
||
| 1338 | /* Get the I2C flag position */
|
||
| 1339 | flagpos = I2C_FLAG & FLAG_MASK; |
||
| 1340 | /* Clear the selected I2C flag */
|
||
| 1341 | I2Cx->SR1 = (uint16_t)~flagpos; |
||
| 1342 | } |
||
| 1343 | |||
| 1344 | /**
|
||
| 1345 | * @brief Checks whether the specified I2C interrupt has occurred or not.
|
||
| 1346 | * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
|
||
| 1347 | * @param I2C_IT: specifies the interrupt source to check.
|
||
| 1348 | * This parameter can be one of the following values:
|
||
| 1349 | * @arg I2C_IT_SMBALERT: SMBus Alert flag
|
||
| 1350 | * @arg I2C_IT_TIMEOUT: Timeout or Tlow error flag
|
||
| 1351 | * @arg I2C_IT_PECERR: PEC error in reception flag
|
||
| 1352 | * @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode)
|
||
| 1353 | * @arg I2C_IT_AF: Acknowledge failure flag
|
||
| 1354 | * @arg I2C_IT_ARLO: Arbitration lost flag (Master mode)
|
||
| 1355 | * @arg I2C_IT_BERR: Bus error flag
|
||
| 1356 | * @arg I2C_IT_TXE: Data register empty flag (Transmitter)
|
||
| 1357 | * @arg I2C_IT_RXNE: Data register not empty (Receiver) flag
|
||
| 1358 | * @arg I2C_IT_STOPF: Stop detection flag (Slave mode)
|
||
| 1359 | * @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode)
|
||
| 1360 | * @arg I2C_IT_BTF: Byte transfer finished flag
|
||
| 1361 | * @arg I2C_IT_ADDR: Address sent flag (Master mode) "ADSL"
|
||
| 1362 | * Address matched flag (Slave mode)"ENDAD"
|
||
| 1363 | * @arg I2C_IT_SB: Start bit flag (Master mode)
|
||
| 1364 | * @retval The new state of I2C_IT (SET or RESET).
|
||
| 1365 | */
|
||
| 1366 | ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT) |
||
| 1367 | {
|
||
| 1368 | ITStatus bitstatus = RESET; |
||
| 1369 | uint32_t enablestatus = 0;
|
||
| 1370 | |||
| 1371 | /* Check the parameters */
|
||
| 1372 | assert_param(IS_I2C_ALL_PERIPH(I2Cx)); |
||
| 1373 | assert_param(IS_I2C_GET_IT(I2C_IT)); |
||
| 1374 | |||
| 1375 | /* Check if the interrupt source is enabled or not */
|
||
| 1376 | enablestatus = (uint32_t)(((I2C_IT & ITEN_MASK) >> 16) & (I2Cx->CR2)) ;
|
||
| 1377 | |||
| 1378 | /* Get bit[23:0] of the flag */
|
||
| 1379 | I2C_IT &= FLAG_MASK; |
||
| 1380 | |||
| 1381 | /* Check the status of the specified I2C flag */
|
||
| 1382 | if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus)
|
||
| 1383 | {
|
||
| 1384 | /* I2C_IT is set */
|
||
| 1385 | bitstatus = SET; |
||
| 1386 | } |
||
| 1387 | else
|
||
| 1388 | {
|
||
| 1389 | /* I2C_IT is reset */
|
||
| 1390 | bitstatus = RESET; |
||
| 1391 | } |
||
| 1392 | /* Return the I2C_IT status */
|
||
| 1393 | return bitstatus;
|
||
| 1394 | } |
||
| 1395 | |||
| 1396 | /**
|
||
| 1397 | * @brief Clears the I2Cx's interrupt pending bits.
|
||
| 1398 | * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
|
||
| 1399 | * @param I2C_IT: specifies the interrupt pending bit to clear.
|
||
| 1400 | * This parameter can be any combination of the following values:
|
||
| 1401 | * @arg I2C_IT_SMBALERT: SMBus Alert interrupt
|
||
| 1402 | * @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt
|
||
| 1403 | * @arg I2C_IT_PECERR: PEC error in reception interrupt
|
||
| 1404 | * @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode)
|
||
| 1405 | * @arg I2C_IT_AF: Acknowledge failure interrupt
|
||
| 1406 | * @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode)
|
||
| 1407 | * @arg I2C_IT_BERR: Bus error interrupt
|
||
| 1408 | *
|
||
| 1409 | * @note STOPF (STOP detection) is cleared by software sequence: a read operation
|
||
| 1410 | * to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to
|
||
| 1411 | * I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).
|
||
| 1412 | * @note ADD10 (10-bit header sent) is cleared by software sequence: a read
|
||
| 1413 | * operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second
|
||
| 1414 | * byte of the address in I2C_DR register.
|
||
| 1415 | * @note BTF (Byte Transfer Finished) is cleared by software sequence: a read
|
||
| 1416 | * operation to I2C_SR1 register (I2C_GetITStatus()) followed by a
|
||
| 1417 | * read/write to I2C_DR register (I2C_SendData()).
|
||
| 1418 | * @note ADDR (Address sent) is cleared by software sequence: a read operation to
|
||
| 1419 | * I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to
|
||
| 1420 | * I2C_SR2 register ((void)(I2Cx->SR2)).
|
||
| 1421 | * @note SB (Start Bit) is cleared by software sequence: a read operation to
|
||
| 1422 | * I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to
|
||
| 1423 | * I2C_DR register (I2C_SendData()).
|
||
| 1424 | * @retval None
|
||
| 1425 | */
|
||
| 1426 | void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
|
||
| 1427 | {
|
||
| 1428 | uint32_t flagpos = 0;
|
||
| 1429 | /* Check the parameters */
|
||
| 1430 | assert_param(IS_I2C_ALL_PERIPH(I2Cx)); |
||
| 1431 | assert_param(IS_I2C_CLEAR_IT(I2C_IT)); |
||
| 1432 | |||
| 1433 | /* Get the I2C flag position */
|
||
| 1434 | flagpos = I2C_IT & FLAG_MASK; |
||
| 1435 | |||
| 1436 | /* Clear the selected I2C flag */
|
||
| 1437 | I2Cx->SR1 = (uint16_t)~flagpos; |
||
| 1438 | } |
||
| 1439 | |||
| 1440 | /**
|
||
| 1441 | * @}
|
||
| 1442 | */
|
||
| 1443 | |||
| 1444 | /**
|
||
| 1445 | * @}
|
||
| 1446 | */
|
||
| 1447 | |||
| 1448 | /**
|
||
| 1449 | * @}
|
||
| 1450 | */
|
||
| 1451 | |||
| 1452 | /**
|
||
| 1453 | * @}
|
||
| 1454 | */
|
||
| 1455 | |||
| 1456 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|