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/**************************************************************************//**
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 * @file     core_cm3.h
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 * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
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 * @version  V1.30
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 * @date     30. October 2009
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 *
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 * @note
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 * Copyright (C) 2009 ARM Limited. All rights reserved.
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 *
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 * @par
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 * ARM Limited (ARM) is supplying this software for use with Cortex-M 
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 * processor based microcontrollers.  This file can be freely distributed 
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 * within development tools that are supporting such ARM based processors. 
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 *
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 * @par
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 * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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 *
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 ******************************************************************************/
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#ifndef __CM3_CORE_H__
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#define __CM3_CORE_H__
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/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration
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 *
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 * List of Lint messages which will be suppressed and not shown:
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 *   - Error 10: \n
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 *     register uint32_t __regBasePri         __asm("basepri"); \n
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 *     Error 10: Expecting ';'
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 * .
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 *   - Error 530: \n
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 *     return(__regBasePri); \n
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 *     Warning 530: Symbol '__regBasePri' (line 264) not initialized
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 * . 
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 *   - Error 550: \n
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 *     __regBasePri = (basePri & 0x1ff); \n
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 *     Warning 550: Symbol '__regBasePri' (line 271) not accessed
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 * .
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 *   - Error 754: \n
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 *     uint32_t RESERVED0[24]; \n
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 *     Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced
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 * .
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 *   - Error 750: \n
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 *     #define __CM3_CORE_H__ \n
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 *     Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced
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 * .
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 *   - Error 528: \n
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 *     static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
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 *     Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced
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 * .
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 *   - Error 751: \n
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 *     } InterruptType_Type; \n
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 *     Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced
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 * .
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 * Note:  To re-enable a Message, insert a space before 'lint' *
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 *
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 */
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/*lint -save */
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/*lint -e10  */
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/*lint -e530 */
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/*lint -e550 */
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/*lint -e754 */
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/*lint -e750 */
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/*lint -e528 */
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/*lint -e751 */
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/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions
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  This file defines all structures and symbols for CMSIS core:
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    - CMSIS version number
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    - Cortex-M core registers and bitfields
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    - Cortex-M core peripheral base address
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  @{
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 */
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#ifdef __cplusplus
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 extern "C" {
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#endif 
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#define __CM3_CMSIS_VERSION_MAIN  (0x01)                                                       /*!< [31:16] CMSIS HAL main version */
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#define __CM3_CMSIS_VERSION_SUB   (0x30)                                                       /*!< [15:0]  CMSIS HAL sub version  */
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#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number       */
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#define __CORTEX_M                (0x03)                                                       /*!< Cortex core                    */
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#include <stdint.h>                           /* Include standard types */
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#if defined (__ICCARM__)
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  #include <intrinsics.h>                     /* IAR Intrinsics   */
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#endif
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#ifndef __NVIC_PRIO_BITS
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  #define __NVIC_PRIO_BITS    4               /*!< standard definition for NVIC Priority Bits */
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#endif
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/**
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 * IO definitions
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 *
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 * define access restrictions to peripheral registers
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 */
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#ifdef __cplusplus
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  #define     __I     volatile                /*!< defines 'read only' permissions      */
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#else
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  #define     __I     volatile const          /*!< defines 'read only' permissions      */
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#endif
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#define     __O     volatile                  /*!< defines 'write only' permissions     */
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#define     __IO    volatile                  /*!< defines 'read / write' permissions   */
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/*******************************************************************************
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 *                 Register Abstraction
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 ******************************************************************************/
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/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register
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 @{
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*/
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/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC
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  memory mapped structure for Nested Vectored Interrupt Controller (NVIC)
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  @{
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 */
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typedef struct
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{
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  __IO uint32_t ISER[8];                      /*!< Offset: 0x000  Interrupt Set Enable Register           */
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       uint32_t RESERVED0[24];                                   
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  __IO uint32_t ICER[8];                      /*!< Offset: 0x080  Interrupt Clear Enable Register         */
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       uint32_t RSERVED1[24];                                    
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  __IO uint32_t ISPR[8];                      /*!< Offset: 0x100  Interrupt Set Pending Register          */
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       uint32_t RESERVED2[24];                                   
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  __IO uint32_t ICPR[8];                      /*!< Offset: 0x180  Interrupt Clear Pending Register        */
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       uint32_t RESERVED3[24];                                   
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  __IO uint32_t IABR[8];                      /*!< Offset: 0x200  Interrupt Active bit Register           */
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       uint32_t RESERVED4[56];                                   
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  __IO uint8_t  IP[240];                      /*!< Offset: 0x300  Interrupt Priority Register (8Bit wide) */
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       uint32_t RESERVED5[644];                                  
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  __O  uint32_t STIR;                         /*!< Offset: 0xE00  Software Trigger Interrupt Register     */
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}  NVIC_Type;                                               
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/*@}*/ /* end of group CMSIS_CM3_NVIC */
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/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB
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  memory mapped structure for System Control Block (SCB)
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  @{
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 */
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typedef struct
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{
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  __I  uint32_t CPUID;                        /*!< Offset: 0x00  CPU ID Base Register                                  */
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  __IO uint32_t ICSR;                         /*!< Offset: 0x04  Interrupt Control State Register                      */
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  __IO uint32_t VTOR;                         /*!< Offset: 0x08  Vector Table Offset Register                          */
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  __IO uint32_t AIRCR;                        /*!< Offset: 0x0C  Application Interrupt / Reset Control Register        */
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  __IO uint32_t SCR;                          /*!< Offset: 0x10  System Control Register                               */
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  __IO uint32_t CCR;                          /*!< Offset: 0x14  Configuration Control Register                        */
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  __IO uint8_t  SHP[12];                      /*!< Offset: 0x18  System Handlers Priority Registers (4-7, 8-11, 12-15) */
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  __IO uint32_t SHCSR;                        /*!< Offset: 0x24  System Handler Control and State Register             */
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  __IO uint32_t CFSR;                         /*!< Offset: 0x28  Configurable Fault Status Register                    */
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  __IO uint32_t HFSR;                         /*!< Offset: 0x2C  Hard Fault Status Register                            */
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  __IO uint32_t DFSR;                         /*!< Offset: 0x30  Debug Fault Status Register                           */
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  __IO uint32_t MMFAR;                        /*!< Offset: 0x34  Mem Manage Address Register                           */
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  __IO uint32_t BFAR;                         /*!< Offset: 0x38  Bus Fault Address Register                            */
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  __IO uint32_t AFSR;                         /*!< Offset: 0x3C  Auxiliary Fault Status Register                       */
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  __I  uint32_t PFR[2];                       /*!< Offset: 0x40  Processor Feature Register                            */
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  __I  uint32_t DFR;                          /*!< Offset: 0x48  Debug Feature Register                                */
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  __I  uint32_t ADR;                          /*!< Offset: 0x4C  Auxiliary Feature Register                            */
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  __I  uint32_t MMFR[4];                      /*!< Offset: 0x50  Memory Model Feature Register                         */
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  __I  uint32_t ISAR[5];                      /*!< Offset: 0x60  ISA Feature Register                                  */
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} SCB_Type;                                                
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/* SCB CPUID Register Definitions */
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#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
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#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFul << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
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#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
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#define SCB_CPUID_VARIANT_Msk              (0xFul << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
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#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
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#define SCB_CPUID_PARTNO_Msk               (0xFFFul << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
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#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
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#define SCB_CPUID_REVISION_Msk             (0xFul << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
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/* SCB Interrupt Control State Register Definitions */
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#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
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#define SCB_ICSR_NMIPENDSET_Msk            (1ul << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
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#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
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#define SCB_ICSR_PENDSVSET_Msk             (1ul << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
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#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
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#define SCB_ICSR_PENDSVCLR_Msk             (1ul << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
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#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
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#define SCB_ICSR_PENDSTSET_Msk             (1ul << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
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#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
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#define SCB_ICSR_PENDSTCLR_Msk             (1ul << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
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#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
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#define SCB_ICSR_ISRPREEMPT_Msk            (1ul << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
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#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
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#define SCB_ICSR_ISRPENDING_Msk            (1ul << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
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#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
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#define SCB_ICSR_VECTPENDING_Msk           (0x1FFul << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
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#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
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#define SCB_ICSR_RETTOBASE_Msk             (1ul << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
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#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
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#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFul << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
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/* SCB Interrupt Control State Register Definitions */
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#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
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#define SCB_VTOR_TBLBASE_Msk               (0x1FFul << SCB_VTOR_TBLBASE_Pos)              /*!< SCB VTOR: TBLBASE Mask */
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#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
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#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
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/* SCB Application Interrupt and Reset Control Register Definitions */
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#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
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#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFul << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
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#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
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#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
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#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
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#define SCB_AIRCR_ENDIANESS_Msk            (1ul << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
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#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
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#define SCB_AIRCR_PRIGROUP_Msk             (7ul << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
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#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
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#define SCB_AIRCR_SYSRESETREQ_Msk          (1ul << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
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#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
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#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
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#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
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#define SCB_AIRCR_VECTRESET_Msk            (1ul << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
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/* SCB System Control Register Definitions */
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#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
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#define SCB_SCR_SEVONPEND_Msk              (1ul << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
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#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
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#define SCB_SCR_SLEEPDEEP_Msk              (1ul << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
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#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
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#define SCB_SCR_SLEEPONEXIT_Msk            (1ul << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
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/* SCB Configuration Control Register Definitions */
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#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
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#define SCB_CCR_STKALIGN_Msk               (1ul << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
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#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
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#define SCB_CCR_BFHFNMIGN_Msk              (1ul << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
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#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
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#define SCB_CCR_DIV_0_TRP_Msk              (1ul << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
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#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
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#define SCB_CCR_UNALIGN_TRP_Msk            (1ul << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
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#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
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#define SCB_CCR_USERSETMPEND_Msk           (1ul << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
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#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
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#define SCB_CCR_NONBASETHRDENA_Msk         (1ul << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
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/* SCB System Handler Control and State Register Definitions */
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#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
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#define SCB_SHCSR_USGFAULTENA_Msk          (1ul << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
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#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
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#define SCB_SHCSR_BUSFAULTENA_Msk          (1ul << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
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#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
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#define SCB_SHCSR_MEMFAULTENA_Msk          (1ul << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
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#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
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#define SCB_SHCSR_SVCALLPENDED_Msk         (1ul << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
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#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
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