amiro-blt / Target / Demo / ARMCM3_STM32F103_DiWheelDrive_GCC / Boot / lib / STM32F10x_StdPeriph_Driver / inc / stm32f10x_tim.h @ 69661903
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/**
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******************************************************************************
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* @file stm32f10x_tim.h
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* @author MCD Application Team
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* @version V3.5.0
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* @date 11-March-2011
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* @brief This file contains all the functions prototypes for the TIM firmware
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* library.
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******************************************************************************
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* @attention
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*
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*
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* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32F10x_TIM_H
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#define __STM32F10x_TIM_H
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#ifdef __cplusplus
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extern "C" { |
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f10x.h" |
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/** @addtogroup STM32F10x_StdPeriph_Driver
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* @{
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*/
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/** @addtogroup TIM
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* @{
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*/
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/** @defgroup TIM_Exported_Types
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* @{
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*/
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/**
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* @brief TIM Time Base Init structure definition
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* @note This structure is used with all TIMx except for TIM6 and TIM7.
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*/
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typedef struct |
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{ |
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uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
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This parameter can be a number between 0x0000 and 0xFFFF */
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uint16_t TIM_CounterMode; /*!< Specifies the counter mode.
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This parameter can be a value of @ref TIM_Counter_Mode */
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uint16_t TIM_Period; /*!< Specifies the period value to be loaded into the active
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Auto-Reload Register at the next update event.
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This parameter must be a number between 0x0000 and 0xFFFF. */
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uint16_t TIM_ClockDivision; /*!< Specifies the clock division.
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This parameter can be a value of @ref TIM_Clock_Division_CKD */
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uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
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reaches zero, an update event is generated and counting restarts
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from the RCR value (N).
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This means in PWM mode that (N+1) corresponds to:
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- the number of PWM periods in edge-aligned mode
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- the number of half PWM period in center-aligned mode
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This parameter must be a number between 0x00 and 0xFF.
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@note This parameter is valid only for TIM1 and TIM8. */
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} TIM_TimeBaseInitTypeDef; |
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/**
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* @brief TIM Output Compare Init structure definition
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*/
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typedef struct |
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{ |
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uint16_t TIM_OCMode; /*!< Specifies the TIM mode.
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This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
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uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state.
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This parameter can be a value of @ref TIM_Output_Compare_state */
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uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state.
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This parameter can be a value of @ref TIM_Output_Compare_N_state
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@note This parameter is valid only for TIM1 and TIM8. */
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uint16_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
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This parameter can be a number between 0x0000 and 0xFFFF */
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uint16_t TIM_OCPolarity; /*!< Specifies the output polarity.
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This parameter can be a value of @ref TIM_Output_Compare_Polarity */
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uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity.
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This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
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@note This parameter is valid only for TIM1 and TIM8. */
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uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
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This parameter can be a value of @ref TIM_Output_Compare_Idle_State
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@note This parameter is valid only for TIM1 and TIM8. */
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uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
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This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
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@note This parameter is valid only for TIM1 and TIM8. */
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} TIM_OCInitTypeDef; |
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/**
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* @brief TIM Input Capture Init structure definition
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*/
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typedef struct |
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{ |
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uint16_t TIM_Channel; /*!< Specifies the TIM channel.
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This parameter can be a value of @ref TIM_Channel */
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uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal.
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This parameter can be a value of @ref TIM_Input_Capture_Polarity */
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uint16_t TIM_ICSelection; /*!< Specifies the input.
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This parameter can be a value of @ref TIM_Input_Capture_Selection */
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uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler.
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This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
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uint16_t TIM_ICFilter; /*!< Specifies the input capture filter.
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This parameter can be a number between 0x0 and 0xF */
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} TIM_ICInitTypeDef; |
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/**
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* @brief BDTR structure definition
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* @note This structure is used only with TIM1 and TIM8.
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*/
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typedef struct |
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{ |
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uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode.
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This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */
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uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state.
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This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */
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uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters.
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This parameter can be a value of @ref Lock_level */
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uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the
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switching-on of the outputs.
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This parameter can be a number between 0x00 and 0xFF */
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uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not.
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This parameter can be a value of @ref Break_Input_enable_disable */
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uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
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This parameter can be a value of @ref Break_Polarity */
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uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
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This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
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} TIM_BDTRInitTypeDef; |
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/** @defgroup TIM_Exported_constants
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* @{
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*/
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#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
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((PERIPH) == TIM2) || \ |
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((PERIPH) == TIM3) || \ |
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((PERIPH) == TIM4) || \ |
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((PERIPH) == TIM5) || \ |
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((PERIPH) == TIM6) || \ |
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((PERIPH) == TIM7) || \ |
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((PERIPH) == TIM8) || \ |
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((PERIPH) == TIM9) || \ |
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((PERIPH) == TIM10)|| \ |
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((PERIPH) == TIM11)|| \ |
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((PERIPH) == TIM12)|| \ |
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((PERIPH) == TIM13)|| \ |
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((PERIPH) == TIM14)|| \ |
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((PERIPH) == TIM15)|| \ |
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((PERIPH) == TIM16)|| \ |
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((PERIPH) == TIM17)) |
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/* LIST1: TIM 1 and 8 */
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#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
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((PERIPH) == TIM8)) |
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/* LIST2: TIM 1, 8, 15 16 and 17 */
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#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
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((PERIPH) == TIM8) || \ |
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((PERIPH) == TIM15)|| \ |
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((PERIPH) == TIM16)|| \ |
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((PERIPH) == TIM17)) |
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/* LIST3: TIM 1, 2, 3, 4, 5 and 8 */
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#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
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((PERIPH) == TIM2) || \ |
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((PERIPH) == TIM3) || \ |
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((PERIPH) == TIM4) || \ |
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((PERIPH) == TIM5) || \ |
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((PERIPH) == TIM8)) |
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/* LIST4: TIM 1, 2, 3, 4, 5, 8, 15, 16 and 17 */
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#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
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((PERIPH) == TIM2) || \ |
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((PERIPH) == TIM3) || \ |
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((PERIPH) == TIM4) || \ |
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((PERIPH) == TIM5) || \ |
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((PERIPH) == TIM8) || \ |
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((PERIPH) == TIM15)|| \ |
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((PERIPH) == TIM16)|| \ |
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((PERIPH) == TIM17)) |
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/* LIST5: TIM 1, 2, 3, 4, 5, 8 and 15 */
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#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
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((PERIPH) == TIM2) || \ |
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((PERIPH) == TIM3) || \ |
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((PERIPH) == TIM4) || \ |
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((PERIPH) == TIM5) || \ |
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((PERIPH) == TIM8) || \ |
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((PERIPH) == TIM15)) |
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/* LIST6: TIM 1, 2, 3, 4, 5, 8, 9, 12 and 15 */
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#define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
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((PERIPH) == TIM2) || \ |
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((PERIPH) == TIM3) || \ |
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((PERIPH) == TIM4) || \ |
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((PERIPH) == TIM5) || \ |
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((PERIPH) == TIM8) || \ |
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((PERIPH) == TIM9) || \ |
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((PERIPH) == TIM12)|| \ |
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((PERIPH) == TIM15)) |
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/* LIST7: TIM 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 and 15 */
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#define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
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((PERIPH) == TIM2) || \ |
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((PERIPH) == TIM3) || \ |
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((PERIPH) == TIM4) || \ |
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((PERIPH) == TIM5) || \ |
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((PERIPH) == TIM6) || \ |
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((PERIPH) == TIM7) || \ |
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((PERIPH) == TIM8) || \ |
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((PERIPH) == TIM9) || \ |
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((PERIPH) == TIM12)|| \ |
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((PERIPH) == TIM15)) |
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/* LIST8: TIM 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 15, 16 and 17 */
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#define IS_TIM_LIST8_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
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((PERIPH) == TIM2) || \ |
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((PERIPH) == TIM3) || \ |
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((PERIPH) == TIM4) || \ |
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((PERIPH) == TIM5) || \ |
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((PERIPH) == TIM8) || \ |
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((PERIPH) == TIM9) || \ |
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((PERIPH) == TIM10)|| \ |
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((PERIPH) == TIM11)|| \ |
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((PERIPH) == TIM12)|| \ |
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((PERIPH) == TIM13)|| \ |
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((PERIPH) == TIM14)|| \ |
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((PERIPH) == TIM15)|| \ |
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((PERIPH) == TIM16)|| \ |
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((PERIPH) == TIM17)) |
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/* LIST9: TIM 1, 2, 3, 4, 5, 6, 7, 8, 15, 16, and 17 */
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#define IS_TIM_LIST9_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
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((PERIPH) == TIM2) || \ |
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((PERIPH) == TIM3) || \ |
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((PERIPH) == TIM4) || \ |
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((PERIPH) == TIM5) || \ |
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((PERIPH) == TIM6) || \ |
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((PERIPH) == TIM7) || \ |
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((PERIPH) == TIM8) || \ |
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((PERIPH) == TIM15)|| \ |
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((PERIPH) == TIM16)|| \ |
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((PERIPH) == TIM17)) |
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/**
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* @}
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*/
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/** @defgroup TIM_Output_Compare_and_PWM_modes
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* @{
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*/
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#define TIM_OCMode_Timing ((uint16_t)0x0000) |
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#define TIM_OCMode_Active ((uint16_t)0x0010) |
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#define TIM_OCMode_Inactive ((uint16_t)0x0020) |
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#define TIM_OCMode_Toggle ((uint16_t)0x0030) |
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#define TIM_OCMode_PWM1 ((uint16_t)0x0060) |
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#define TIM_OCMode_PWM2 ((uint16_t)0x0070) |
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#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \
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((MODE) == TIM_OCMode_Active) || \ |
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((MODE) == TIM_OCMode_Inactive) || \ |
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((MODE) == TIM_OCMode_Toggle)|| \ |
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((MODE) == TIM_OCMode_PWM1) || \ |
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((MODE) == TIM_OCMode_PWM2)) |
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#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \
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((MODE) == TIM_OCMode_Active) || \ |
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((MODE) == TIM_OCMode_Inactive) || \ |
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((MODE) == TIM_OCMode_Toggle)|| \ |
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((MODE) == TIM_OCMode_PWM1) || \ |
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((MODE) == TIM_OCMode_PWM2) || \ |
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((MODE) == TIM_ForcedAction_Active) || \ |
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((MODE) == TIM_ForcedAction_InActive)) |
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/**
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* @}
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*/
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/** @defgroup TIM_One_Pulse_Mode
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* @{
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*/
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#define TIM_OPMode_Single ((uint16_t)0x0008) |
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#define TIM_OPMode_Repetitive ((uint16_t)0x0000) |
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#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \
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((MODE) == TIM_OPMode_Repetitive)) |
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/**
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* @}
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*/
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/** @defgroup TIM_Channel
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* @{
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*/
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#define TIM_Channel_1 ((uint16_t)0x0000) |
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#define TIM_Channel_2 ((uint16_t)0x0004) |
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#define TIM_Channel_3 ((uint16_t)0x0008) |
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#define TIM_Channel_4 ((uint16_t)0x000C) |
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#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
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((CHANNEL) == TIM_Channel_2) || \ |
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((CHANNEL) == TIM_Channel_3) || \ |
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((CHANNEL) == TIM_Channel_4)) |
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#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
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((CHANNEL) == TIM_Channel_2)) |
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#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
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((CHANNEL) == TIM_Channel_2) || \ |
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((CHANNEL) == TIM_Channel_3)) |
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/**
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* @}
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*/
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/** @defgroup TIM_Clock_Division_CKD
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* @{
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*/
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