amiro-blt / Target / Demo / ARMCM3_STM32F103_DiWheelDrive_GCC / Boot / lib / STM32F10x_StdPeriph_Driver / inc / stm32f10x_tim.h @ 69661903
History | View | Annotate | Download (51.2 KB)
| 1 |
/**
|
|---|---|
| 2 |
******************************************************************************
|
| 3 |
* @file stm32f10x_tim.h
|
| 4 |
* @author MCD Application Team
|
| 5 |
* @version V3.5.0
|
| 6 |
* @date 11-March-2011
|
| 7 |
* @brief This file contains all the functions prototypes for the TIM firmware
|
| 8 |
* library.
|
| 9 |
******************************************************************************
|
| 10 |
* @attention
|
| 11 |
*
|
| 12 |
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
| 13 |
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
| 14 |
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
| 15 |
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
| 16 |
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
| 17 |
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
| 18 |
*
|
| 19 |
* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
|
| 20 |
******************************************************************************
|
| 21 |
*/
|
| 22 |
|
| 23 |
/* Define to prevent recursive inclusion -------------------------------------*/
|
| 24 |
#ifndef __STM32F10x_TIM_H
|
| 25 |
#define __STM32F10x_TIM_H
|
| 26 |
|
| 27 |
#ifdef __cplusplus
|
| 28 |
extern "C" { |
| 29 |
#endif
|
| 30 |
|
| 31 |
/* Includes ------------------------------------------------------------------*/
|
| 32 |
#include "stm32f10x.h" |
| 33 |
|
| 34 |
/** @addtogroup STM32F10x_StdPeriph_Driver
|
| 35 |
* @{
|
| 36 |
*/
|
| 37 |
|
| 38 |
/** @addtogroup TIM
|
| 39 |
* @{
|
| 40 |
*/
|
| 41 |
|
| 42 |
/** @defgroup TIM_Exported_Types
|
| 43 |
* @{
|
| 44 |
*/
|
| 45 |
|
| 46 |
/**
|
| 47 |
* @brief TIM Time Base Init structure definition
|
| 48 |
* @note This structure is used with all TIMx except for TIM6 and TIM7.
|
| 49 |
*/
|
| 50 |
|
| 51 |
typedef struct |
| 52 |
{
|
| 53 |
uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
|
| 54 |
This parameter can be a number between 0x0000 and 0xFFFF */
|
| 55 |
|
| 56 |
uint16_t TIM_CounterMode; /*!< Specifies the counter mode.
|
| 57 |
This parameter can be a value of @ref TIM_Counter_Mode */
|
| 58 |
|
| 59 |
uint16_t TIM_Period; /*!< Specifies the period value to be loaded into the active
|
| 60 |
Auto-Reload Register at the next update event.
|
| 61 |
This parameter must be a number between 0x0000 and 0xFFFF. */
|
| 62 |
|
| 63 |
uint16_t TIM_ClockDivision; /*!< Specifies the clock division.
|
| 64 |
This parameter can be a value of @ref TIM_Clock_Division_CKD */
|
| 65 |
|
| 66 |
uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
|
| 67 |
reaches zero, an update event is generated and counting restarts
|
| 68 |
from the RCR value (N).
|
| 69 |
This means in PWM mode that (N+1) corresponds to:
|
| 70 |
- the number of PWM periods in edge-aligned mode
|
| 71 |
- the number of half PWM period in center-aligned mode
|
| 72 |
This parameter must be a number between 0x00 and 0xFF.
|
| 73 |
@note This parameter is valid only for TIM1 and TIM8. */
|
| 74 |
} TIM_TimeBaseInitTypeDef; |
| 75 |
|
| 76 |
/**
|
| 77 |
* @brief TIM Output Compare Init structure definition
|
| 78 |
*/
|
| 79 |
|
| 80 |
typedef struct |
| 81 |
{
|
| 82 |
uint16_t TIM_OCMode; /*!< Specifies the TIM mode.
|
| 83 |
This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
|
| 84 |
|
| 85 |
uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state.
|
| 86 |
This parameter can be a value of @ref TIM_Output_Compare_state */
|
| 87 |
|
| 88 |
uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state.
|
| 89 |
This parameter can be a value of @ref TIM_Output_Compare_N_state
|
| 90 |
@note This parameter is valid only for TIM1 and TIM8. */
|
| 91 |
|
| 92 |
uint16_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
|
| 93 |
This parameter can be a number between 0x0000 and 0xFFFF */
|
| 94 |
|
| 95 |
uint16_t TIM_OCPolarity; /*!< Specifies the output polarity.
|
| 96 |
This parameter can be a value of @ref TIM_Output_Compare_Polarity */
|
| 97 |
|
| 98 |
uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity.
|
| 99 |
This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
|
| 100 |
@note This parameter is valid only for TIM1 and TIM8. */
|
| 101 |
|
| 102 |
uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
|
| 103 |
This parameter can be a value of @ref TIM_Output_Compare_Idle_State
|
| 104 |
@note This parameter is valid only for TIM1 and TIM8. */
|
| 105 |
|
| 106 |
uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
|
| 107 |
This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
|
| 108 |
@note This parameter is valid only for TIM1 and TIM8. */
|
| 109 |
} TIM_OCInitTypeDef; |
| 110 |
|
| 111 |
/**
|
| 112 |
* @brief TIM Input Capture Init structure definition
|
| 113 |
*/
|
| 114 |
|
| 115 |
typedef struct |
| 116 |
{
|
| 117 |
|
| 118 |
uint16_t TIM_Channel; /*!< Specifies the TIM channel.
|
| 119 |
This parameter can be a value of @ref TIM_Channel */
|
| 120 |
|
| 121 |
uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal.
|
| 122 |
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
|
| 123 |
|
| 124 |
uint16_t TIM_ICSelection; /*!< Specifies the input.
|
| 125 |
This parameter can be a value of @ref TIM_Input_Capture_Selection */
|
| 126 |
|
| 127 |
uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler.
|
| 128 |
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
|
| 129 |
|
| 130 |
uint16_t TIM_ICFilter; /*!< Specifies the input capture filter.
|
| 131 |
This parameter can be a number between 0x0 and 0xF */
|
| 132 |
} TIM_ICInitTypeDef; |
| 133 |
|
| 134 |
/**
|
| 135 |
* @brief BDTR structure definition
|
| 136 |
* @note This structure is used only with TIM1 and TIM8.
|
| 137 |
*/
|
| 138 |
|
| 139 |
typedef struct |
| 140 |
{
|
| 141 |
|
| 142 |
uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode.
|
| 143 |
This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */
|
| 144 |
|
| 145 |
uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state.
|
| 146 |
This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */
|
| 147 |
|
| 148 |
uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters.
|
| 149 |
This parameter can be a value of @ref Lock_level */
|
| 150 |
|
| 151 |
uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the
|
| 152 |
switching-on of the outputs.
|
| 153 |
This parameter can be a number between 0x00 and 0xFF */
|
| 154 |
|
| 155 |
uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not.
|
| 156 |
This parameter can be a value of @ref Break_Input_enable_disable */
|
| 157 |
|
| 158 |
uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
|
| 159 |
This parameter can be a value of @ref Break_Polarity */
|
| 160 |
|
| 161 |
uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
|
| 162 |
This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
|
| 163 |
} TIM_BDTRInitTypeDef; |
| 164 |
|
| 165 |
/** @defgroup TIM_Exported_constants
|
| 166 |
* @{
|
| 167 |
*/
|
| 168 |
|
| 169 |
#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
|
| 170 |
((PERIPH) == TIM2) || \ |
| 171 |
((PERIPH) == TIM3) || \ |
| 172 |
((PERIPH) == TIM4) || \ |
| 173 |
((PERIPH) == TIM5) || \ |
| 174 |
((PERIPH) == TIM6) || \ |
| 175 |
((PERIPH) == TIM7) || \ |
| 176 |
((PERIPH) == TIM8) || \ |
| 177 |
((PERIPH) == TIM9) || \ |
| 178 |
((PERIPH) == TIM10)|| \ |
| 179 |
((PERIPH) == TIM11)|| \ |
| 180 |
((PERIPH) == TIM12)|| \ |
| 181 |
((PERIPH) == TIM13)|| \ |
| 182 |
((PERIPH) == TIM14)|| \ |
| 183 |
((PERIPH) == TIM15)|| \ |
| 184 |
((PERIPH) == TIM16)|| \ |
| 185 |
((PERIPH) == TIM17)) |
| 186 |
|
| 187 |
/* LIST1: TIM 1 and 8 */
|
| 188 |
#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
|
| 189 |
((PERIPH) == TIM8)) |
| 190 |
|
| 191 |
/* LIST2: TIM 1, 8, 15 16 and 17 */
|
| 192 |
#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
|
| 193 |
((PERIPH) == TIM8) || \ |
| 194 |
((PERIPH) == TIM15)|| \ |
| 195 |
((PERIPH) == TIM16)|| \ |
| 196 |
((PERIPH) == TIM17)) |
| 197 |
|
| 198 |
/* LIST3: TIM 1, 2, 3, 4, 5 and 8 */
|
| 199 |
#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
|
| 200 |
((PERIPH) == TIM2) || \ |
| 201 |
((PERIPH) == TIM3) || \ |
| 202 |
((PERIPH) == TIM4) || \ |
| 203 |
((PERIPH) == TIM5) || \ |
| 204 |
((PERIPH) == TIM8)) |
| 205 |
|
| 206 |
/* LIST4: TIM 1, 2, 3, 4, 5, 8, 15, 16 and 17 */
|
| 207 |
#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
|
| 208 |
((PERIPH) == TIM2) || \ |
| 209 |
((PERIPH) == TIM3) || \ |
| 210 |
((PERIPH) == TIM4) || \ |
| 211 |
((PERIPH) == TIM5) || \ |
| 212 |
((PERIPH) == TIM8) || \ |
| 213 |
((PERIPH) == TIM15)|| \ |
| 214 |
((PERIPH) == TIM16)|| \ |
| 215 |
((PERIPH) == TIM17)) |
| 216 |
|
| 217 |
/* LIST5: TIM 1, 2, 3, 4, 5, 8 and 15 */
|
| 218 |
#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
|
| 219 |
((PERIPH) == TIM2) || \ |
| 220 |
((PERIPH) == TIM3) || \ |
| 221 |
((PERIPH) == TIM4) || \ |
| 222 |
((PERIPH) == TIM5) || \ |
| 223 |
((PERIPH) == TIM8) || \ |
| 224 |
((PERIPH) == TIM15)) |
| 225 |
|
| 226 |
/* LIST6: TIM 1, 2, 3, 4, 5, 8, 9, 12 and 15 */
|
| 227 |
#define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
|
| 228 |
((PERIPH) == TIM2) || \ |
| 229 |
((PERIPH) == TIM3) || \ |
| 230 |
((PERIPH) == TIM4) || \ |
| 231 |
((PERIPH) == TIM5) || \ |
| 232 |
((PERIPH) == TIM8) || \ |
| 233 |
((PERIPH) == TIM9) || \ |
| 234 |
((PERIPH) == TIM12)|| \ |
| 235 |
((PERIPH) == TIM15)) |
| 236 |
|
| 237 |
/* LIST7: TIM 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 and 15 */
|
| 238 |
#define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
|
| 239 |
((PERIPH) == TIM2) || \ |
| 240 |
((PERIPH) == TIM3) || \ |
| 241 |
((PERIPH) == TIM4) || \ |
| 242 |
((PERIPH) == TIM5) || \ |
| 243 |
((PERIPH) == TIM6) || \ |
| 244 |
((PERIPH) == TIM7) || \ |
| 245 |
((PERIPH) == TIM8) || \ |
| 246 |
((PERIPH) == TIM9) || \ |
| 247 |
((PERIPH) == TIM12)|| \ |
| 248 |
((PERIPH) == TIM15)) |
| 249 |
|
| 250 |
/* LIST8: TIM 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 15, 16 and 17 */
|
| 251 |
#define IS_TIM_LIST8_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
|
| 252 |
((PERIPH) == TIM2) || \ |
| 253 |
((PERIPH) == TIM3) || \ |
| 254 |
((PERIPH) == TIM4) || \ |
| 255 |
((PERIPH) == TIM5) || \ |
| 256 |
((PERIPH) == TIM8) || \ |
| 257 |
((PERIPH) == TIM9) || \ |
| 258 |
((PERIPH) == TIM10)|| \ |
| 259 |
((PERIPH) == TIM11)|| \ |
| 260 |
((PERIPH) == TIM12)|| \ |
| 261 |
((PERIPH) == TIM13)|| \ |
| 262 |
((PERIPH) == TIM14)|| \ |
| 263 |
((PERIPH) == TIM15)|| \ |
| 264 |
((PERIPH) == TIM16)|| \ |
| 265 |
((PERIPH) == TIM17)) |
| 266 |
|
| 267 |
/* LIST9: TIM 1, 2, 3, 4, 5, 6, 7, 8, 15, 16, and 17 */
|
| 268 |
#define IS_TIM_LIST9_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
|
| 269 |
((PERIPH) == TIM2) || \ |
| 270 |
((PERIPH) == TIM3) || \ |
| 271 |
((PERIPH) == TIM4) || \ |
| 272 |
((PERIPH) == TIM5) || \ |
| 273 |
((PERIPH) == TIM6) || \ |
| 274 |
((PERIPH) == TIM7) || \ |
| 275 |
((PERIPH) == TIM8) || \ |
| 276 |
((PERIPH) == TIM15)|| \ |
| 277 |
((PERIPH) == TIM16)|| \ |
| 278 |
((PERIPH) == TIM17)) |
| 279 |
|
| 280 |
/**
|
| 281 |
* @}
|
| 282 |
*/
|
| 283 |
|
| 284 |
/** @defgroup TIM_Output_Compare_and_PWM_modes
|
| 285 |
* @{
|
| 286 |
*/
|
| 287 |
|
| 288 |
#define TIM_OCMode_Timing ((uint16_t)0x0000) |
| 289 |
#define TIM_OCMode_Active ((uint16_t)0x0010) |
| 290 |
#define TIM_OCMode_Inactive ((uint16_t)0x0020) |
| 291 |
#define TIM_OCMode_Toggle ((uint16_t)0x0030) |
| 292 |
#define TIM_OCMode_PWM1 ((uint16_t)0x0060) |
| 293 |
#define TIM_OCMode_PWM2 ((uint16_t)0x0070) |
| 294 |
#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \
|
| 295 |
((MODE) == TIM_OCMode_Active) || \ |
| 296 |
((MODE) == TIM_OCMode_Inactive) || \ |
| 297 |
((MODE) == TIM_OCMode_Toggle)|| \ |
| 298 |
((MODE) == TIM_OCMode_PWM1) || \ |
| 299 |
((MODE) == TIM_OCMode_PWM2)) |
| 300 |
#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \
|
| 301 |
((MODE) == TIM_OCMode_Active) || \ |
| 302 |
((MODE) == TIM_OCMode_Inactive) || \ |
| 303 |
((MODE) == TIM_OCMode_Toggle)|| \ |
| 304 |
((MODE) == TIM_OCMode_PWM1) || \ |
| 305 |
((MODE) == TIM_OCMode_PWM2) || \ |
| 306 |
((MODE) == TIM_ForcedAction_Active) || \ |
| 307 |
((MODE) == TIM_ForcedAction_InActive)) |
| 308 |
/**
|
| 309 |
* @}
|
| 310 |
*/
|
| 311 |
|
| 312 |
/** @defgroup TIM_One_Pulse_Mode
|
| 313 |
* @{
|
| 314 |
*/
|
| 315 |
|
| 316 |
#define TIM_OPMode_Single ((uint16_t)0x0008) |
| 317 |
#define TIM_OPMode_Repetitive ((uint16_t)0x0000) |
| 318 |
#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \
|
| 319 |
((MODE) == TIM_OPMode_Repetitive)) |
| 320 |
/**
|
| 321 |
* @}
|
| 322 |
*/
|
| 323 |
|
| 324 |
/** @defgroup TIM_Channel
|
| 325 |
* @{
|
| 326 |
*/
|
| 327 |
|
| 328 |
#define TIM_Channel_1 ((uint16_t)0x0000) |
| 329 |
#define TIM_Channel_2 ((uint16_t)0x0004) |
| 330 |
#define TIM_Channel_3 ((uint16_t)0x0008) |
| 331 |
#define TIM_Channel_4 ((uint16_t)0x000C) |
| 332 |
#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
|
| 333 |
((CHANNEL) == TIM_Channel_2) || \ |
| 334 |
((CHANNEL) == TIM_Channel_3) || \ |
| 335 |
((CHANNEL) == TIM_Channel_4)) |
| 336 |
#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
|
| 337 |
((CHANNEL) == TIM_Channel_2)) |
| 338 |
#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
|
| 339 |
((CHANNEL) == TIM_Channel_2) || \ |
| 340 |
((CHANNEL) == TIM_Channel_3)) |
| 341 |
/**
|
| 342 |
* @}
|
| 343 |
*/
|
| 344 |
|
| 345 |
/** @defgroup TIM_Clock_Division_CKD
|
| 346 |
* @{
|
| 347 |
*/
|
| 348 |