amiro-blt / Target / Demo / ARMCM3_STM32F103_DiWheelDrive_GCC / Boot / lib / fatfs / mmc.c @ 69661903
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/*------------------------------------------------------------------------/
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/ MMCv3/SDv1/SDv2 (in SPI mode) control module
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/-------------------------------------------------------------------------/
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/
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/ Copyright (C) 2013, ChaN, all right reserved.
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/
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/ * This software is a free software and there is NO WARRANTY.
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/ * No restriction on use. You can use, modify and redistribute it for
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/ personal, non-profit or commercial products UNDER YOUR RESPONSIBILITY.
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/ * Redistributions of source code must retain the above copyright notice.
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/
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/-------------------------------------------------------------------------*/
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/*
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* This file was modified from a sample available from the FatFs
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* web site. It was modified to work with a Olimex STM32-P103
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* evaluation board.
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*
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*/
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#include "diskio.h" |
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#include "stm32f10x.h" /* STM32 registers */ |
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#include "stm32f10x_conf.h" /* STM32 peripheral drivers */ |
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#include "boot.h" |
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/*--------------------------------------------------------------------------
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Module Private Functions
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---------------------------------------------------------------------------*/
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/* Definitions for MMC/SDC command */
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#define CMD0 (0) /* GO_IDLE_STATE */ |
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#define CMD1 (1) /* SEND_OP_COND */ |
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#define ACMD41 (41|0x80) /* SEND_OP_COND (SDC) */ |
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#define CMD8 (8) /* SEND_IF_COND */ |
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#define CMD9 (9) /* SEND_CSD */ |
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#define CMD10 (10) /* SEND_CID */ |
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#define CMD12 (12) /* STOP_TRANSMISSION */ |
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#define ACMD13 (13|0x80) /* SD_STATUS (SDC) */ |
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#define CMD16 (16) /* SET_BLOCKLEN */ |
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#define CMD17 (17) /* READ_SINGLE_BLOCK */ |
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#define CMD18 (18) /* READ_MULTIPLE_BLOCK */ |
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#define CMD23 (23) /* SET_BLOCK_COUNT */ |
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#define ACMD23 (23|0x80) /* SET_WR_BLK_ERASE_COUNT (SDC) */ |
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#define CMD24 (24) /* WRITE_BLOCK */ |
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#define CMD25 (25) /* WRITE_MULTIPLE_BLOCK */ |
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#define CMD41 (41) /* SEND_OP_COND (ACMD) */ |
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#define CMD55 (55) /* APP_CMD */ |
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#define CMD58 (58) /* READ_OCR */ |
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/* Control signals (Platform dependent) */
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#define CS_LOW() GPIO_ResetBits(GPIOB, GPIO_Pin_12) /* MMC CS = L */ |
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#define CS_HIGH() GPIO_SetBits(GPIOB, GPIO_Pin_12) /* MMC CS = H */ |
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#define FCLK_SLOW() /* Set slow clock (100k-400k) */ |
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#define FCLK_FAST() set_max_speed() /* Set fast clock (depends on the CSD) */ |
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static volatile |
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DSTATUS Stat = STA_NOINIT; /* Disk status */
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static
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UINT CardType; |
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/*-----------------------------------------------------------------------*/
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/* Send 80 or so clock transitions with CS and DI held high. This is */
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/* required after card power up to get it into SPI mode */
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/*-----------------------------------------------------------------------*/
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static
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void send_initial_clock_train(void) |
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{
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GPIO_InitTypeDef GPIO_InitStructure; |
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unsigned int i; |
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/* Ensure CS is held high. */
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CS_HIGH(); |
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/* Switch the SSI TX line to a GPIO and drive it high too. */
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15; |
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; |
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; |
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GPIO_Init(GPIOB, &GPIO_InitStructure); |
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GPIO_SetBits(GPIOB, GPIO_Pin_15); |
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/* Send 10 bytes over the SSI. This causes the clock to wiggle the */
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/* required number of times. */
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for(i = 0 ; i < 10 ; i++) |
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{
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/* Loop while DR register in not empty */
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while (SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_TXE) == RESET) { ; }
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/* Send byte through the SPI peripheral */
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SPI_I2S_SendData(SPI2, 0xff);
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/* Wait to receive a byte */
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while (SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_RXNE) == RESET) { ; }
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} |
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/* Revert to hardware control of the SSI TX line. */
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15; |
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; |
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; |
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GPIO_Init(GPIOB, &GPIO_InitStructure); |
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} |
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/*-----------------------------------------------------------------------*/
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/* Power Control (Platform dependent) */
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/*-----------------------------------------------------------------------*/
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/* When the target system does not support socket power control, there */
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/* is nothing to do in these functions. */
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static
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void power_on (void) |
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{
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SPI_InitTypeDef SPI_InitStructure; |
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GPIO_InitTypeDef GPIO_InitStructure; |
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/*
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* This doesn't really turn the power on, but initializes the
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* SSI port and pins needed to talk to the card.
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*/
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/* Enable GPIO clock for CS */
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RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE); |
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/* Enable SPI clock, SPI2: APB1 */
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RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE); |
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/* Configure I/O for Flash Chip select (PB12) */
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12; |
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; |
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; |
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GPIO_Init(GPIOB, &GPIO_InitStructure); |
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/* De-select the Card: Chip Select high */
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GPIO_SetBits(GPIOB, GPIO_Pin_12); |
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/* Configure SPI pins: SCK (PB13) and MOSI (PB15) with default alternate function (not re-mapped) push-pull */
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13 | GPIO_Pin_15; |
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; |
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; |
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GPIO_Init(GPIOB, &GPIO_InitStructure); |
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/* Configure MISO (PB14) as Input with internal pull-up */
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GPIO_InitStructure.GPIO_Pin = GPIO_Pin_14; |
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; |
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GPIO_Init(GPIOB, &GPIO_InitStructure); |
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/* SPI configuration */
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SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; |
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SPI_InitStructure.SPI_Mode = SPI_Mode_Master; |
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SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b; |
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SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low; |
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SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge; |
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SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; |
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SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_256; // 72000kHz/256=281kHz < 400kHz
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SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; |
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SPI_InitStructure.SPI_CRCPolynomial = 7;
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SPI_Init(SPI2, &SPI_InitStructure); |
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SPI_CalculateCRC(SPI2, DISABLE); |
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SPI_Cmd(SPI2, ENABLE); |
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/* Set DI and CS high and apply more than 74 pulses to SCLK for the card */
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/* to be able to accept a native command. */
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send_initial_clock_train(); |
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} |
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// set the SSI speed to the max setting
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static
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void set_max_speed(void) |
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{
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SPI_InitTypeDef SPI_InitStructure; |
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/* Disable the SPI system */
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SPI_Cmd(SPI2, DISABLE); |
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/* MMC/SDC can work at the clock frequency up to 20/25MHz so pick a speed close to
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* this but not higher
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*/
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SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; |
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SPI_InitStructure.SPI_Mode = SPI_Mode_Master; |
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SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b; |
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SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low; |
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SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge; |
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SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; |
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SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4; // 72MHz/4=18MHz < 20MHz
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SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; |
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SPI_InitStructure.SPI_CRCPolynomial = 7;
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SPI_Init(SPI2, &SPI_InitStructure); |
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SPI_CalculateCRC(SPI2, DISABLE); |
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/* Enable the SPI system */
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SPI_Cmd(SPI2, ENABLE); |
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} |
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static
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void power_off (void) |
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{
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Stat |= STA_NOINIT; /* Force uninitialized */
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} |
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/*-----------------------------------------------------------------------*/
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/* Transmit/Receive data to/from MMC via SPI (Platform dependent) */
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/*-----------------------------------------------------------------------*/
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static
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BYTE xchg_spi (BYTE dat) |
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{
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/* Send byte through the SPI peripheral */
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SPI_I2S_SendData(SPI2, dat); |
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/* Wait to receive a byte */
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while (SPI_I2S_GetFlagStatus(SPI2, SPI_I2S_FLAG_RXNE) == RESET) { ; }
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/* Return the byte read from the SPI bus */
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return (BYTE)SPI_I2S_ReceiveData(SPI2);
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} |
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static
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void rcvr_spi_m (BYTE *dst)
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{
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*dst = xchg_spi(0xFF);
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} |
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/*-----------------------------------------------------------------------*/
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/* Wait for card ready */
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/*-----------------------------------------------------------------------*/
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static
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int wait_ready (void) |
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{
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BYTE d; |
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ULONG timeOutTime; |
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/* set timeout for 500 ms from now */
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timeOutTime = TimerGet() + 500;
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do {
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d = xchg_spi(0xFF);
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} while ((d != 0xFF) && (TimerGet() < timeOutTime)); |
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return (d == 0xFF) ? 1 : 0; |
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} |
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/*-----------------------------------------------------------------------*/
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/* Deselect the card and release SPI bus */
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/*-----------------------------------------------------------------------*/
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static
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void deselect (void) |
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{
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CS_HIGH(); |
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xchg_spi(0xFF); /* Dummy clock (force DO hi-z for multiple slave SPI) */ |
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} |
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/*-----------------------------------------------------------------------*/
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/* Select the card and wait ready */
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/*-----------------------------------------------------------------------*/
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static
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int select (void) /* 1:Successful, 0:Timeout */ |
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{
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CS_LOW(); |
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xchg_spi(0xFF); /* Dummy clock (force DO enabled) */ |
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if (wait_ready()) return 1; /* OK */ |
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deselect(); |
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return 0; /* Timeout */ |
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} |
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/*-----------------------------------------------------------------------*/
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/* Receive a data packet from MMC */
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/*-----------------------------------------------------------------------*/
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static
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int rcvr_datablock ( /* 1:OK, 0:Failed */ |
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BYTE *buff, /* Data buffer to store received data */
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UINT btr /* Byte count (must be multiple of 4) */
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) |
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{
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BYTE token; |
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ULONG timeOutTime; |
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/* set timeout for 100 ms from now */
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timeOutTime = TimerGet() + 100;
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do { /* Wait for data packet in timeout of 100ms */ |
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token = xchg_spi(0xFF);
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} while ((token == 0xFF) && (TimerGet() < timeOutTime)); |
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if(token != 0xFE) return 0; /* If not valid data token, retutn with error */ |
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do { /* Receive the data block into buffer */ |
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rcvr_spi_m(buff++); |
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rcvr_spi_m(buff++); |
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} while (btr -= 2); |
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xchg_spi(0xFF); /* Discard CRC */ |
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xchg_spi(0xFF);
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return 1; /* Return with success */ |
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} |
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/*-----------------------------------------------------------------------*/
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/* Send a data packet to MMC */
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/*-----------------------------------------------------------------------*/
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#if _USE_WRITE
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static
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int xmit_datablock ( /* 1:OK, 0:Failed */ |
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const BYTE *buff, /* 512 byte data block to be transmitted */ |
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BYTE token /* Data token */
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) |
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{
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BYTE resp; |
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UINT wc; |
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if (!wait_ready()) return 0; |
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xchg_spi(token); /* Xmit a token */
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if (token != 0xFD) { /* Not StopTran token */ |
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wc = 512;
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do { /* Xmit the 512 byte data block to MMC */ |
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xchg_spi(*buff++); |
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xchg_spi(*buff++); |
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} while (wc -= 2); |
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xchg_spi(0xFF); /* CRC (Dummy) */ |
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xchg_spi(0xFF);
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resp = xchg_spi(0xFF); /* Receive a data response */ |
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if ((resp & 0x1F) != 0x05) /* If not accepted, return with error */ |
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return 0; |
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} |
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return 1; |
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} |
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#endif
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/*-----------------------------------------------------------------------*/
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/* Send a command packet to MMC */
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/*-----------------------------------------------------------------------*/
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static
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BYTE send_cmd ( |
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BYTE cmd, /* Command byte */
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DWORD arg /* Argument */
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) |
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{
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BYTE n, res; |
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if (cmd & 0x80) { /* ACMD<n> is the command sequense of CMD55-CMD<n> */ |
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cmd &= 0x7F;
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res = send_cmd(CMD55, 0);
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if (res > 1) return res; |
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} |
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/* Select the card and wait for ready */
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deselect(); |
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if (!select()) return 0xFF; |
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/* Send command packet */
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xchg_spi(0x40 | cmd); /* Start + Command index */ |
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xchg_spi((BYTE)(arg >> 24)); /* Argument[31..24] */ |
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xchg_spi((BYTE)(arg >> 16)); /* Argument[23..16] */ |
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xchg_spi((BYTE)(arg >> 8)); /* Argument[15..8] */ |
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xchg_spi((BYTE)arg); /* Argument[7..0] */
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n = 0x01; /* Dummy CRC + Stop */ |
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if (cmd == CMD0) n = 0x95; /* Valid CRC for CMD0(0) + Stop */ |
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if (cmd == CMD8) n = 0x87; /* Valid CRC for CMD8(0x1AA) + Stop */ |
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xchg_spi(n); |
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/* Receive command response */
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if (cmd == CMD12) xchg_spi(0xFF); /* Skip a stuff byte on stop to read */ |
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n = 10; /* Wait for a valid response in timeout of 10 attempts */ |
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do
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res = xchg_spi(0xFF);
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while ((res & 0x80) && --n); |
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return res; /* Return with the response value */ |
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} |
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/*--------------------------------------------------------------------------
|
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|
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Public Functions
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|
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---------------------------------------------------------------------------*/
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/*-----------------------------------------------------------------------*/
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/* Initialize Disk Drive */
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/*-----------------------------------------------------------------------*/
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DSTATUS disk_initialize ( |
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BYTE pdrv /* Physical drive nmuber (0) */
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) |
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{
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BYTE n, cmd, ty, ocr[4];
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ULONG timeOutTime; |
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if (pdrv) return STA_NOINIT; /* Supports only single drive */ |
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if (Stat & STA_NODISK) return Stat; /* No card in the socket */ |
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power_on(); /* Force socket power on */
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CS_LOW(); /* CS = L */
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ty = 0;
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if (send_cmd(CMD0, 0) == 1) { /* Enter Idle state */ |
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timeOutTime = TimerGet() + 1000; /* Initialization timeout of 1000 msec */ |
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if (send_cmd(CMD8, 0x1AA) == 1) { /* SDv2? */ |
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for (n = 0; n < 4; n++) ocr[n] = xchg_spi(0xFF); /* Get trailing return value of R7 resp */ |
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if (ocr[2] == 0x01 && ocr[3] == 0xAA) { /* The card can work at vdd range of 2.7-3.6V */ |
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while ((TimerGet() < timeOutTime) && send_cmd(ACMD41, 0x40000000)); /* Wait for leaving idle state (ACMD41 with HCS bit) */ |
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if ((TimerGet() < timeOutTime) && send_cmd(CMD58, 0) == 0) { /* Check CCS bit in the OCR */ |
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for (n = 0; n < 4; n++) ocr[n] = xchg_spi(0xFF); |
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ty = (ocr[0] & 0x40) ? CT_SD2|CT_BLOCK : CT_SD2; /* SDv2 */ |
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} |
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} |
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} else { /* SDv1 or MMCv3 */ |
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if (send_cmd(ACMD41, 0) <= 1) { |
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ty = CT_SD1; cmd = ACMD41; /* SDv1 */
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} else {
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ty = CT_MMC; cmd = CMD1; /* MMCv3 */
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} |
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while ((TimerGet() < timeOutTime) && send_cmd(cmd, 0)); /* Wait for leaving idle state */ |
| 446 |
if (!(TimerGet() < timeOutTime) || send_cmd(CMD16, 512) != 0) /* Set read/write block length to 512 */ |
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ty = 0;
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} |
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} |
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CardType = ty; |
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deselect(); |
| 452 |
|
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if (ty) { /* Initialization succeded */ |
| 454 |
Stat &= ~STA_NOINIT; /* Clear STA_NOINIT */
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FCLK_FAST(); |
| 456 |
} else { /* Initialization failed */ |
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power_off(); |
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} |
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return Stat;
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} |
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|
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|
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/*-----------------------------------------------------------------------*/
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/* Get Disk Status */
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/*-----------------------------------------------------------------------*/
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|
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DSTATUS disk_status ( |
| 470 |
BYTE pdrv /* Physical drive nmuber (0) */
|
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) |
| 472 |
{
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if (pdrv) return STA_NOINIT; /* Supports only single drive */ |
| 474 |
return Stat;
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} |
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|
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|
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/*-----------------------------------------------------------------------*/
|
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/* Read Sector(s) */
|
| 481 |
/*-----------------------------------------------------------------------*/
|
| 482 |
|
| 483 |
DRESULT disk_read ( |
| 484 |
BYTE pdrv, /* Physical drive number (0) */
|
| 485 |
BYTE *buff, /* Pointer to the data buffer to store read data */
|
| 486 |
DWORD sector, /* Start sector number (LBA) */
|
| 487 |
BYTE count /* Sector count (1..255) */
|
| 488 |
) |
| 489 |
{
|
| 490 |
if (pdrv || !count) return RES_PARERR; |
| 491 |
if (Stat & STA_NOINIT) return RES_NOTRDY; |
| 492 |
|
| 493 |
if (!(CardType & CT_BLOCK)) sector *= 512; /* Convert to byte address if needed */ |
| 494 |
|
| 495 |
if (count == 1) { /* Single block read */ |
| 496 |
if ((send_cmd(CMD17, sector) == 0) /* READ_SINGLE_BLOCK */ |
| 497 |
&& rcvr_datablock(buff, 512))
|
| 498 |
count = 0;
|
| 499 |
} |
| 500 |
else { /* Multiple block read */ |
| 501 |
if (send_cmd(CMD18, sector) == 0) { /* READ_MULTIPLE_BLOCK */ |
| 502 |
do {
|
| 503 |
if (!rcvr_datablock(buff, 512)) break; |
| 504 |
buff += 512;
|
| 505 |
} while (--count);
|
| 506 |
send_cmd(CMD12, 0); /* STOP_TRANSMISSION */ |
| 507 |
} |
| 508 |
} |
| 509 |
deselect(); |
| 510 |
|
| 511 |
return count ? RES_ERROR : RES_OK;
|
| 512 |
} |
| 513 |
|
| 514 |
|
| 515 |
|
| 516 |
/*-----------------------------------------------------------------------*/
|
| 517 |
/* Write Sector(s) */
|
| 518 |
/*-----------------------------------------------------------------------*/
|
| 519 |
|
| 520 |
#if _USE_WRITE
|
| 521 |
DRESULT disk_write ( |
| 522 |
BYTE pdrv, /* Physical drive nmuber (0) */
|
| 523 |
const BYTE *buff, /* Pointer to the data to be written */ |
| 524 |
DWORD sector, /* Start sector number (LBA) */
|
| 525 |
BYTE count /* Sector count (1..255) */
|
| 526 |
) |
| 527 |
{
|
| 528 |
if (pdrv || !count) return RES_PARERR; |
| 529 |
if (Stat & STA_NOINIT) return RES_NOTRDY; |
| 530 |
if (Stat & STA_PROTECT) return RES_WRPRT; |
| 531 |
|
| 532 |
if (!(CardType & CT_BLOCK)) sector *= 512; /* Convert to byte address if needed */ |
| 533 |
|
| 534 |
if (count == 1) { /* Single block write */ |
| 535 |
if ((send_cmd(CMD24, sector) == 0) /* WRITE_BLOCK */ |
| 536 |
&& xmit_datablock(buff, 0xFE))
|
| 537 |
count = 0;
|
| 538 |
} |
| 539 |
else { /* Multiple block write */ |
| 540 |
if (CardType & CT_SDC) send_cmd(ACMD23, count);
|
| 541 |
if (send_cmd(CMD25, sector) == 0) { /* WRITE_MULTIPLE_BLOCK */ |
| 542 |
do {
|
| 543 |
if (!xmit_datablock(buff, 0xFC)) break; |
| 544 |
buff += 512;
|
| 545 |
} while (--count);
|
| 546 |
if (!xmit_datablock(0, 0xFD)) /* STOP_TRAN token */ |
| 547 |
count = 1;
|
| 548 |
} |
| 549 |
} |
| 550 |
deselect(); |
| 551 |
|
| 552 |
return count ? RES_ERROR : RES_OK;
|
| 553 |
} |
| 554 |
#endif
|
| 555 |
|
| 556 |
|
| 557 |
|
| 558 |
/*-----------------------------------------------------------------------*/
|
| 559 |
/* Miscellaneous Functions */
|
| 560 |
/*-----------------------------------------------------------------------*/
|
| 561 |
|
| 562 |
#if _USE_IOCTL
|
| 563 |
DRESULT disk_ioctl ( |
| 564 |
BYTE pdrv, /* Physical drive nmuber (0) */
|
| 565 |
BYTE cmd, /* Control code */
|
| 566 |
void *buff /* Buffer to send/receive data block */ |
| 567 |
) |
| 568 |
{
|
| 569 |
DRESULT res; |
| 570 |
BYTE n, csd[16], *ptr = buff;
|
| 571 |
DWORD csz; |
| 572 |
|
| 573 |
|
| 574 |
if (pdrv) return RES_PARERR; |
| 575 |
if (Stat & STA_NOINIT) return RES_NOTRDY; |
| 576 |
|
| 577 |
res = RES_ERROR; |
| 578 |
switch (cmd) {
|
| 579 |
case CTRL_SYNC : /* Flush write-back cache, Wait for end of internal process */ |
| 580 |
if (select()) res = RES_OK;
|
| 581 |
break;
|
| 582 |
|
| 583 |
case GET_SECTOR_COUNT : /* Get number of sectors on the disk (WORD) */ |
| 584 |
if ((send_cmd(CMD9, 0) == 0) && rcvr_datablock(csd, 16)) { |
| 585 |
if ((csd[0] >> 6) == 1) { /* SDv2? */ |
| 586 |
csz = csd[9] + ((WORD)csd[8] << 8) + ((DWORD)(csd[7] & 63) << 16) + 1; |
| 587 |
*(DWORD*)buff = csz << 10;
|
| 588 |
} else { /* SDv1 or MMCv3 */ |
| 589 |
n = (csd[5] & 15) + ((csd[10] & 128) >> 7) + ((csd[9] & 3) << 1) + 2; |
| 590 |
csz = (csd[8] >> 6) + ((WORD)csd[7] << 2) + ((WORD)(csd[6] & 3) << 10) + 1; |
| 591 |
*(DWORD*)buff = csz << (n - 9);
|
| 592 |
} |
| 593 |
res = RES_OK; |
| 594 |
} |
| 595 |
break;
|
| 596 |
|
| 597 |
case GET_BLOCK_SIZE : /* Get erase block size in unit of sectors (DWORD) */ |
| 598 |
if (CardType & CT_SD2) { /* SDv2? */ |
| 599 |
if (send_cmd(ACMD13, 0) == 0) { /* Read SD status */ |
| 600 |
xchg_spi(0xFF);
|
| 601 |
if (rcvr_datablock(csd, 16)) { /* Read partial block */ |
| 602 |
for (n = 64 - 16; n; n--) xchg_spi(0xFF); /* Purge trailing data */ |
| 603 |
*(DWORD*)buff = 16UL << (csd[10] >> 4); |
| 604 |
res = RES_OK; |
| 605 |
} |
| 606 |
} |
| 607 |
} else { /* SDv1 or MMCv3 */ |
| 608 |
if ((send_cmd(CMD9, 0) == 0) && rcvr_datablock(csd, 16)) { /* Read CSD */ |
| 609 |
if (CardType & CT_SD1) { /* SDv1 */ |
| 610 |
*(DWORD*)buff = (((csd[10] & 63) << 1) + ((WORD)(csd[11] & 128) >> 7) + 1) << ((csd[13] >> 6) - 1); |
| 611 |
} else { /* MMCv3 */ |
| 612 |
*(DWORD*)buff = ((WORD)((csd[10] & 124) >> 2) + 1) * (((csd[11] & 3) << 3) + ((csd[11] & 224) >> 5) + 1); |
| 613 |
} |
| 614 |
res = RES_OK; |
| 615 |
} |
| 616 |
} |
| 617 |
break;
|
| 618 |
|
| 619 |
case MMC_GET_TYPE : /* Get card type flags (1 byte) */ |
| 620 |
*ptr = CardType; |
| 621 |
res = RES_OK; |
| 622 |
break;
|
| 623 |
|
| 624 |
case MMC_GET_CSD : /* Receive CSD as a data block (16 bytes) */ |
| 625 |
if ((send_cmd(CMD9, 0) == 0) /* READ_CSD */ |
| 626 |
&& rcvr_datablock(buff, 16))
|
| 627 |
res = RES_OK; |
| 628 |
break;
|
| 629 |
|
| 630 |
case MMC_GET_CID : /* Receive CID as a data block (16 bytes) */ |
| 631 |
if ((send_cmd(CMD10, 0) == 0) /* READ_CID */ |
| 632 |
&& rcvr_datablock(buff, 16))
|
| 633 |
res = RES_OK; |
| 634 |
break;
|
| 635 |
|
| 636 |
case MMC_GET_OCR : /* Receive OCR as an R3 resp (4 bytes) */ |
| 637 |
if (send_cmd(CMD58, 0) == 0) { /* READ_OCR */ |
| 638 |
for (n = 0; n < 4; n++) |
| 639 |
*((BYTE*)buff+n) = xchg_spi(0xFF);
|
| 640 |
res = RES_OK; |
| 641 |
} |
| 642 |
break;
|
| 643 |
|
| 644 |
case MMC_GET_SDSTAT : /* Receive SD status as a data block (64 bytes) */ |
| 645 |
if ((CardType & CT_SD2) && send_cmd(ACMD13, 0) == 0) { /* SD_STATUS */ |
| 646 |
xchg_spi(0xFF);
|
| 647 |
if (rcvr_datablock(buff, 64)) |
| 648 |
res = RES_OK; |
| 649 |
} |
| 650 |
break;
|
| 651 |
|
| 652 |
default:
|
| 653 |
res = RES_PARERR; |
| 654 |
} |
| 655 |
|
| 656 |
deselect(); |
| 657 |
|
| 658 |
return res;
|
| 659 |
} |
| 660 |
#endif
|
| 661 |
|
| 662 |
|
| 663 |
/*---------------------------------------------------------*/
|
| 664 |
/* User Provided Timer Function for FatFs module */
|
| 665 |
/*---------------------------------------------------------*/
|
| 666 |
/* This is a real time clock service to be called from */
|
| 667 |
/* FatFs module. Any valid time must be returned even if */
|
| 668 |
/* the system does not support a real time clock. */
|
| 669 |
/* This is not required in read-only configuration. */
|
| 670 |
|
| 671 |
DWORD get_fattime (void)
|
| 672 |
{
|
| 673 |
/* No RTC supprt. Return a fixed value 2013/5/10 0:00:00 */
|
| 674 |
return ((DWORD)(2013 - 1980) << 25) /* Y */ |
| 675 |
| ((DWORD)5 << 21) /* M */ |
| 676 |
| ((DWORD)10 << 16) /* D */ |
| 677 |
| ((DWORD)0 << 11) /* H */ |
| 678 |
| ((DWORD)0 << 5) /* M */ |
| 679 |
| ((DWORD)0 >> 1); /* S */ |
| 680 |
} |
| 681 |
|
| 682 |
|
| 683 |
|