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amiro-blt / Target / Demo / ARMCM3_STM32F103_LightRing_GCC / Boot / lib / CMSIS / CM3 / DeviceSupport / ST / STM32F10x / system_stm32f10x.c @ 69661903

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/**
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  ******************************************************************************
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  * @file    system_stm32f10x.c
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  * @author  MCD Application Team
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  * @version V3.5.0
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  * @date    11-March-2011
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  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
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  * 
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  * 1.  This file provides two functions and one global variable to be called from 
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  *     user application:
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  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
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  *                      factors, AHB/APBx prescalers and Flash settings). 
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  *                      This function is called at startup just after reset and 
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  *                      before branch to main program. This call is made inside
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  *                      the "startup_stm32f10x_xx.s" file.
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  *
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  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
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  *                                  by the user application to setup the SysTick 
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  *                                  timer or configure other parameters.
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  *                                     
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  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
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  *                                 be called whenever the core clock is changed
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  *                                 during program execution.
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  *
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  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
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  *    Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
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  *    configure the system clock before to branch to main program.
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  *
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  * 3. If the system clock source selected by user fails to startup, the SystemInit()
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  *    function will do nothing and HSI still used as system clock source. User can 
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  *    add some code to deal with this issue inside the SetSysClock() function.
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  *
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  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
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  *    the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 
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  *    When HSE is used as system clock source, directly or through PLL, and you
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  *    are using different crystal you have to adapt the HSE value to your own
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  *    configuration.
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  *        
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  ******************************************************************************
40
  * @attention
41
  *
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  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
44
  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
45
  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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  *
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  * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
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  ******************************************************************************
51
  */
52

    
53
/** @addtogroup CMSIS
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  * @{
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  */
56

    
57
/** @addtogroup stm32f10x_system
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  * @{
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  */  
60
  
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/** @addtogroup STM32F10x_System_Private_Includes
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  * @{
63
  */
64

    
65
#include "stm32f10x.h"
66

    
67
/**
68
  * @}
69
  */
70

    
71
/** @addtogroup STM32F10x_System_Private_TypesDefinitions
72
  * @{
73
  */
74

    
75
/**
76
  * @}
77
  */
78

    
79
/** @addtogroup STM32F10x_System_Private_Defines
80
  * @{
81
  */
82

    
83
/*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
84
   frequency (after reset the HSI is used as SYSCLK source)
85
   
86
   IMPORTANT NOTE:
87
   ============== 
88
   1. After each device reset the HSI is used as System clock source.
89

90
   2. Please make sure that the selected System clock doesn't exceed your device's
91
      maximum frequency.
92
      
93
   3. If none of the define below is enabled, the HSI is used as System clock
94
    source.
95

96
   4. The System clock configuration functions provided within this file assume that:
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        - For Low, Medium and High density Value line devices an external 8MHz 
98
          crystal is used to drive the System clock.
99
        - For Low, Medium and High density devices an external 8MHz crystal is
100
          used to drive the System clock.
101
        - For Connectivity line devices an external 25MHz crystal is used to drive
102
          the System clock.
103
     If you are using different crystal you have to adapt those functions accordingly.
104
    */
105
    
106
#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
107
/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
108
 #define SYSCLK_FREQ_24MHz  24000000
109
#else
110
/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
111
/* #define SYSCLK_FREQ_24MHz  24000000 */ 
112
/* #define SYSCLK_FREQ_36MHz  36000000 */
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/* #define SYSCLK_FREQ_48MHz  48000000 */
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/* #define SYSCLK_FREQ_56MHz  56000000 */
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#define SYSCLK_FREQ_72MHz  72000000
116
#endif
117

    
118
/*!< Uncomment the following line if you need to use external SRAM mounted
119
     on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 
120
     STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 
121
#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
122
/* #define DATA_IN_ExtSRAM */
123
#endif
124

    
125
/*!< Uncomment the following line if you need to relocate your vector Table in
126
     Internal SRAM. */ 
127
/* #define VECT_TAB_SRAM */
128
#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
129
                                  This value must be a multiple of 0x200. */
130

    
131

    
132
/**
133
  * @}
134
  */
135

    
136
/** @addtogroup STM32F10x_System_Private_Macros
137
  * @{
138
  */
139

    
140
/**
141
  * @}
142
  */
143

    
144
/** @addtogroup STM32F10x_System_Private_Variables
145
  * @{
146
  */
147

    
148
/*******************************************************************************
149
*  Clock Definitions
150
*******************************************************************************/
151
#ifdef SYSCLK_FREQ_HSE
152
  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;        /*!< System Clock Frequency (Core Clock) */
153
#elif defined SYSCLK_FREQ_24MHz
154
  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /*!< System Clock Frequency (Core Clock) */
155
#elif defined SYSCLK_FREQ_36MHz
156
  uint32_t SystemCoreClock         = SYSCLK_FREQ_36MHz;        /*!< System Clock Frequency (Core Clock) */
157
#elif defined SYSCLK_FREQ_48MHz
158
  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /*!< System Clock Frequency (Core Clock) */
159
#elif defined SYSCLK_FREQ_56MHz
160
  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /*!< System Clock Frequency (Core Clock) */
161
#elif defined SYSCLK_FREQ_72MHz
162
  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /*!< System Clock Frequency (Core Clock) */
163
#else /*!< HSI Selected as System Clock source */
164
  uint32_t SystemCoreClock         = HSI_VALUE;        /*!< System Clock Frequency (Core Clock) */
165
#endif
166

    
167
__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
168
/**
169
  * @}
170
  */
171

    
172
/** @addtogroup STM32F10x_System_Private_FunctionPrototypes
173
  * @{
174
  */
175

    
176
static void SetSysClock(void);
177

    
178
#ifdef SYSCLK_FREQ_HSE
179
  static void SetSysClockToHSE(void);
180
#elif defined SYSCLK_FREQ_24MHz
181
  static void SetSysClockTo24(void);
182
#elif defined SYSCLK_FREQ_36MHz
183
  static void SetSysClockTo36(void);
184
#elif defined SYSCLK_FREQ_48MHz
185
  static void SetSysClockTo48(void);
186
#elif defined SYSCLK_FREQ_56MHz
187
  static void SetSysClockTo56(void);  
188
#elif defined SYSCLK_FREQ_72MHz
189
  static void SetSysClockTo72(void);
190
#endif
191

    
192
#ifdef DATA_IN_ExtSRAM
193
  static void SystemInit_ExtMemCtl(void); 
194
#endif /* DATA_IN_ExtSRAM */
195

    
196
/**
197
  * @}
198
  */
199

    
200
/** @addtogroup STM32F10x_System_Private_Functions
201
  * @{
202
  */
203

    
204
/**
205
  * @brief  Setup the microcontroller system
206
  *         Initialize the Embedded Flash Interface, the PLL and update the 
207
  *         SystemCoreClock variable.
208
  * @note   This function should be used only after reset.
209
  * @param  None
210
  * @retval None
211
  */
212
void SystemInit (void)
213
{
214
  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
215
  /* Set HSION bit */
216
  RCC->CR |= (uint32_t)0x00000001;
217

    
218
  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
219
#ifndef STM32F10X_CL
220
  RCC->CFGR &= (uint32_t)0xF8FF0000;
221
#else
222
  RCC->CFGR &= (uint32_t)0xF0FF0000;
223
#endif /* STM32F10X_CL */   
224
  
225
  /* Reset HSEON, CSSON and PLLON bits */
226
  RCC->CR &= (uint32_t)0xFEF6FFFF;
227

    
228
  /* Reset HSEBYP bit */
229
  RCC->CR &= (uint32_t)0xFFFBFFFF;
230

    
231
  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
232
  RCC->CFGR &= (uint32_t)0xFF80FFFF;
233

    
234
#ifdef STM32F10X_CL
235
  /* Reset PLL2ON and PLL3ON bits */
236
  RCC->CR &= (uint32_t)0xEBFFFFFF;
237

    
238
  /* Disable all interrupts and clear pending bits  */
239
  RCC->CIR = 0x00FF0000;
240

    
241
  /* Reset CFGR2 register */
242
  RCC->CFGR2 = 0x00000000;
243
#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
244
  /* Disable all interrupts and clear pending bits  */
245
  RCC->CIR = 0x009F0000;
246

    
247
  /* Reset CFGR2 register */
248
  RCC->CFGR2 = 0x00000000;      
249
#else
250
  /* Disable all interrupts and clear pending bits  */
251
  RCC->CIR = 0x009F0000;
252
#endif /* STM32F10X_CL */
253
    
254
#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
255
  #ifdef DATA_IN_ExtSRAM
256
    SystemInit_ExtMemCtl(); 
257
  #endif /* DATA_IN_ExtSRAM */
258
#endif 
259

    
260
  /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
261
  /* Configure the Flash Latency cycles and enable prefetch buffer */
262
  SetSysClock();
263

    
264
#ifdef VECT_TAB_SRAM
265
  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
266
#else
267
  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
268
#endif 
269
}
270

    
271
/**
272
  * @brief  Update SystemCoreClock variable according to Clock Register Values.
273
  *         The SystemCoreClock variable contains the core clock (HCLK), it can
274
  *         be used by the user application to setup the SysTick timer or configure
275
  *         other parameters.
276
  *           
277
  * @note   Each time the core clock (HCLK) changes, this function must be called
278
  *         to update SystemCoreClock variable value. Otherwise, any configuration
279
  *         based on this variable will be incorrect.         
280
  *     
281
  * @note   - The system frequency computed by this function is not the real 
282
  *           frequency in the chip. It is calculated based on the predefined 
283
  *           constant and the selected clock source:
284
  *             
285
  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
286
  *                                              
287
  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
288
  *                          
289
  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
290
  *             or HSI_VALUE(*) multiplied by the PLL factors.
291
  *         
292
  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
293
  *             8 MHz) but the real value may vary depending on the variations
294
  *             in voltage and temperature.   
295
  *    
296
  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
297
  *              8 MHz or 25 MHz, depedning on the product used), user has to ensure
298
  *              that HSE_VALUE is same as the real frequency of the crystal used.
299
  *              Otherwise, this function may have wrong result.
300
  *                
301
  *         - The result of this function could be not correct when using fractional
302
  *           value for HSE crystal.
303
  * @param  None
304
  * @retval None
305
  */
306
void SystemCoreClockUpdate (void)
307
{
308
  uint32_t tmp = 0, pllmull = 0, pllsource = 0;
309

    
310
#ifdef  STM32F10X_CL
311
  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
312
#endif /* STM32F10X_CL */
313

    
314
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
315
  uint32_t prediv1factor = 0;
316
#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
317
    
318
  /* Get SYSCLK source -------------------------------------------------------*/
319
  tmp = RCC->CFGR & RCC_CFGR_SWS;
320
  
321
  switch (tmp)
322
  {
323
    case 0x00:  /* HSI used as system clock */
324
      SystemCoreClock = HSI_VALUE;
325
      break;
326
    case 0x04:  /* HSE used as system clock */
327
      SystemCoreClock = HSE_VALUE;
328
      break;
329
    case 0x08:  /* PLL used as system clock */
330

    
331
      /* Get PLL clock source and multiplication factor ----------------------*/
332
      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
333
      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
334
      
335
#ifndef STM32F10X_CL      
336
      pllmull = ( pllmull >> 18) + 2;
337
      
338
      if (pllsource == 0x00)
339
      {
340
        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
341
        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
342
      }
343
      else
344
      {
345
 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
346
       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
347
       /* HSE oscillator clock selected as PREDIV1 clock entry */
348
       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
349
 #else
350
        /* HSE selected as PLL clock entry */
351
        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
352
        {/* HSE oscillator clock divided by 2 */
353
          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
354
        }
355
        else
356
        {
357
          SystemCoreClock = HSE_VALUE * pllmull;
358
        }
359
 #endif
360
      }
361
#else
362
      pllmull = pllmull >> 18;
363
      
364
      if (pllmull != 0x0D)
365
      {
366
         pllmull += 2;
367
      }
368
      else
369
      { /* PLL multiplication factor = PLL input clock * 6.5 */
370
        pllmull = 13 / 2; 
371
      }
372
            
373
      if (pllsource == 0x00)
374
      {
375
        /* HSI oscillator clock divided by 2 selected as PLL clock entry */
376
        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
377
      }
378
      else
379
      {/* PREDIV1 selected as PLL clock entry */
380
        
381
        /* Get PREDIV1 clock source and division factor */
382
        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
383
        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
384
        
385
        if (prediv1source == 0)
386
        { 
387
          /* HSE oscillator clock selected as PREDIV1 clock entry */
388
          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          
389
        }
390
        else
391
        {/* PLL2 clock selected as PREDIV1 clock entry */
392
          
393
          /* Get PREDIV2 division factor and PLL2 multiplication factor */
394
          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
395
          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 
396
          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
397
        }
398
      }
399
#endif /* STM32F10X_CL */ 
400
      break;
401

    
402
    default:
403
      SystemCoreClock = HSI_VALUE;
404
      break;
405
  }
406
  
407
  /* Compute HCLK clock frequency ----------------*/
408
  /* Get HCLK prescaler */
409
  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
410
  /* HCLK clock frequency */
411
  SystemCoreClock >>= tmp;  
412
}
413

    
414
/**
415
  * @brief  Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
416
  * @param  None
417
  * @retval None
418
  */
419
static void SetSysClock(void)
420
{
421
#ifdef SYSCLK_FREQ_HSE
422
  SetSysClockToHSE();
423
#elif defined SYSCLK_FREQ_24MHz
424
  SetSysClockTo24();
425
#elif defined SYSCLK_FREQ_36MHz
426
  SetSysClockTo36();
427
#elif defined SYSCLK_FREQ_48MHz
428
  SetSysClockTo48();
429
#elif defined SYSCLK_FREQ_56MHz
430
  SetSysClockTo56();  
431
#elif defined SYSCLK_FREQ_72MHz
432
  SetSysClockTo72();
433
#endif
434
 
435
 /* If none of the define above is enabled, the HSI is used as System clock
436
    source (default after reset) */ 
437
}
438

    
439
/**
440
  * @brief  Setup the external memory controller. Called in startup_stm32f10x.s 
441
  *          before jump to __main
442
  * @param  None
443
  * @retval None
444
  */ 
445
#ifdef DATA_IN_ExtSRAM
446
/**
447
  * @brief  Setup the external memory controller. 
448
  *         Called in startup_stm32f10x_xx.s/.c before jump to main.
449
  *               This function configures the external SRAM mounted on STM3210E-EVAL
450
  *         board (STM32 High density devices). This SRAM will be used as program
451
  *         data memory (including heap and stack).
452
  * @param  None
453
  * @retval None
454
  */ 
455
void SystemInit_ExtMemCtl(void) 
456
{
457
/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 
458
  required, then adjust the Register Addresses */
459

    
460
  /* Enable FSMC clock */
461
  RCC->AHBENR = 0x00000114;
462
  
463
  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */  
464
  RCC->APB2ENR = 0x000001E0;
465
  
466
/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/
467
/*----------------  SRAM Address lines configuration -------------------------*/
468
/*----------------  NOE and NWE configuration --------------------------------*/  
469
/*----------------  NE3 configuration ----------------------------------------*/
470
/*----------------  NBL0, NBL1 configuration ---------------------------------*/
471
  
472
  GPIOD->CRL = 0x44BB44BB;  
473
  GPIOD->CRH = 0xBBBBBBBB;
474

    
475
  GPIOE->CRL = 0xB44444BB;  
476
  GPIOE->CRH = 0xBBBBBBBB;
477

    
478
  GPIOF->CRL = 0x44BBBBBB;  
479
  GPIOF->CRH = 0xBBBB4444;
480

    
481
  GPIOG->CRL = 0x44BBBBBB;  
482
  GPIOG->CRH = 0x44444B44;
483
   
484
/*----------------  FSMC Configuration ---------------------------------------*/  
485
/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/
486
  
487
  FSMC_Bank1->BTCR[4] = 0x00001011;
488
  FSMC_Bank1->BTCR[5] = 0x00000200;
489
}
490
#endif /* DATA_IN_ExtSRAM */
491

    
492
#ifdef SYSCLK_FREQ_HSE
493
/**
494
  * @brief  Selects HSE as System clock source and configure HCLK, PCLK2
495
  *         and PCLK1 prescalers.
496
  * @note   This function should be used only after reset.
497
  * @param  None
498
  * @retval None
499
  */
500
static void SetSysClockToHSE(void)
501
{
502
  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
503
  
504
  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
505
  /* Enable HSE */    
506
  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
507
 
508
  /* Wait till HSE is ready and if Time out is reached exit */
509
  do
510
  {
511
    HSEStatus = RCC->CR & RCC_CR_HSERDY;
512
    StartUpCounter++;  
513
  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
514

    
515
  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
516
  {
517
    HSEStatus = (uint32_t)0x01;
518
  }
519
  else
520
  {
521
    HSEStatus = (uint32_t)0x00;
522
  }  
523

    
524
  if (HSEStatus == (uint32_t)0x01)
525
  {
526

    
527
#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
528
    /* Enable Prefetch Buffer */
529
    FLASH->ACR |= FLASH_ACR_PRFTBE;
530

    
531
    /* Flash 0 wait state */
532
    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
533

    
534
#ifndef STM32F10X_CL
535
    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
536
#else
537
    if (HSE_VALUE <= 24000000)
538
        {
539
      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
540
        }
541
        else
542
        {
543
      FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
544
        }
545
#endif /* STM32F10X_CL */
546
#endif
547
 
548
    /* HCLK = SYSCLK */
549
    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
550
      
551
    /* PCLK2 = HCLK */
552
    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
553
    
554
    /* PCLK1 = HCLK */
555
    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
556
    
557
    /* Select HSE as system clock source */
558
    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
559
    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;    
560

    
561
    /* Wait till HSE is used as system clock source */
562
    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
563
    {
564
    }
565
  }
566
  else
567
  { /* If HSE fails to start-up, the application will have wrong clock 
568
         configuration. User can add here some code to deal with this error */
569
  }  
570
}
571
#elif defined SYSCLK_FREQ_24MHz
572
/**
573
  * @brief  Sets System clock frequency to 24MHz and configure HCLK, PCLK2 
574
  *         and PCLK1 prescalers.
575
  * @note   This function should be used only after reset.
576
  * @param  None
577
  * @retval None
578
  */
579
static void SetSysClockTo24(void)
580
{
581
  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
582
  
583
  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
584
  /* Enable HSE */    
585
  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
586
 
587
  /* Wait till HSE is ready and if Time out is reached exit */
588
  do
589
  {
590
    HSEStatus = RCC->CR & RCC_CR_HSERDY;
591
    StartUpCounter++;  
592
  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
593

    
594
  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
595
  {
596
    HSEStatus = (uint32_t)0x01;
597
  }
598
  else
599
  {
600
    HSEStatus = (uint32_t)0x00;
601
  }  
602

    
603
  if (HSEStatus == (uint32_t)0x01)
604
  {
605
#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 
606
    /* Enable Prefetch Buffer */
607
    FLASH->ACR |= FLASH_ACR_PRFTBE;
608

    
609
    /* Flash 0 wait state */
610
    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
611
    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;    
612
#endif
613
 
614
    /* HCLK = SYSCLK */
615
    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
616
      
617
    /* PCLK2 = HCLK */
618
    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
619
    
620
    /* PCLK1 = HCLK */
621
    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
622
    
623
#ifdef STM32F10X_CL
624
    /* Configure PLLs ------------------------------------------------------*/
625
    /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 
626
    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
627
    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
628
                            RCC_CFGR_PLLMULL6); 
629

    
630
    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
631
    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */       
632
    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
633
                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
634
    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
635
                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
636
  
637
    /* Enable PLL2 */
638
    RCC->CR |= RCC_CR_PLL2ON;
639
    /* Wait till PLL2 is ready */
640
    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
641
    {
642
    }   
643
#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
644
    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
645
    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
646
    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
647
#else    
648
    /*  PLL configuration:  = (HSE / 2) * 6 = 24 MHz */
649
    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
650
    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
651
#endif /* STM32F10X_CL */
652

    
653
    /* Enable PLL */
654
    RCC->CR |= RCC_CR_PLLON;
655

    
656
    /* Wait till PLL is ready */
657
    while((RCC->CR & RCC_CR_PLLRDY) == 0)
658
    {
659
    }
660

    
661
    /* Select PLL as system clock source */
662
    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
663
    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
664

    
665
    /* Wait till PLL is used as system clock source */
666
    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
667
    {
668
    }
669
  }
670
  else
671
  { /* If HSE fails to start-up, the application will have wrong clock 
672
         configuration. User can add here some code to deal with this error */
673
  } 
674
}
675
#elif defined SYSCLK_FREQ_36MHz
676
/**
677
  * @brief  Sets System clock frequency to 36MHz and configure HCLK, PCLK2 
678
  *         and PCLK1 prescalers. 
679
  * @note   This function should be used only after reset.
680
  * @param  None
681
  * @retval None
682
  */
683
static void SetSysClockTo36(void)
684
{
685
  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
686
  
687
  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/    
688
  /* Enable HSE */    
689
  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
690
 
691
  /* Wait till HSE is ready and if Time out is reached exit */
692
  do
693
  {
694
    HSEStatus = RCC->CR & RCC_CR_HSERDY;
695
    StartUpCounter++;  
696
  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
697

    
698
  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
699
  {
700
    HSEStatus = (uint32_t)0x01;
701
  }
702
  else
703
  {
704
    HSEStatus = (uint32_t)0x00;
705
  }  
706

    
707
  if (HSEStatus == (uint32_t)0x01)
708
  {
709
    /* Enable Prefetch Buffer */
710
    FLASH->ACR |= FLASH_ACR_PRFTBE;
711

    
712
    /* Flash 1 wait state */
713
    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
714
    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;    
715
 
716
    /* HCLK = SYSCLK */
717
    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
718
      
719
    /* PCLK2 = HCLK */
720
    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
721
    
722
    /* PCLK1 = HCLK */
723
    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
724
    
725
#ifdef STM32F10X_CL
726
    /* Configure PLLs ------------------------------------------------------*/
727
    
728
    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 
729
    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
730
    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 
731
                            RCC_CFGR_PLLMULL9); 
732

    
733
        /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
734
    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
735
        
736
    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
737
                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
738
    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
739
                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
740
  
741
    /* Enable PLL2 */
742
    RCC->CR |= RCC_CR_PLL2ON;
743
    /* Wait till PLL2 is ready */
744
    while((RCC->CR & RCC_CR_PLL2RDY) == 0)
745
    {
746
    }
747
    
748
#else    
749
    /*  PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
750
    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
751
    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
752
#endif /* STM32F10X_CL */
753

    
754
    /* Enable PLL */
755