amiro-blt / Target / Demo / ARMCM4_STM32F405_Power_Management_GCC / Boot / lib / ethernetlib / inc / stm32_eth.h @ 69661903
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/**
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******************************************************************************
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* @file stm32_eth.h
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* @author MCD Application Team
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* @version V1.0.0
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* @date 06/19/2009
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* @brief This file contains all the functions prototypes for the Ethernet
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* firmware library.
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******************************************************************************
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* @copy
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*
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*
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* <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32_ETH_H
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#define __STM32_ETH_H
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#ifdef __cplusplus
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extern "C" { |
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f4xx.h" /* STM32 registers */ |
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/** @addtogroup STM32_ETH_Driver
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* @{
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*/
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/** @defgroup ETH_Exported_Types
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* @{
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*/
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/**
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* @brief ETH MAC Init structure definition
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*/
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typedef struct { |
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/**
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* @brief / * MAC
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*/
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uint32_t ETH_AutoNegotiation; /*!< Selects or not the AutoNegotiation with the external PHY */
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uint32_t ETH_Watchdog; /*!< Enable/disable Watchdog timer */
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uint32_t ETH_Jabber; /*!< Enable/disable Jabber timer */
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uint32_t ETH_InterFrameGap; /*!< Selects minimum IFG between frames during transmission */
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uint32_t ETH_CarrierSense; /*!< Enable/disable Carrier Sense */
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uint32_t ETH_Speed; /*!< Indicates the Ethernet speed: 10/100 Mbps */
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uint32_t ETH_ReceiveOwn; /*!< Enable/disable the reception of frames when the TX_EN signal is asserted in Half-Duplex mode */
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uint32_t ETH_LoopbackMode; /*!< Enable/disable internal MAC MII Loopback mode */
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uint32_t ETH_Mode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode */
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uint32_t ETH_ChecksumOffload; /*!< Enable/disable the calculation of complement sum of all received Ethernet frame payloads */
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uint32_t ETH_RetryTransmission; /*!< Enable/disable the MAC attempt retries transmission, based on the settings of BL, when a colision occurs (Half-Duplex mode) */
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uint32_t ETH_AutomaticPadCRCStrip; /*!< Enable/disable Automatic MAC Pad/CRC Stripping */
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uint32_t ETH_BackOffLimit; /*!< Selects the BackOff limit value */
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uint32_t ETH_DeferralCheck; /*!< Enable/disable deferral check function (Half-Duplex mode) */
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uint32_t ETH_ReceiveAll; /*!< Enable/disable all frames reception by the MAC (No fitering)*/
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uint32_t ETH_SourceAddrFilter; /*!< Selects EnableNormal/EnableInverse/disable Source Address Filter comparison */
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uint32_t ETH_PassControlFrames; /*!< Selects None/All/FilterPass of all control frames (including unicast and multicast PAUSE frames) */
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uint32_t ETH_BroadcastFramesReception; /*!< Enable/disable reception of Broadcast Frames */
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uint32_t ETH_DestinationAddrFilter; /*!< Selects EnableNormal/EnableInverse destination filter for both unicast and multicast frames */
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uint32_t ETH_PromiscuousMode; /*!< Enable/disable Promiscuous Mode */
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uint32_t ETH_MulticastFramesFilter; /*!< Selects the Multicast Frames filter: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter */
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uint32_t ETH_UnicastFramesFilter; /*!< Selects the Unicast Frames filter: HashTableFilter/PerfectFilter/PerfectHashTableFilter */
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uint32_t ETH_HashTableHigh; /*!< This field contains the higher 32 bits of Hash table. */
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uint32_t ETH_HashTableLow; /*!< This field contains the lower 32 bits of Hash table. */
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uint32_t ETH_PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame */
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uint32_t ETH_ZeroQuantaPause; /*!< Enable/disable the automatic generation of Zero-Quanta Pause Control frames */
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uint32_t ETH_PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for automatic retransmission of PAUSE Frame */
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uint32_t ETH_UnicastPauseFrameDetect; /*!< Enable/disable MAC to detect the Pause frames (with MAC Address0 unicast address and unique multicast address) */
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uint32_t ETH_ReceiveFlowControl; /*!< Enable/disable the MAC to decode the received Pause frame and disable its transmitter for a specified (Pause Time) time */
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uint32_t ETH_TransmitFlowControl; /*!< Enable/disable the MAC to transmit Pause frames (Full-Duplex mode) or the MAC back-pressure operation (Half-Duplex mode) */
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uint32_t ETH_VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for comparison and filtering */
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uint32_t ETH_VLANTagIdentifier; /*!< VLAN tag identifier for receive frames */
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/**
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* @brief / * DMA
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*/
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uint32_t ETH_DropTCPIPChecksumErrorFrame; /*!< Enable/disable Dropping of TCP/IP Checksum Error Frames */
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uint32_t ETH_ReceiveStoreForward; /*!< Enable/disable Receive store and forward */
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uint32_t ETH_FlushReceivedFrame; /*!< Enable/disable flushing of received frames */
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uint32_t ETH_TransmitStoreForward; /*!< Enable/disable Transmit store and forward */
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uint32_t ETH_TransmitThresholdControl; /*!< Selects the Transmit Threshold Control */
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uint32_t ETH_ForwardErrorFrames; /*!< Enable/disable forward to DMA of all frames except runt error frames */
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uint32_t ETH_ForwardUndersizedGoodFrames; /*!< Enable/disable Rx FIFO to forward Undersized frames (frames with no Error and length less than 64 bytes) including pad-bytes and CRC) */
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uint32_t ETH_ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO */
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uint32_t ETH_SecondFrameOperate; /*!< Enable/disable the DMA process of a second frame of Transmit data even before status for first frame is obtained */
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uint32_t ETH_AddressAlignedBeats; /*!< Enable/disable Address Aligned Beats */
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uint32_t ETH_FixedBurst; /*!< Enable/disable the AHB Master interface fixed burst transfers */
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uint32_t ETH_RxDMABurstLength; /*!< Indicate the maximum number of beats to be transferred in one Rx DMA transaction */
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uint32_t ETH_TxDMABurstLength; /*!< Indicate the maximum number of beats to be transferred in one Tx DMA transaction */
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uint32_t ETH_DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode) */
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uint32_t ETH_DMAArbitration; /*!< Selects DMA Tx/Rx arbitration */
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}ETH_InitTypeDef; |
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/**--------------------------------------------------------------------------**/
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/**
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* @brief DMA descriptors types
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*/
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/**--------------------------------------------------------------------------**/
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/**
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* @brief ETH DMA Desciptors data structure definition
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*/
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typedef struct { |
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uint32_t Status; /*!< Status */
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uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */
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uint32_t Buffer1Addr; /*!< Buffer1 address pointer */
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uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */
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} ETH_DMADESCTypeDef; |
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/**
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* @}
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*/
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/** @defgroup ETH_Exported_Constants
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* @{
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*/
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/**--------------------------------------------------------------------------**/
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/**
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* @brief ETH Frames defines
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*/
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/**--------------------------------------------------------------------------**/
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/** @defgroup ENET_Buffers_setting
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* @{
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*/
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#define ETH_MAX_PACKET_SIZE 1520 /*!< ETH_HEADER + ETH_EXTRA + MAX_ETH_PAYLOAD + ETH_CRC */ |
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#define ETH_HEADER 14 /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ |
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#define ETH_CRC 4 /*!< Ethernet CRC */ |
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#define ETH_EXTRA 2 /*!< Extra bytes in some cases */ |
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#define VLAN_TAG 4 /*!< optional 802.1q VLAN Tag */ |
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#define MIN_ETH_PAYLOAD 46 /*!< Minimum Ethernet payload size */ |
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#define MAX_ETH_PAYLOAD 1500 /*!< Maximum Ethernet payload size */ |
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#define JUMBO_FRAME_PAYLOAD 9000 /*!< Jumbo frame payload size */ |
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/**--------------------------------------------------------------------------**/
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/**
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* @brief Ethernet DMA descriptors registers bits definition
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*/
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/**--------------------------------------------------------------------------**/
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/* DMA Tx Desciptor -----------------------------------------------------------*/
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/**----------------------------------------------------------------------------------------------
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TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
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-----------------------------------------------------------------------------------------------
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TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |
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-----------------------------------------------------------------------------------------------
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TDES2 | Buffer1 Address [31:0] |
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-----------------------------------------------------------------------------------------------
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TDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] |
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---------------------------------------------------------------------------------------------**/
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/**
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* @brief Bit definition of TDES0 register: DMA Tx descriptor status register
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*/
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#define ETH_DMATxDesc_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */ |
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#define ETH_DMATxDesc_IC ((uint32_t)0x40000000) /*!< Interrupt on Completion */ |
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#define ETH_DMATxDesc_LS ((uint32_t)0x20000000) /*!< Last Segment */ |
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#define ETH_DMATxDesc_FS ((uint32_t)0x10000000) /*!< First Segment */ |
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#define ETH_DMATxDesc_DC ((uint32_t)0x08000000) /*!< Disable CRC */ |
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#define ETH_DMATxDesc_DP ((uint32_t)0x04000000) /*!< Disable Padding */ |
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#define ETH_DMATxDesc_TTSE ((uint32_t)0x02000000) /*!< Transmit Time Stamp Enable */ |
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#define ETH_DMATxDesc_CIC ((uint32_t)0x00C00000) /*!< Checksum Insertion Control: 4 cases */ |
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#define ETH_DMATxDesc_CIC_ByPass ((uint32_t)0x00000000) /*!< Do Nothing: Checksum Engine is bypassed */ |
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#define ETH_DMATxDesc_CIC_IPV4Header ((uint32_t)0x00400000) /*!< IPV4 header Checksum Insertion */ |
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#define ETH_DMATxDesc_CIC_TCPUDPICMP_Segment ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ |
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#define ETH_DMATxDesc_CIC_TCPUDPICMP_Full ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ |
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#define ETH_DMATxDesc_TER ((uint32_t)0x00200000) /*!< Transmit End of Ring */ |
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#define ETH_DMATxDesc_TCH ((uint32_t)0x00100000) /*!< Second Address Chained */ |
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#define ETH_DMATxDesc_TTSS ((uint32_t)0x00020000) /*!< Tx Time Stamp Status */ |
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#define ETH_DMATxDesc_IHE ((uint32_t)0x00010000) /*!< IP Header Error */ |
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#define ETH_DMATxDesc_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */ |
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#define ETH_DMATxDesc_JT ((uint32_t)0x00004000) /*!< Jabber Timeout */ |
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#define ETH_DMATxDesc_FF ((uint32_t)0x00002000) /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */ |
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#define ETH_DMATxDesc_PCE ((uint32_t)0x00001000) /*!< Payload Checksum Error */ |
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#define ETH_DMATxDesc_LCA ((uint32_t)0x00000800) /*!< Loss of Carrier: carrier lost during tramsmission */ |
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#define ETH_DMATxDesc_NC ((uint32_t)0x00000400) /*!< No Carrier: no carrier signal from the tranceiver */ |
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#define ETH_DMATxDesc_LCO ((uint32_t)0x00000200) /*!< Late Collision: transmission aborted due to collision */ |
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#define ETH_DMATxDesc_EC ((uint32_t)0x00000100) /*!< Excessive Collision: transmission aborted after 16 collisions */ |
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#define ETH_DMATxDesc_VF ((uint32_t)0x00000080) /*!< VLAN Frame */ |
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#define ETH_DMATxDesc_CC ((uint32_t)0x00000078) /*!< Collision Count */ |
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#define ETH_DMATxDesc_ED ((uint32_t)0x00000004) /*!< Excessive Deferral */ |
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#define ETH_DMATxDesc_UF ((uint32_t)0x00000002) /*!< Underflow Error: late data arrival from the memory */ |
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#define ETH_DMATxDesc_DB ((uint32_t)0x00000001) /*!< Deferred Bit */ |
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/**
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* @brief Bit definition of TDES1 register
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*/
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#define ETH_DMATxDesc_TBS2 ((uint32_t)0x1FFF0000) /*!< Transmit Buffer2 Size */ |
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#define ETH_DMATxDesc_TBS1 ((uint32_t)0x00001FFF) /*!< Transmit Buffer1 Size */ |
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/**
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* @brief Bit definition of TDES2 register
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*/
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#define ETH_DMATxDesc_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */ |
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/**
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* @brief Bit definition of TDES3 register
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*/
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#define ETH_DMATxDesc_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */ |
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/**
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* @}
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*/
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/** @defgroup DMA_Rx_descriptor
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* @{
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*/
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/**--------------------------------------------------------------------------------------------------------------------
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RDES0 | OWN(31) | Status [30:0] |
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---------------------------------------------------------------------------------------------------------------------
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RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |
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---------------------------------------------------------------------------------------------------------------------
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RDES2 | Buffer1 Address [31:0] |
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---------------------------------------------------------------------------------------------------------------------
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RDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] |
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-------------------------------------------------------------------------------------------------------------------**/
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/**
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* @brief Bit definition of RDES0 register: DMA Rx descriptor status register
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*/
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#define ETH_DMARxDesc_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */ |
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#define ETH_DMARxDesc_AFM ((uint32_t)0x40000000) /*!< DA Filter Fail for the rx frame */ |
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#define ETH_DMARxDesc_FL ((uint32_t)0x3FFF0000) /*!< Receive descriptor frame length */ |
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#define ETH_DMARxDesc_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */ |
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#define ETH_DMARxDesc_DE ((uint32_t)0x00004000) /*!< Desciptor error: no more descriptors for receive frame */ |
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#define ETH_DMARxDesc_SAF ((uint32_t)0x00002000) /*!< SA Filter Fail for the received frame */ |
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#define ETH_DMARxDesc_LE ((uint32_t)0x00001000) /*!< Frame size not matching with length field */ |
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#define ETH_DMARxDesc_OE ((uint32_t)0x00000800) /*!< Overflow Error: Frame was damaged due to buffer overflow */ |
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#define ETH_DMARxDesc_VLAN ((uint32_t)0x00000400) /*!< VLAN Tag: received frame is a VLAN frame */ |
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#define ETH_DMARxDesc_FS ((uint32_t)0x00000200) /*!< First descriptor of the frame */ |
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#define ETH_DMARxDesc_LS ((uint32_t)0x00000100) /*!< Last descriptor of the frame */ |
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#define ETH_DMARxDesc_IPV4HCE ((uint32_t)0x00000080) /*!< IPC Checksum Error: Rx Ipv4 header checksum error */ |
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#define ETH_DMARxDesc_LC ((uint32_t)0x00000040) /*!< Late collision occurred during reception */ |
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#define ETH_DMARxDesc_FT ((uint32_t)0x00000020) /*!< Frame type - Ethernet, otherwise 802.3 */ |
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#define ETH_DMARxDesc_RWT ((uint32_t)0x00000010) /*!< Receive Watchdog Timeout: watchdog timer expired during reception */ |
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#define ETH_DMARxDesc_RE ((uint32_t)0x00000008) /*!< Receive error: error reported by MII interface */ |
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#define ETH_DMARxDesc_DBE ((uint32_t)0x00000004) /*!< Dribble bit error: frame contains non int multiple of 8 bits */ |
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#define ETH_DMARxDesc_CE ((uint32_t)0x00000002) /*!< CRC error */ |
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#define ETH_DMARxDesc_MAMPCE ((uint32_t)0x00000001) /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */ |
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/**
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* @brief Bit definition of RDES1 register
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*/
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#define ETH_DMARxDesc_DIC ((uint32_t)0x80000000) /*!< Disable Interrupt on Completion */ |
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#define ETH_DMARxDesc_RBS2 ((uint32_t)0x1FFF0000) /*!< Receive Buffer2 Size */ |
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#define ETH_DMARxDesc_RER ((uint32_t)0x00008000) /*!< Receive End of Ring */ |
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#define ETH_DMARxDesc_RCH ((uint32_t)0x00004000) /*!< Second Address Chained */ |
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#define ETH_DMARxDesc_RBS1 ((uint32_t)0x00001FFF) /*!< Receive Buffer1 Size */ |
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/**
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* @brief Bit definition of RDES2 register
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*/
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#define ETH_DMARxDesc_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */ |
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/**
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* @brief Bit definition of RDES3 register
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*/
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#define ETH_DMARxDesc_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */ |
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/**--------------------------------------------------------------------------**/
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/**
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* @brief Desciption of common PHY registers
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*/
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/**--------------------------------------------------------------------------**/
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/**
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* @}
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*/
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/** @defgroup PHY_Read_write_Timeouts
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* @{
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*/
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#define PHY_READ_TO ((uint32_t)0x0004FFFF) |
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#define PHY_WRITE_TO ((uint32_t)0x0004FFFF) |
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/**
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* @}
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*/
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/** @defgroup PHY_Reset_Delay
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* @{
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*/
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#define PHY_ResetDelay ((uint32_t)0x04000000) |
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/**
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* @}
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*/
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/** @defgroup PHY_Config_Delay
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* @{
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*/
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#define PHY_ConfigDelay ((uint32_t)0x00FFFFFF) |
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/**
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* @}
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*/
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/** @defgroup PHY_Register_address
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* @{
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*/
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#define PHY_BCR 0 /*!< Tranceiver Basic Control Register */ |
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#define PHY_BSR 1 /*!< Tranceiver Basic Status Register */ |
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/**
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* @}
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*/
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/** @defgroup PHY_basic_Control_register
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* @{
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*/
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#define PHY_Reset ((u16)0x8000) /*!< PHY Reset */ |
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#define PHY_Loopback ((u16)0x4000) /*!< Select loop-back mode */ |
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#define PHY_FULLDUPLEX_100M ((u16)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ |
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#define PHY_HALFDUPLEX_100M ((u16)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ |
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#define PHY_FULLDUPLEX_10M ((u16)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ |
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#define PHY_HALFDUPLEX_10M ((u16)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ |
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#define PHY_AutoNegotiation ((u16)0x1000) /*!< Enable auto-negotiation function */ |
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#define PHY_Restart_AutoNegotiation ((u16)0x0200) /*!< Restart auto-negotiation function */ |
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#define PHY_Powerdown ((u16)0x0800) /*!< Select the power down mode */ |
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#define PHY_Isolate ((u16)0x0400) /*!< Isolate PHY from MII */ |
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/**
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* @}
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*/
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/** @defgroup PHY_basic_status_register
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* @{
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*/
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#define PHY_AutoNego_Complete ((u16)0x0020) /*!< Auto-Negotioation process completed */ |
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#define PHY_Linked_Status ((u16)0x0004) /*!< Valid link established */ |
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#define PHY_Jabber_detection ((u16)0x0002) /*!< Jabber condition detected */ |
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/**
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* @}
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*/
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/** @defgroup PHY_status_register
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* @{
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*/
|
| 349 |
/* The PHY status register value change from a PHY to another so the user have
|
| 350 |
to update this value depending on the used external PHY */
|
| 351 |
/**
|
| 352 |
* @brief For LAN8700
|
| 353 |
*/
|
| 354 |
//#define PHY_SR 31 /*!< Tranceiver Status Register */
|
| 355 |
/**
|
| 356 |
* @brief For DP83848
|
| 357 |
*/
|
| 358 |
#define PHY_SR 16 /*!< Tranceiver Status Register */ |
| 359 |
|
| 360 |
/* The Speed and Duplex mask values change from a PHY to another so the user have to update
|
| 361 |
this value depending on the used external PHY */
|
| 362 |
/**
|
| 363 |
* @brief For LAN8700
|
| 364 |
*/
|
| 365 |
//#define PHY_Speed_Status ((u16)0x0004) /*!< Configured information of Speed: 10Mbps */
|
| 366 |
//#define PHY_Duplex_Status ((u16)0x0010) /*!< Configured information of Duplex: Full-duplex */
|
| 367 |
|
| 368 |
/**
|
| 369 |
* @brief For DP83848
|
| 370 |
*/
|
| 371 |
#define PHY_Speed_Status ((u16)0x0002) /*!< Configured information of Speed: 10Mbps */ |
| 372 |
#define PHY_Duplex_Status ((u16)0x0004) /*!< Configured information of Duplex: Full-duplex */ |
| 373 |
#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20) |
| 374 |
#define IS_ETH_PHY_REG(REG) (((REG) == PHY_BCR) || \
|
| 375 |
((REG) == PHY_BSR) || \ |
| 376 |
((REG) == PHY_SR)) |
| 377 |
|
| 378 |
/**--------------------------------------------------------------------------**/
|
| 379 |
/**
|
| 380 |
* @brief MAC defines
|
| 381 |
*/
|
| 382 |
/**--------------------------------------------------------------------------**/
|
| 383 |
|
| 384 |
/**
|
| 385 |
* @}
|
| 386 |
*/
|
| 387 |
|
| 388 |
/** @defgroup ETH_AutoNegotiation
|
| 389 |
* @{
|
| 390 |
*/
|
| 391 |
#define ETH_AutoNegotiation_Enable ((uint32_t)0x00000001) |
| 392 |
#define ETH_AutoNegotiation_Disable ((uint32_t)0x00000000) |
| 393 |
#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AutoNegotiation_Enable) || \
|
| 394 |
((CMD) == ETH_AutoNegotiation_Disable)) |
| 395 |
|
| 396 |
/**
|
| 397 |
* @}
|
| 398 |
*/
|
| 399 |
|
| 400 |
/** @defgroup ETH_watchdog
|
| 401 |
* @{
|
| 402 |
*/
|
| 403 |
#define ETH_Watchdog_Enable ((uint32_t)0x00000000) |
| 404 |
#define ETH_Watchdog_Disable ((uint32_t)0x00800000) |
| 405 |
#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_Watchdog_Enable) || \
|
| 406 |
((CMD) == ETH_Watchdog_Disable)) |
| 407 |
|
| 408 |
/**
|
| 409 |
* @}
|
| 410 |
*/
|
| 411 |
|
| 412 |
/** @defgroup ETH_Jabber
|
| 413 |
* @{
|
| 414 |
*/
|
| 415 |
#define ETH_Jabber_Enable ((uint32_t)0x00000000) |
| 416 |
#define ETH_Jabber_Disable ((uint32_t)0x00400000) |
| 417 |
#define IS_ETH_JABBER(CMD) (((CMD) == ETH_Jabber_Enable) || \
|
| 418 |
((CMD) == ETH_Jabber_Disable)) |
| 419 |
|
| 420 |
/**
|
| 421 |
* @}
|
| 422 |
*/
|
| 423 |
|
| 424 |
/** @defgroup ETH_Inter_Frame_Gap
|
| 425 |
* @{
|
| 426 |
*/
|
| 427 |
#define ETH_InterFrameGap_96Bit ((uint32_t)0x00000000) /*!< minimum IFG between frames during transmission is 96Bit */ |
| 428 |
#define ETH_InterFrameGap_88Bit ((uint32_t)0x00020000) /*!< minimum IFG between frames during transmission is 88Bit */ |
| 429 |
#define ETH_InterFrameGap_80Bit ((uint32_t)0x00040000) /*!< minimum IFG between frames during transmission is 80Bit */ |
| 430 |
#define ETH_InterFrameGap_72Bit ((uint32_t)0x00060000) /*!< minimum IFG between frames during transmission is 72Bit */ |
| 431 |
#define ETH_InterFrameGap_64Bit ((uint32_t)0x00080000) /*!< minimum IFG between frames during transmission is 64Bit */ |
| 432 |
#define ETH_InterFrameGap_56Bit ((uint32_t)0x000A0000) /*!< minimum IFG between frames during transmission is 56Bit */ |
| 433 |
#define ETH_InterFrameGap_48Bit ((uint32_t)0x000C0000) /*!< minimum IFG between frames during transmission is 48Bit */ |
| 434 |
#define ETH_InterFrameGap_40Bit ((uint32_t)0x000E0000) /*!< minimum IFG between frames during transmission is 40Bit */ |
| 435 |
#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_InterFrameGap_96Bit) || \
|
| 436 |
((GAP) == ETH_InterFrameGap_88Bit) || \ |
| 437 |
((GAP) == ETH_InterFrameGap_80Bit) || \ |
| 438 |
((GAP) == ETH_InterFrameGap_72Bit) || \ |
| 439 |
((GAP) == ETH_InterFrameGap_64Bit) || \ |
| 440 |
((GAP) == ETH_InterFrameGap_56Bit) || \ |
| 441 |
((GAP) == ETH_InterFrameGap_48Bit) || \ |
| 442 |
((GAP) == ETH_InterFrameGap_40Bit)) |
| 443 |
|
| 444 |
/**
|
| 445 |
* @}
|
| 446 |
*/
|
| 447 |
|
| 448 |
/** @defgroup ETH_Carrier_Sense
|
| 449 |
* @{
|
| 450 |
*/
|
| 451 |
#define ETH_CarrierSense_Enable ((uint32_t)0x00000000) |
| 452 |
#define ETH_CarrierSense_Disable ((uint32_t)0x00010000) |
| 453 |
#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CarrierSense_Enable) || \
|
| 454 |
((CMD) == ETH_CarrierSense_Disable)) |
| 455 |
|
| 456 |
/**
|
| 457 |
* @}
|
| 458 |
*/
|
| 459 |
|
| 460 |
/** @defgroup ETH_Speed
|
| 461 |
* @{
|
| 462 |
*/
|
| 463 |
#define ETH_Speed_10M ((uint32_t)0x00000000) |
| 464 |
#define ETH_Speed_100M ((uint32_t)0x00004000) |
| 465 |
#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_Speed_10M) || \
|
| 466 |
((SPEED) == ETH_Speed_100M)) |
| 467 |
|
| 468 |
/**
|
| 469 |
* @}
|
| 470 |
*/
|
| 471 |
|
| 472 |
/** @defgroup ETH_Receive_Own
|
| 473 |
* @{
|
| 474 |
*/
|
| 475 |
#define ETH_ReceiveOwn_Enable ((uint32_t)0x00000000) |
| 476 |
#define ETH_ReceiveOwn_Disable ((uint32_t)0x00002000) |
| 477 |
#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_ReceiveOwn_Enable) || \
|
| 478 |
((CMD) == ETH_ReceiveOwn_Disable)) |
| 479 |
|
| 480 |
/**
|
| 481 |
* @}
|
| 482 |
*/
|
| 483 |
|
| 484 |
/** @defgroup ETH_Loop_back_Mode
|
| 485 |
* @{
|
| 486 |
*/
|
| 487 |
#define ETH_LoopbackMode_Enable ((uint32_t)0x00001000) |
| 488 |
#define ETH_LoopbackMode_Disable ((uint32_t)0x00000000) |
| 489 |
#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LoopbackMode_Enable) || \
|
| 490 |
((CMD) == ETH_LoopbackMode_Disable)) |
| 491 |
|
| 492 |
/**
|
| 493 |
* @}
|
| 494 |
*/
|
| 495 |
|
| 496 |
/** @defgroup ETH_Duplex_mode
|
| 497 |
* @{
|
| 498 |
*/
|
| 499 |
#define ETH_Mode_FullDuplex ((uint32_t)0x00000800) |
| 500 |
#define ETH_Mode_HalfDuplex ((uint32_t)0x00000000) |
| 501 |
#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_Mode_FullDuplex) || \
|
| 502 |
((MODE) == ETH_Mode_HalfDuplex)) |
| 503 |
|
| 504 |
/**
|
| 505 |
* @}
|
| 506 |
*/
|
| 507 |
|
| 508 |
/** @defgroup ETH_Checksum_Offload
|
| 509 |
* @{
|
| 510 |
*/
|
| 511 |
#define ETH_ChecksumOffload_Enable ((uint32_t)0x00000400) |
| 512 |
#define ETH_ChecksumOffload_Disable ((uint32_t)0x00000000) |
| 513 |
#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_ChecksumOffload_Enable) || \
|
| 514 |
((CMD) == ETH_ChecksumOffload_Disable)) |
| 515 |
|
| 516 |
/**
|
| 517 |
* @}
|
| 518 |
*/
|
| 519 |
|
| 520 |
/** @defgroup ETH_Retry_Transmission
|
| 521 |
* @{
|
| 522 |
*/
|
| 523 |
#define ETH_RetryTransmission_Enable ((uint32_t)0x00000000) |
| 524 |
#define ETH_RetryTransmission_Disable ((uint32_t)0x00000200) |
| 525 |
#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RetryTransmission_Enable) || \
|
| 526 |
((CMD) == ETH_RetryTransmission_Disable)) |
| 527 |
|
| 528 |
/**
|
| 529 |
* @}
|
| 530 |
*/
|
| 531 |
|
| 532 |
/** @defgroup ETH_Automatic_Pad_CRC_Strip
|
| 533 |
* @{
|
| 534 |
*/
|
| 535 |
#define ETH_AutomaticPadCRCStrip_Enable ((uint32_t)0x00000080) |
| 536 |
#define ETH_AutomaticPadCRCStrip_Disable ((uint32_t)0x00000000) |
| 537 |
#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AutomaticPadCRCStrip_Enable) || \
|
| 538 |
((CMD) == ETH_AutomaticPadCRCStrip_Disable)) |
| 539 |
|
| 540 |
/**
|
| 541 |
* @}
|
| 542 |
*/
|
| 543 |
|
| 544 |
/** @defgroup ETH_Back-Off_limit
|
| 545 |
* @{
|
| 546 |
*/
|
| 547 |
#define ETH_BackOffLimit_10 ((uint32_t)0x00000000) |
| 548 |
#define ETH_BackOffLimit_8 ((uint32_t)0x00000020) |
| 549 |
#define ETH_BackOffLimit_4 ((uint32_t)0x00000040) |
| 550 |
#define ETH_BackOffLimit_1 ((uint32_t)0x00000060) |
| 551 |
#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BackOffLimit_10) || \
|
| 552 |
((LIMIT) == ETH_BackOffLimit_8) || \ |
| 553 |
((LIMIT) == ETH_BackOffLimit_4) || \ |
| 554 |
((LIMIT) == ETH_BackOffLimit_1)) |
| 555 |
|
| 556 |
/**
|
| 557 |
* @}
|
| 558 |
*/
|
| 559 |
|
| 560 |
/** @defgroup ETH_Deferral_Check
|
| 561 |
* @{
|
| 562 |
*/
|
| 563 |
#define ETH_DeferralCheck_Enable ((uint32_t)0x00000010) |
| 564 |
#define ETH_DeferralCheck_Disable ((uint32_t)0x00000000) |
| 565 |
#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DeferralCheck_Enable) || \
|
| 566 |
((CMD) == ETH_DeferralCheck_Disable)) |
| 567 |
|
| 568 |
/**
|
| 569 |
* @}
|
| 570 |
*/
|
| 571 |
|
| 572 |
/** @defgroup ETH_Receive_All
|
| 573 |
* @{
|
| 574 |
*/
|
| 575 |
#define ETH_ReceiveAll_Enable ((uint32_t)0x80000000) |
| 576 |
#define ETH_ReceiveAll_Disable ((uint32_t)0x00000000) |
| 577 |
#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_ReceiveAll_Enable) || \
|
| 578 |
((CMD) == ETH_ReceiveAll_Disable)) |
| 579 |
|
| 580 |
/**
|
| 581 |
* @}
|
| 582 |
*/
|
| 583 |
|
| 584 |
/** @defgroup ETH_Source_Addr_Filter
|
| 585 |
* @{
|
| 586 |
*/
|
| 587 |
#define ETH_SourceAddrFilter_Normal_Enable ((uint32_t)0x00000200) |
| 588 |
#define ETH_SourceAddrFilter_Inverse_Enable ((uint32_t)0x00000300) |
| 589 |
#define ETH_SourceAddrFilter_Disable ((uint32_t)0x00000000) |
| 590 |
#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SourceAddrFilter_Normal_Enable) || \
|
| 591 |
((CMD) == ETH_SourceAddrFilter_Inverse_Enable) || \ |
| 592 |
((CMD) == ETH_SourceAddrFilter_Disable)) |
| 593 |
|
| 594 |
/**
|
| 595 |
* @}
|
| 596 |
*/
|
| 597 |
|
| 598 |
/** @defgroup ETH_Pass_Control_Frames
|
| 599 |
* @{
|
| 600 |
*/
|
| 601 |
#define ETH_PassControlFrames_BlockAll ((uint32_t)0x00000040) /*!< MAC filters all control frames from reaching the application */ |
| 602 |
#define ETH_PassControlFrames_ForwardAll ((uint32_t)0x00000080) /*!< MAC forwards all control frames to application even if they fail the Address Filter */ |
| 603 |
#define ETH_PassControlFrames_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /*!< MAC forwards control frames that pass the Address Filter. */ |
| 604 |
#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PassControlFrames_BlockAll) || \
|
| 605 |
((PASS) == ETH_PassControlFrames_ForwardAll) || \ |
| 606 |
((PASS) == ETH_PassControlFrames_ForwardPassedAddrFilter)) |
| 607 |
|
| 608 |
/**
|
| 609 |
* @}
|
| 610 |
*/
|
| 611 |
|
| 612 |
/** @defgroup ETH_Broadcast_Frames_Reception
|
| 613 |
* @{
|
| 614 |
*/
|
| 615 |
#define ETH_BroadcastFramesReception_Enable ((uint32_t)0x00000000) |
| 616 |
#define ETH_BroadcastFramesReception_Disable ((uint32_t)0x00000020) |
| 617 |
#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BroadcastFramesReception_Enable) || \
|
| 618 |
((CMD) == ETH_BroadcastFramesReception_Disable)) |
| 619 |
|
| 620 |
/**
|
| 621 |
* @}
|
| 622 |
*/
|
| 623 |
|
| 624 |
/** @defgroup ETH_Destination_Addr_Filter
|
| 625 |
* @{
|
| 626 |
*/
|
| 627 |
#define ETH_DestinationAddrFilter_Normal ((uint32_t)0x00000000) |
| 628 |
#define ETH_DestinationAddrFilter_Inverse ((uint32_t)0x00000008) |
| 629 |
#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DestinationAddrFilter_Normal) || \
|
| 630 |
((FILTER) == ETH_DestinationAddrFilter_Inverse)) |
| 631 |
|
| 632 |
/**
|
| 633 |
* @}
|
| 634 |
*/
|
| 635 |
|
| 636 |
/** @defgroup ETH_Promiscuous_Mode
|
| 637 |
* @{
|
| 638 |
*/
|
| 639 |
#define ETH_PromiscuousMode_Enable ((uint32_t)0x00000001) |
| 640 |
#define ETH_PromiscuousMode_Disable ((uint32_t)0x00000000) |
| 641 |
#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PromiscuousMode_Enable) || \
|
| 642 |
((CMD) == ETH_PromiscuousMode_Disable)) |
| 643 |
|
| 644 |
/**
|
| 645 |
* @}
|
| 646 |
*/
|
| 647 |
|
| 648 |
/** @defgroup ETH_multicast_frames_filter
|
| 649 |
* @{
|
| 650 |
*/
|
| 651 |
#define ETH_MulticastFramesFilter_PerfectHashTable ((uint32_t)0x00000404) |
| 652 |
#define ETH_MulticastFramesFilter_HashTable ((uint32_t)0x00000004) |
| 653 |
#define ETH_MulticastFramesFilter_Perfect ((uint32_t)0x00000000) |
| 654 |
#define ETH_MulticastFramesFilter_None ((uint32_t)0x00000010) |
| 655 |
#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MulticastFramesFilter_PerfectHashTable) || \
|
| 656 |
((FILTER) == ETH_MulticastFramesFilter_HashTable) || \ |
| 657 |
((FILTER) == ETH_MulticastFramesFilter_Perfect) || \ |
| 658 |
((FILTER) == ETH_MulticastFramesFilter_None)) |
| 659 |
|
| 660 |
|
| 661 |
/**
|
| 662 |
* @}
|
| 663 |
*/
|
| 664 |
|
| 665 |
/** @defgroup ETH_unicast_frames_filter
|
| 666 |
* @{
|
| 667 |
*/
|
| 668 |
#define ETH_UnicastFramesFilter_PerfectHashTable ((uint32_t)0x00000402) |
| 669 |
#define ETH_UnicastFramesFilter_HashTable ((uint32_t)0x00000002) |
| 670 |
#define ETH_UnicastFramesFilter_Perfect ((uint32_t)0x00000000) |
| 671 |
#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UnicastFramesFilter_PerfectHashTable) || \
|
| 672 |
((FILTER) == ETH_UnicastFramesFilter_HashTable) || \ |
| 673 |
((FILTER) == ETH_UnicastFramesFilter_Perfect)) |
| 674 |
|
| 675 |
/**
|
| 676 |
* @}
|
| 677 |
*/
|
| 678 |
|
| 679 |
/** @defgroup ETH_Pause_Time
|
| 680 |
* @{
|
| 681 |
*/
|
| 682 |
#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF) |
| 683 |
|
| 684 |
/**
|
| 685 |
* @}
|
| 686 |
*/
|
| 687 |
|
| 688 |
/** @defgroup ETH_Zero_Quanta_Pause
|
| 689 |
* @{
|
| 690 |
*/
|
| 691 |
#define ETH_ZeroQuantaPause_Enable ((uint32_t)0x00000000) |
| 692 |
#define ETH_ZeroQuantaPause_Disable ((uint32_t)0x00000080) |
| 693 |
#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZeroQuantaPause_Enable) || \
|
| 694 |
((CMD) == ETH_ZeroQuantaPause_Disable)) |
| 695 |
/**
|
| 696 |
* @}
|
| 697 |
*/
|
| 698 |
|
| 699 |
/** @defgroup ETH_Pause_Low_Threshold
|
| 700 |
* @{
|
| 701 |
*/
|
| 702 |
#define ETH_PauseLowThreshold_Minus4 ((uint32_t)0x00000000) /*!< Pause time minus 4 slot times */ |
| 703 |
#define ETH_PauseLowThreshold_Minus28 ((uint32_t)0x00000010) /*!< Pause time minus 28 slot times */ |
| 704 |
#define ETH_PauseLowThreshold_Minus144 ((uint32_t)0x00000020) /*!< Pause time minus 144 slot times */ |
| 705 |
#define ETH_PauseLowThreshold_Minus256 ((uint32_t)0x00000030) /*!< Pause time minus 256 slot times */ |
| 706 |
#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PauseLowThreshold_Minus4) || \
|
| 707 |
((THRESHOLD) == ETH_PauseLowThreshold_Minus28) || \ |
| 708 |
((THRESHOLD) == ETH_PauseLowThreshold_Minus144) || \ |
| 709 |
((THRESHOLD) == ETH_PauseLowThreshold_Minus256)) |
| 710 |
|
| 711 |
/**
|
| 712 |
* @}
|
| 713 |
*/
|
| 714 |
|
| 715 |
/** @defgroup ETH_Unicast_Pause_Frame_Detect
|
| 716 |
* @{
|
| 717 |
*/
|
| 718 |
#define ETH_UnicastPauseFrameDetect_Enable ((uint32_t)0x00000008) |
| 719 |
#define ETH_UnicastPauseFrameDetect_Disable ((uint32_t)0x00000000) |
| 720 |
#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UnicastPauseFrameDetect_Enable) || \
|
| 721 |
((CMD) == ETH_UnicastPauseFrameDetect_Disable)) |
| 722 |
|
| 723 |
/**
|
| 724 |
* @}
|
| 725 |
*/
|
| 726 |
|
| 727 |
/** @defgroup ETH_Receive_Flow_Control
|
| 728 |
* @{
|
| 729 |
*/
|
| 730 |
#define ETH_ReceiveFlowControl_Enable ((uint32_t)0x00000004) |
| 731 |
#define ETH_ReceiveFlowControl_Disable ((uint32_t)0x00000000) |
| 732 |
#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_ReceiveFlowControl_Enable) || \
|
| 733 |
((CMD) == ETH_ReceiveFlowControl_Disable)) |
| 734 |
|
| 735 |
/**
|
| 736 |
* @}
|
| 737 |
*/
|
| 738 |
|
| 739 |
/** @defgroup ETH_Transmit_Flow_Control
|
| 740 |
* @{
|
| 741 |
*/
|
| 742 |
#define ETH_TransmitFlowControl_Enable ((uint32_t)0x00000002) |
| 743 |
#define ETH_TransmitFlowControl_Disable ((uint32_t)0x00000000) |
| 744 |
#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TransmitFlowControl_Enable) || \
|
| 745 |
((CMD) == ETH_TransmitFlowControl_Disable)) |
| 746 |
|
| 747 |
/**
|
| 748 |
* @}
|
| 749 |
*/
|
| 750 |
|
| 751 |
/** @defgroup ETH_VLAN_Tag_Comparison
|
| 752 |
* @{
|
| 753 |
*/
|
| 754 |
#define ETH_VLANTagComparison_12Bit ((uint32_t)0x00010000) |
| 755 |
#define ETH_VLANTagComparison_16Bit ((uint32_t)0x00000000) |
| 756 |
#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTagComparison_12Bit) || \
|
| 757 |
((COMPARISON) == ETH_VLANTagComparison_16Bit)) |
| 758 |
#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF) |
| 759 |
|
| 760 |
/**
|
| 761 |
* @}
|
| 762 |
*/
|
| 763 |
|
| 764 |
/** @defgroup ETH_MAC_Flags
|
| 765 |
* @{
|
| 766 |
*/
|
| 767 |
#define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /*!< Time stamp trigger flag (on MAC) */ |
| 768 |
#define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040) /*!< MMC transmit flag */ |
| 769 |
#define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /*!< MMC receive flag */ |
| 770 |
#define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /*!< MMC flag (on MAC) */ |
| 771 |
#define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /*!< PMT flag (on MAC) */ |
| 772 |
#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \
|
| 773 |
((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \ |
| 774 |
((FLAG) == ETH_MAC_FLAG_PMT)) |
| 775 |
/**
|
| 776 |
* @}
|
| 777 |
*/
|
| 778 |
|
| 779 |
/** @defgroup ETH_MAC_Interrupts
|
| 780 |
* @{
|
| 781 |
*/
|
| 782 |
#define ETH_MAC_IT_TST ((uint32_t)0x00000200) /*!< Time stamp trigger interrupt (on MAC) */ |
| 783 |
#define ETH_MAC_IT_MMCT ((uint32_t)0x00000040) /*!< MMC transmit interrupt */ |
| 784 |
#define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /*!< MMC receive interrupt */ |
| 785 |
#define ETH_MAC_IT_MMC ((uint32_t)0x00000010) /*!< MMC interrupt (on MAC) */ |
| 786 |
#define ETH_MAC_IT_PMT ((uint32_t)0x00000008) /*!< PMT interrupt (on MAC) */ |
| 787 |
#define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF7) == 0x00) && ((IT) != 0x00)) |
| 788 |
#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \
|
| 789 |
((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \ |
| 790 |
((IT) == ETH_MAC_IT_PMT)) |
| 791 |
/**
|
| 792 |
* @}
|
| 793 |
*/
|
| 794 |
|
| 795 |
/** @defgroup ETH_MAC_addresses
|
| 796 |
* @{
|
| 797 |
*/
|
| 798 |
#define ETH_MAC_Address0 ((uint32_t)0x00000000) |
| 799 |
#define ETH_MAC_Address1 ((uint32_t)0x00000008) |
| 800 |
#define ETH_MAC_Address2 ((uint32_t)0x00000010) |
| 801 |
#define ETH_MAC_Address3 ((uint32_t)0x00000018) |
| 802 |
#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_Address0) || \
|
| 803 |
((ADDRESS) == ETH_MAC_Address1) || \ |
| 804 |
((ADDRESS) == ETH_MAC_Address2) || \ |
| 805 |
((ADDRESS) == ETH_MAC_Address3)) |
| 806 |
#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_Address1) || \
|
| 807 |
((ADDRESS) == ETH_MAC_Address2) || \ |
| 808 |
((ADDRESS) == ETH_MAC_Address3)) |
| 809 |
/**
|
| 810 |
* @}
|
| 811 |
*/
|
| 812 |
|
| 813 |
/** @defgroup ETH_MAC_addresses_filter:_SA_DA_filed_of_received_frames
|
| 814 |
* @{
|
| 815 |
*/
|
| 816 |
#define ETH_MAC_AddressFilter_SA ((uint32_t)0x00000000) |
| 817 |
#define ETH_MAC_AddressFilter_DA ((uint32_t)0x00000008) |
| 818 |
#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_AddressFilter_SA) || \
|
| 819 |
((FILTER) == ETH_MAC_AddressFilter_DA)) |
| 820 |
/**
|
| 821 |
* @}
|
| 822 |
*/
|
| 823 |
|
| 824 |
/** @defgroup ETH_MAC_addresses_filter:_Mask_bytes
|
| 825 |
* @{
|
| 826 |
*/
|
| 827 |
#define ETH_MAC_AddressMask_Byte6 ((uint32_t)0x20000000) /*!< Mask MAC Address high reg bits [15:8] */ |
| 828 |
#define ETH_MAC_AddressMask_Byte5 ((uint32_t)0x10000000) /*!< Mask MAC Address high reg bits [7:0] */ |
| 829 |
#define ETH_MAC_AddressMask_Byte4 ((uint32_t)0x08000000) /*!< Mask MAC Address low reg bits [31:24] */ |
| 830 |
#define ETH_MAC_AddressMask_Byte3 ((uint32_t)0x04000000) /*!< Mask MAC Address low reg bits [23:16] */ |
| 831 |
#define ETH_MAC_AddressMask_Byte2 ((uint32_t)0x02000000) /*!< Mask MAC Address low reg bits [15:8] */ |
| 832 |
#define ETH_MAC_AddressMask_Byte1 ((uint32_t)0x01000000) /*!< Mask MAC Address low reg bits [70] */ |
| 833 |
#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_AddressMask_Byte6) || \
|
| 834 |
((MASK) == ETH_MAC_AddressMask_Byte5) || \ |
| 835 |
((MASK) == ETH_MAC_AddressMask_Byte4) || \ |
| 836 |
((MASK) == ETH_MAC_AddressMask_Byte3) || \ |
| 837 |
((MASK) == ETH_MAC_AddressMask_Byte2) || \ |
| 838 |
((MASK) == ETH_MAC_AddressMask_Byte1)) |
| 839 |
|
| 840 |
/**--------------------------------------------------------------------------**/
|
| 841 |
/**
|
| 842 |
* @brief Ethernet DMA Desciptors defines
|
| 843 |
*/
|
| 844 |
/**--------------------------------------------------------------------------**/
|
| 845 |
/**
|
| 846 |
* @}
|
| 847 |
*/
|
| 848 |
|
| 849 |
/** @defgroup ETH_DMA_Tx_descriptor_flags
|
| 850 |
* @{
|
| 851 |
*/
|
| 852 |
#define IS_ETH_DMATxDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATxDesc_OWN) || \
|
| 853 |
((FLAG) == ETH_DMATxDesc_IC) || \ |
| 854 |
((FLAG) == ETH_DMATxDesc_LS) || \ |
| 855 |
((FLAG) == ETH_DMATxDesc_FS) || \ |
| 856 |
((FLAG) == ETH_DMATxDesc_DC) || \ |
| 857 |
((FLAG) == ETH_DMATxDesc_DP) || \ |
| 858 |
((FLAG) == ETH_DMATxDesc_TTSE) || \ |
| 859 |
((FLAG) == ETH_DMATxDesc_TER) || \ |
| 860 |
((FLAG) == ETH_DMATxDesc_TCH) || \ |
| 861 |
((FLAG) == ETH_DMATxDesc_TTSS) || \ |
| 862 |
((FLAG) == ETH_DMATxDesc_IHE) || \ |
| 863 |
((FLAG) == ETH_DMATxDesc_ES) || \ |
| 864 |
((FLAG) == ETH_DMATxDesc_JT) || \ |
| 865 |
((FLAG) == ETH_DMATxDesc_FF) || \ |
| 866 |
((FLAG) == ETH_DMATxDesc_PCE) || \ |
| 867 |
((FLAG) == ETH_DMATxDesc_LCA) || \ |
| 868 |
((FLAG) == ETH_DMATxDesc_NC) || \ |
| 869 |
((FLAG) == ETH_DMATxDesc_LCO) || \ |
| 870 |
((FLAG) == ETH_DMATxDesc_EC) || \ |
| 871 |
((FLAG) == ETH_DMATxDesc_VF) || \ |
| 872 |
((FLAG) == ETH_DMATxDesc_CC) || \ |
| 873 |
((FLAG) == ETH_DMATxDesc_ED) || \ |
| 874 |
((FLAG) == ETH_DMATxDesc_UF) || \ |
| 875 |
((FLAG) == ETH_DMATxDesc_DB)) |
| 876 |
|
| 877 |
/**
|
| 878 |
* @}
|
| 879 |
*/
|
| 880 |
|
| 881 |
/** @defgroup ETH_DMA_Tx_descriptor_segment
|
| 882 |
* @{
|
| 883 |
*/
|
| 884 |
#define ETH_DMATxDesc_LastSegment ((uint32_t)0x40000000) /*!< Last Segment */ |
| 885 |
#define ETH_DMATxDesc_FirstSegment ((uint32_t)0x20000000) /*!< First Segment */ |
| 886 |
#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATxDesc_LastSegment) || \
|
| 887 |
((SEGMENT) == ETH_DMATxDesc_FirstSegment)) |
| 888 |
|
| 889 |
/**
|
| 890 |
* @}
|
| 891 |
*/
|
| 892 |
|
| 893 |
/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control
|
| 894 |
* @{
|
| 895 |
*/
|
| 896 |
#define ETH_DMATxDesc_ChecksumByPass ((uint32_t)0x00000000) /*!< Checksum engine bypass */ |
| 897 |
#define ETH_DMATxDesc_ChecksumIPV4Header ((uint32_t)0x00400000) /*!< IPv4 header checksum insertion */ |
| 898 |
#define ETH_DMATxDesc_ChecksumTCPUDPICMPSegment ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */ |
| 899 |
#define ETH_DMATxDesc_ChecksumTCPUDPICMPFull ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */ |
| 900 |
#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATxDesc_ChecksumByPass) || \
|
| 901 |
((CHECKSUM) == ETH_DMATxDesc_ChecksumIPV4Header) || \ |
| 902 |
((CHECKSUM) == ETH_DMATxDesc_ChecksumTCPUDPICMPSegment) || \ |
| 903 |
((CHECKSUM) == ETH_DMATxDesc_ChecksumTCPUDPICMPFull)) |
| 904 |
/**
|
| 905 |
* @brief ETH DMA Tx Desciptor buffer size
|
| 906 |
*/
|
| 907 |
#define IS_ETH_DMATxDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF) |
| 908 |
|
| 909 |
/**
|
| 910 |
* @}
|
| 911 |
*/
|
| 912 |
|
| 913 |
/** @defgroup ETH_DMA_Rx_descriptor_flags
|
| 914 |
* @{
|
| 915 |
*/
|
| 916 |
#define IS_ETH_DMARxDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARxDesc_OWN) || \
|
| 917 |
((FLAG) == ETH_DMARxDesc_AFM) || \ |
| 918 |
((FLAG) == ETH_DMARxDesc_ES) || \ |
| 919 |
((FLAG) == ETH_DMARxDesc_DE) || \ |
| 920 |
((FLAG) == ETH_DMARxDesc_SAF) || \ |
| 921 |
((FLAG) == ETH_DMARxDesc_LE) || \ |
| 922 |
((FLAG) == ETH_DMARxDesc_OE) || \ |
| 923 |
((FLAG) == ETH_DMARxDesc_VLAN) || \ |
| 924 |
((FLAG) == ETH_DMARxDesc_FS) || \ |
| 925 |
((FLAG) == ETH_DMARxDesc_LS) || \ |
| 926 |
((FLAG) == ETH_DMARxDesc_IPV4HCE) || \ |
| 927 |
((FLAG) == ETH_DMARxDesc_LC) || \ |
| 928 |
((FLAG) == ETH_DMARxDesc_FT) || \ |
| 929 |
((FLAG) == ETH_DMARxDesc_RWT) || \ |
| 930 |
((FLAG) == ETH_DMARxDesc_RE) || \ |
| 931 |
((FLAG) == ETH_DMARxDesc_DBE) || \ |
| 932 |
((FLAG) == ETH_DMARxDesc_CE) || \ |
| 933 |
((FLAG) == ETH_DMARxDesc_MAMPCE)) |
| 934 |
|
| 935 |
/**
|
| 936 |
* @}
|
| 937 |
*/
|
| 938 |
|
| 939 |
/** @defgroup ETH_DMA_Rx_descriptor_buffers_
|
| 940 |
* @{
|
| 941 |
*/
|
| 942 |
#define ETH_DMARxDesc_Buffer1 ((uint32_t)0x00000000) /*!< DMA Rx Desc Buffer1 */ |
| 943 |
#define ETH_DMARxDesc_Buffer2 ((uint32_t)0x00000001) /*!< DMA Rx Desc Buffer2 */ |
| 944 |
#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARxDesc_Buffer1) || \
|
| 945 |
((BUFFER) == ETH_DMARxDesc_Buffer2)) |
| 946 |
|
| 947 |
/**--------------------------------------------------------------------------**/
|
| 948 |
/**
|
| 949 |
* @brief Ethernet DMA defines
|
| 950 |
*/
|
| 951 |
/**--------------------------------------------------------------------------**/
|
| 952 |
/**
|
| 953 |
* @}
|
| 954 |
*/
|
| 955 |
|
| 956 |
/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame
|
| 957 |
* @{
|
| 958 |
*/
|
| 959 |
#define ETH_DropTCPIPChecksumErrorFrame_Enable ((uint32_t)0x00000000) |
| 960 |
#define ETH_DropTCPIPChecksumErrorFrame_Disable ((uint32_t)0x04000000) |
| 961 |
#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DropTCPIPChecksumErrorFrame_Enable) || \
|
| 962 |
((CMD) == ETH_DropTCPIPChecksumErrorFrame_Disable)) |
| 963 |
/**
|
| 964 |
* @}
|
| 965 |
*/
|
| 966 |
|
| 967 |
/** @defgroup ETH_Receive_Store_Forward
|
| 968 |
* @{
|
| 969 |
*/
|
| 970 |
#define ETH_ReceiveStoreForward_Enable ((uint32_t)0x02000000) |
| 971 |
#define ETH_ReceiveStoreForward_Disable ((uint32_t)0x00000000) |
| 972 |
#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_ReceiveStoreForward_Enable) || \
|
| 973 |
((CMD) == ETH_ReceiveStoreForward_Disable)) |
| 974 |
/**
|
| 975 |
* @}
|
| 976 |
*/
|
| 977 |
|
| 978 |
/** @defgroup ETH_Flush_Received_Frame
|
| 979 |
* @{
|
| 980 |
*/
|
| 981 |
#define ETH_FlushReceivedFrame_Enable ((uint32_t)0x00000000) |
| 982 |
#define ETH_FlushReceivedFrame_Disable ((uint32_t)0x01000000) |
| 983 |
#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FlushReceivedFrame_Enable) || \
|
| 984 |
((CMD) == ETH_FlushReceivedFrame_Disable)) |
| 985 |
/**
|
| 986 |
* @}
|
| 987 |
*/
|
| 988 |
|
| 989 |
/** @defgroup ETH_Transmit_Store_Forward
|
| 990 |
* @{
|
| 991 |
*/
|
| 992 |
#define ETH_TransmitStoreForward_Enable ((uint32_t)0x00200000) |
| 993 |
#define ETH_TransmitStoreForward_Disable ((uint32_t)0x00000000) |
| 994 |
#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TransmitStoreForward_Enable) || \
|
| 995 |
((CMD) == ETH_TransmitStoreForward_Disable)) |
| 996 |
/**
|
| 997 |
* @}
|
| 998 |
*/
|
| 999 |
|
| 1000 |
/** @defgroup ETH_Transmit_Threshold_Control
|
| 1001 |
* @{
|
| 1002 |
*/
|
| 1003 |
#define ETH_TransmitThresholdControl_64Bytes ((uint32_t)0x00000000) /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */ |
| 1004 |
#define ETH_TransmitThresholdControl_128Bytes ((uint32_t)0x00004000) /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */ |
| 1005 |
#define ETH_TransmitThresholdControl_192Bytes ((uint32_t)0x00008000) /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */ |
| 1006 |
#define ETH_TransmitThresholdControl_256Bytes ((uint32_t)0x0000C000) /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */ |
| 1007 |
#define ETH_TransmitThresholdControl_40Bytes ((uint32_t)0x00010000) /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */ |
| 1008 |
#define ETH_TransmitThresholdControl_32Bytes ((uint32_t)0x00014000) /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */ |
| 1009 |
#define ETH_TransmitThresholdControl_24Bytes ((uint32_t)0x00018000) /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */ |
| 1010 |
#define ETH_TransmitThresholdControl_16Bytes ((uint32_t)0x0001C000) /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */ |
| 1011 |
#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TransmitThresholdControl_64Bytes) || \
|
| 1012 |
((THRESHOLD) == ETH_TransmitThresholdControl_128Bytes) || \ |
| 1013 |
((THRESHOLD) == ETH_TransmitThresholdControl_192Bytes) || \ |
| 1014 |
((THRESHOLD) == ETH_TransmitThresholdControl_256Bytes) || \ |
| 1015 |
((THRESHOLD) == ETH_TransmitThresholdControl_40Bytes) || \ |
| 1016 |
((THRESHOLD) == ETH_TransmitThresholdControl_32Bytes) || \ |
| 1017 |
((THRESHOLD) == ETH_TransmitThresholdControl_24Bytes) || \ |
| 1018 |
((THRESHOLD) == ETH_TransmitThresholdControl_16Bytes)) |
| 1019 |
/**
|
| 1020 |
* @}
|
| 1021 |
*/
|
| 1022 |
|
| 1023 |
/** @defgroup ETH_Forward_Error_Frames
|
| 1024 |
* @{
|
| 1025 |
*/
|
| 1026 |
#define ETH_ForwardErrorFrames_Enable ((uint32_t)0x00000080) |
| 1027 |
#define ETH_ForwardErrorFrames_Disable ((uint32_t)0x00000000) |
| 1028 |
#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_ForwardErrorFrames_Enable) || \
|
| 1029 |
((CMD) == ETH_ForwardErrorFrames_Disable)) |
| 1030 |
/**
|
| 1031 |
* @}
|
| 1032 |
*/
|
| 1033 |
|
| 1034 |
/** @defgroup ETH_Forward_Undersized_Good_Frames
|
| 1035 |
* @{
|
| 1036 |
*/
|
| 1037 |
#define ETH_ForwardUndersizedGoodFrames_Enable ((uint32_t)0x00000040) |
| 1038 |
#define ETH_ForwardUndersizedGoodFrames_Disable ((uint32_t)0x00000000) |
| 1039 |
#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_ForwardUndersizedGoodFrames_Enable) || \
|
| 1040 |
((CMD) == ETH_ForwardUndersizedGoodFrames_Disable)) |
| 1041 |
|
| 1042 |
/**
|
| 1043 |
* @}
|
| 1044 |
*/
|
| 1045 |
|
| 1046 |
/** @defgroup ETH_Receive_Threshold_Control
|
| 1047 |
* @{
|
| 1048 |
*/
|
| 1049 |
#define ETH_ReceiveThresholdControl_64Bytes ((uint32_t)0x00000000) /*!< threshold level of the MTL Receive FIFO is 64 Bytes */ |
| 1050 |
#define ETH_ReceiveThresholdControl_32Bytes ((uint32_t)0x00000008) /*!< threshold level of the MTL Receive FIFO is 32 Bytes */ |
| 1051 |
#define ETH_ReceiveThresholdControl_96Bytes ((uint32_t)0x00000010) /*!< threshold level of the MTL Receive FIFO is 96 Bytes */ |
| 1052 |
#define ETH_ReceiveThresholdControl_128Bytes ((uint32_t)0x00000018) /*!< threshold level of the MTL Receive FIFO is 128 Bytes */ |
| 1053 |
#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_ReceiveThresholdControl_64Bytes) || \
|
| 1054 |
((THRESHOLD) == ETH_ReceiveThresholdControl_32Bytes) || \ |
| 1055 |
((THRESHOLD) == ETH_ReceiveThresholdControl_96Bytes) || \ |
| 1056 |
((THRESHOLD) == ETH_ReceiveThresholdControl_128Bytes)) |
| 1057 |
/**
|
| 1058 |
* @}
|
| 1059 |
*/
|
| 1060 |
|
| 1061 |
/** @defgroup ETH_Second_Frame_Operate
|
| 1062 |
* @{
|
| 1063 |
*/
|
| 1064 |
#define ETH_SecondFrameOperate_Enable ((uint32_t)0x00000004) |
| 1065 |
#define ETH_SecondFrameOperate_Disable ((uint32_t)0x00000000) |
| 1066 |
#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SecondFrameOperate_Enable) || \
|
| 1067 |
((CMD) == ETH_SecondFrameOperate_Disable)) |
| 1068 |
|
| 1069 |
/**
|
| 1070 |
* @}
|
| 1071 |
*/
|
| 1072 |
|
| 1073 |
/** @defgroup ETH_Address_Aligned_Beats
|
| 1074 |
* @{
|
| 1075 |
*/
|
| 1076 |
#define ETH_AddressAlignedBeats_Enable ((uint32_t)0x02000000) |
| 1077 |
#define ETH_AddressAlignedBeats_Disable ((uint32_t)0x00000000) |
| 1078 |
#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_AddressAlignedBeats_Enable) || \
|
| 1079 |
((CMD) == ETH_AddressAlignedBeats_Disable)) |
| 1080 |
|
| 1081 |
/**
|
| 1082 |
* @}
|
| 1083 |
*/
|
| 1084 |
|
| 1085 |
/** @defgroup ETH_Fixed_Burst
|
| 1086 |
* @{
|
| 1087 |
*/
|
| 1088 |
#define ETH_FixedBurst_Enable ((uint32_t)0x00010000) |
| 1089 |
#define ETH_FixedBurst_Disable ((uint32_t)0x00000000) |
| 1090 |
#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FixedBurst_Enable) || \
|
| 1091 |
((CMD) == ETH_FixedBurst_Disable)) |
| 1092 |
|
| 1093 |
/**
|
| 1094 |
* @}
|
| 1095 |
*/
|
| 1096 |
|
| 1097 |
/** @defgroup ETH_Rx_DMA_Burst_Length
|
| 1098 |
* @{
|
| 1099 |
*/
|
| 1100 |
#define ETH_RxDMABurstLength_1Beat ((uint32_t)0x00020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */ |
| 1101 |
#define ETH_RxDMABurstLength_2Beat ((uint32_t)0x00040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */ |
| 1102 |
#define ETH_RxDMABurstLength_4Beat ((uint32_t)0x00080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ |
| 1103 |
#define ETH_RxDMABurstLength_8Beat ((uint32_t)0x00100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ |
| 1104 |
#define ETH_RxDMABurstLength_16Beat ((uint32_t)0x00200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ |
| 1105 |
#define ETH_RxDMABurstLength_32Beat ((uint32_t)0x00400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ |
| 1106 |
#define ETH_RxDMABurstLength_4xPBL_4Beat ((uint32_t)0x01020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ |
| 1107 |
#define ETH_RxDMABurstLength_4xPBL_8Beat ((uint32_t)0x01040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ |
| 1108 |
#define ETH_RxDMABurstLength_4xPBL_16Beat ((uint32_t)0x01080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ |
| 1109 |
#define ETH_RxDMABurstLength_4xPBL_32Beat ((uint32_t)0x01100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ |
| 1110 |
#define ETH_RxDMABurstLength_4xPBL_64Beat ((uint32_t)0x01200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */ |
| 1111 |
#define ETH_RxDMABurstLength_4xPBL_128Beat ((uint32_t)0x01400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */ |
| 1112 |
#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RxDMABurstLength_1Beat) || \
|
| 1113 |
((LENGTH) == ETH_RxDMABurstLength_2Beat) || \ |
| 1114 |
((LENGTH) == ETH_RxDMABurstLength_4Beat) || \ |
| 1115 |
((LENGTH) == ETH_RxDMABurstLength_8Beat) || \ |
| 1116 |
((LENGTH) == ETH_RxDMABurstLength_16Beat) || \ |
| 1117 |
((LENGTH) == ETH_RxDMABurstLength_32Beat) || \ |
| 1118 |
((LENGTH) == ETH_RxDMABurstLength_4xPBL_4Beat) || \ |
| 1119 |
((LENGTH) == ETH_RxDMABurstLength_4xPBL_8Beat) || \ |
| 1120 |
((LENGTH) == ETH_RxDMABurstLength_4xPBL_16Beat) || \ |
| 1121 |
((LENGTH) == ETH_RxDMABurstLength_4xPBL_32Beat) || \ |
| 1122 |
((LENGTH) == ETH_RxDMABurstLength_4xPBL_64Beat) || \ |
| 1123 |
((LENGTH) == ETH_RxDMABurstLength_4xPBL_128Beat)) |
| 1124 |
|
| 1125 |
/**
|
| 1126 |
* @}
|
| 1127 |
*/
|
| 1128 |
|
| 1129 |
/** @defgroup ETH_Tx_DMA_Burst_Length
|
| 1130 |
* @{
|
| 1131 |
*/
|
| 1132 |
#define ETH_TxDMABurstLength_1Beat ((uint32_t)0x00000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ |
| 1133 |
#define ETH_TxDMABurstLength_2Beat ((uint32_t)0x00000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ |
| 1134 |
#define ETH_TxDMABurstLength_4Beat ((uint32_t)0x00000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ |
| 1135 |
#define ETH_TxDMABurstLength_8Beat ((uint32_t)0x00000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ |
| 1136 |
#define ETH_TxDMABurstLength_16Beat ((uint32_t)0x00001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ |
| 1137 |
#define ETH_TxDMABurstLength_32Beat ((uint32_t)0x00002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ |
| 1138 |
#define ETH_TxDMABurstLength_4xPBL_4Beat ((uint32_t)0x01000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ |
| 1139 |
#define ETH_TxDMABurstLength_4xPBL_8Beat ((uint32_t)0x01000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ |
| 1140 |
#define ETH_TxDMABurstLength_4xPBL_16Beat ((uint32_t)0x01000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ |
| 1141 |
#define ETH_TxDMABurstLength_4xPBL_32Beat ((uint32_t)0x01000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ |
| 1142 |
#define ETH_TxDMABurstLength_4xPBL_64Beat ((uint32_t)0x01001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ |
| 1143 |
#define ETH_TxDMABurstLength_4xPBL_128Beat ((uint32_t)0x01002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ |
| 1144 |
#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TxDMABurstLength_1Beat) || \
|
| 1145 |
((LENGTH) == ETH_TxDMABurstLength_2Beat) || \ |
| 1146 |
((LENGTH) == ETH_TxDMABurstLength_4Beat) || \ |
| 1147 |
((LENGTH) == ETH_TxDMABurstLength_8Beat) || \ |
| 1148 |
((LENGTH) == ETH_TxDMABurstLength_16Beat) || \ |
| 1149 |
((LENGTH) == ETH_TxDMABurstLength_32Beat) || \ |
| 1150 |
((LENGTH) == ETH_TxDMABurstLength_4xPBL_4Beat) || \ |
| 1151 |
((LENGTH) == ETH_TxDMABurstLength_4xPBL_8Beat) || \ |
| 1152 |
((LENGTH) == ETH_TxDMABurstLength_4xPBL_16Beat) || \ |
| 1153 |
((LENGTH) == ETH_TxDMABurstLength_4xPBL_32Beat) || \ |
| 1154 |
((LENGTH) == ETH_TxDMABurstLength_4xPBL_64Beat) || \ |
| 1155 |
((LENGTH) == ETH_TxDMABurstLength_4xPBL_128Beat)) |
| 1156 |
/**
|
| 1157 |
* @brief ETH DMA Desciptor SkipLength
|
| 1158 |
*/
|
| 1159 |
#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F) |
| 1160 |
|
| 1161 |
/**
|
| 1162 |
* @}
|
| 1163 |
*/
|
| 1164 |
|
| 1165 |
/** @defgroup ETH_DMA_Arbitration
|
| 1166 |
* @{
|
| 1167 |
*/
|
| 1168 |
#define ETH_DMAArbitration_RoundRobin_RxTx_1_1 ((uint32_t)0x00000000) |
| 1169 |
#define ETH_DMAArbitration_RoundRobin_RxTx_2_1 ((uint32_t)0x00004000) |
| 1170 |
#define ETH_DMAArbitration_RoundRobin_RxTx_3_1 ((uint32_t)0x00008000) |
| 1171 |
#define ETH_DMAArbitration_RoundRobin_RxTx_4_1 ((uint32_t)0x0000C000) |
| 1172 |
#define ETH_DMAArbitration_RxPriorTx ((uint32_t)0x00000002) |
| 1173 |
#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_1_1) || \
|
| 1174 |
((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_2_1) || \ |
| 1175 |
((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_3_1) || \ |
| 1176 |
((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_4_1) || \ |
| 1177 |
((RATIO) == ETH_DMAArbitration_RxPriorTx)) |
| 1178 |
/**
|
| 1179 |
* @}
|
| 1180 |
*/
|
| 1181 |
|
| 1182 |
/** @defgroup ETH_DMA_Flags
|
| 1183 |
* @{
|
| 1184 |
*/
|
| 1185 |
#define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */ |
| 1186 |
#define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */ |
| 1187 |
#define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */ |
| 1188 |
#define ETH_DMA_FLAG_DataTransferError ((uint32_t)0x00800000) /*!< Error bits 0-Rx DMA, 1-Tx DMA */ |
| 1189 |
#define ETH_DMA_FLAG_ReadWriteError ((uint32_t)0x01000000) /*!< Error bits 0-write trnsf, 1-read transfr */ |
| 1190 |
#define ETH_DMA_FLAG_AccessError ((uint32_t)0x02000000) /*!< Error bits 0-data buffer, 1-desc. access */ |
| 1191 |
#define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary flag */ |
| 1192 |
#define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary flag */ |
| 1193 |
#define ETH_DMA_FLAG_ER ((uint32_t)0x00004000) /*!< Early receive flag */ |
| 1194 |
#define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000) /*!< Fatal bus error flag */ |
| 1195 |
#define ETH_DMA_FLAG_ET ((uint32_t)0x00000400) /*!< Early transmit flag */ |
| 1196 |
#define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout flag */ |
| 1197 |
#define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100) /*!< Receive process stopped flag */ |
| 1198 |
#define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable flag */ |
| 1199 |
#define ETH_DMA_FLAG_R ((uint32_t)0x00000040) /*!< Receive flag */ |
| 1200 |
#define ETH_DMA_FLAG_TU ((uint32_t)0x00000020) /*!< Underflow flag */ |
| 1201 |
#define ETH_DMA_FLAG_RO ((uint32_t)0x00000010) /*!< Overflow flag */ |
| 1202 |
#define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout flag */ |
| 1203 |
#define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable flag */ |
| 1204 |
#define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped flag */ |
| 1205 |
#define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /*!< Transmit flag */ |
| 1206 |
|
| 1207 |
#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFE1800) == 0x00) && ((FLAG) != 0x00)) |
| 1208 |
#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \
|
| 1209 |
((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DataTransferError) || \ |
| 1210 |
((FLAG) == ETH_DMA_FLAG_ReadWriteError) || ((FLAG) == ETH_DMA_FLAG_AccessError) || \ |
| 1211 |
((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \ |
| 1212 |
((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \ |
| 1213 |
((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \ |
| 1214 |
((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \ |
| 1215 |
((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \ |
| 1216 |
((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \ |
| 1217 |
((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \ |
| 1218 |
((FLAG) == ETH_DMA_FLAG_T)) |
| 1219 |
/**
|
| 1220 |
* @}
|
| 1221 |
*/
|
| 1222 |
|
| 1223 |
/** @defgroup ETH_DMA_Interrupts
|
| 1224 |
* @{
|
| 1225 |
*/
|
| 1226 |
#define ETH_DMA_IT_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */ |
| 1227 |
#define ETH_DMA_IT_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */ |
| 1228 |
#define ETH_DMA_IT_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */ |
| 1229 |
#define ETH_DMA_IT_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary */ |
| 1230 |
#define ETH_DMA_IT_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary */ |
| 1231 |
#define ETH_DMA_IT_ER ((uint32_t)0x00004000) /*!< Early receive interrupt */ |
| 1232 |
#define ETH_DMA_IT_FBE ((uint32_t)0x00002000) /*!< Fatal bus error interrupt */ |
| 1233 |
#define ETH_DMA_IT_ET ((uint32_t)0x00000400) /*!< Early transmit interrupt */ |
| 1234 |
#define ETH_DMA_IT_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout interrupt */ |
| 1235 |
#define ETH_DMA_IT_RPS ((uint32_t)0x00000100) /*!< Receive process stopped interrupt */ |
| 1236 |
#define ETH_DMA_IT_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable interrupt */ |
| 1237 |
#define ETH_DMA_IT_R ((uint32_t)0x00000040) /*!< Receive interrupt */ |
| 1238 |
#define ETH_DMA_IT_TU ((uint32_t)0x00000020) /*!< Underflow interrupt */ |
| 1239 |
#define ETH_DMA_IT_RO ((uint32_t)0x00000010) /*!< Overflow interrupt */ |
| 1240 |
#define ETH_DMA_IT_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout interrupt */ |
| 1241 |
#define ETH_DMA_IT_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable interrupt */ |
| 1242 |
#define ETH_DMA_IT_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped interrupt */ |
| 1243 |
#define ETH_DMA_IT_T ((uint32_t)0x00000001) /*!< Transmit interrupt */ |
| 1244 |
|
| 1245 |
#define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xFFFE1800) == 0x00) && ((IT) != 0x00)) |
| 1246 |
#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \
|
| 1247 |
((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \ |
| 1248 |
((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \ |
| 1249 |
((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \ |
| 1250 |
((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \ |
| 1251 |
((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \ |
| 1252 |
((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \ |
| 1253 |
((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \ |
| 1254 |
((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T)) |
| 1255 |
|
| 1256 |
/**
|
| 1257 |
* @}
|
| 1258 |
*/
|
| 1259 |
|
| 1260 |
/** @defgroup ETH_DMA_transmit_process_state_
|
| 1261 |
* @{
|
| 1262 |
*/
|
| 1263 |
#define ETH_DMA_TransmitProcess_Stopped ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Tx Command issued */ |
| 1264 |
#define ETH_DMA_TransmitProcess_Fetching ((uint32_t)0x00100000) /*!< Running - fetching the Tx descriptor */ |
| 1265 |
#define ETH_DMA_TransmitProcess_Waiting ((uint32_t)0x00200000) /*!< Running - waiting for status */ |
| 1266 |
#define ETH_DMA_TransmitProcess_Reading ((uint32_t)0x00300000) /*!< Running - reading the data from host memory */ |
| 1267 |
#define ETH_DMA_TransmitProcess_Suspended ((uint32_t)0x00600000) /*!< Suspended - Tx Desciptor unavailabe */ |
| 1268 |
#define ETH_DMA_TransmitProcess_Closing ((uint32_t)0x00700000) /*!< Running - closing Rx descriptor */ |
| 1269 |
|
| 1270 |
/**
|
| 1271 |
* @}
|
| 1272 |
*/
|
| 1273 |
|
| 1274 |
|
| 1275 |
/** @defgroup ETH_DMA_receive_process_state_
|
| 1276 |
* @{
|
| 1277 |
*/
|
| 1278 |
#define ETH_DMA_ReceiveProcess_Stopped ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Rx Command issued */ |
| 1279 |
#define ETH_DMA_ReceiveProcess_Fetching ((uint32_t)0x00020000) /*!< Running - fetching the Rx descriptor */ |
| 1280 |
#define ETH_DMA_ReceiveProcess_Waiting ((uint32_t)0x00060000) /*!< Running - waiting for packet */ |
| 1281 |
#define ETH_DMA_ReceiveProcess_Suspended ((uint32_t)0x00080000) /*!< Suspended - Rx Desciptor unavailable */ |
| 1282 |
#define ETH_DMA_ReceiveProcess_Closing ((uint32_t)0x000A0000) /*!< Running - closing descriptor */ |
| 1283 |
#define ETH_DMA_ReceiveProcess_Queuing ((uint32_t)0x000E0000) /*!< Running - queuing the recieve frame into host memory */ |
| 1284 |
|
| 1285 |
/**
|
| 1286 |
* @}
|
| 1287 |
*/
|
| 1288 |
|
| 1289 |
/** @defgroup ETH_DMA_overflow_
|
| 1290 |
* @{
|
| 1291 |
*/
|
| 1292 |
#define ETH_DMA_Overflow_RxFIFOCounter ((uint32_t)0x10000000) /*!< Overflow bit for FIFO overflow counter */ |
| 1293 |
#define ETH_DMA_Overflow_MissedFrameCounter ((uint32_t)0x00010000) /*!< Overflow bit for missed frame counter */ |
| 1294 |
#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_Overflow_RxFIFOCounter) || \
|
| 1295 |
((OVERFLOW) == ETH_DMA_Overflow_MissedFrameCounter)) |
| 1296 |
|
| 1297 |
/**--------------------------------------------------------------------------**/
|
| 1298 |
/**
|
| 1299 |
* @brief Ethernet PMT defines
|
| 1300 |
*/
|
| 1301 |
/**--------------------------------------------------------------------------**/
|
| 1302 |
/**
|
| 1303 |
* @}
|
| 1304 |
*/
|
| 1305 |
|
| 1306 |
/** @defgroup ETH_PMT_Flags
|
| 1307 |
* @{
|
| 1308 |
*/
|
| 1309 |
#define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /*!< Wake-Up Frame Filter Register Poniter Reset */ |
| 1310 |
#define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /*!< Wake-Up Frame Received */ |
| 1311 |
#define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /*!< Magic Packet Received */ |
| 1312 |
#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \
|
| 1313 |
((FLAG) == ETH_PMT_FLAG_MPR)) |
| 1314 |
|
| 1315 |
/**--------------------------------------------------------------------------**/
|
| 1316 |
/**
|
| 1317 |
* @brief Ethernet MMC defines
|
| 1318 |
*/
|
| 1319 |
/**--------------------------------------------------------------------------**/
|
| 1320 |
/**
|
| 1321 |
* @}
|
| 1322 |
*/
|
| 1323 |
|
| 1324 |
/** @defgroup ETH_MMC_Tx_Interrupts
|
| 1325 |
* @{
|
| 1326 |
*/
|
| 1327 |
#define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /*!< When Tx good frame counter reaches half the maximum value */ |
| 1328 |
#define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /*!< When Tx good multi col counter reaches half the maximum value */ |
| 1329 |
#define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /*!< When Tx good single col counter reaches half the maximum value */ |
| 1330 |
|
| 1331 |
/**
|
| 1332 |
* @}
|
| 1333 |
*/
|
| 1334 |
|
| 1335 |
/** @defgroup ETH_MMC_Rx_Interrupts
|
| 1336 |
* @{
|
| 1337 |
*/
|
| 1338 |
#define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /*!< When Rx good unicast frames counter reaches half the maximum value */ |
| 1339 |
#define ETH_MMC_IT_RFAE ((uint32_t)0x10000040) /*!< When Rx alignment error counter reaches half the maximum value */ |
| 1340 |
#define ETH_MMC_IT_RFCE ((uint32_t)0x10000020) /*!< When Rx crc error counter reaches half the maximum value */ |
| 1341 |
#define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) || (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \ |
| 1342 |
((IT) != 0x00))
|
| 1343 |
#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \
|
| 1344 |
((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \ |
| 1345 |
((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE)) |
| 1346 |
/**
|
| 1347 |
* @}
|
| 1348 |
*/
|
| 1349 |
|
| 1350 |
/** @defgroup ETH_MMC_Registers
|
| 1351 |
* @{
|
| 1352 |
*/
|
| 1353 |
#define ETH_MMCCR ((uint32_t)0x00000100) /*!< MMC CR register */ |
| 1354 |
#define ETH_MMCRIR ((uint32_t)0x00000104) /*!< MMC RIR register */ |
| 1355 |
#define ETH_MMCTIR ((uint32_t)0x00000108) /*!< MMC TIR register */ |
| 1356 |
#define ETH_MMCRIMR ((uint32_t)0x0000010C) /*!< MMC RIMR register */ |
| 1357 |
#define ETH_MMCTIMR ((uint32_t)0x00000110) /*!< MMC TIMR register */ |
| 1358 |
#define ETH_MMCTGFSCCR ((uint32_t)0x0000014C) /*!< MMC TGFSCCR register */ |
| 1359 |
#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150) /*!< MMC TGFMSCCR register */ |
| 1360 |
#define ETH_MMCTGFCR ((uint32_t)0x00000168) /*!< MMC TGFCR register */ |
| 1361 |
#define ETH_MMCRFCECR ((uint32_t)0x00000194) /*!< MMC RFCECR register */ |
| 1362 |
#define ETH_MMCRFAECR ((uint32_t)0x00000198) /*!< MMC RFAECR register */ |
| 1363 |
#define ETH_MMCRGUFCR ((uint32_t)0x000001C4) /*!< MMC RGUFCR register */ |
| 1364 |
|
| 1365 |
/**
|
| 1366 |
* @brief ETH MMC registers
|
| 1367 |
*/
|
| 1368 |
#define IS_ETH_MMC_REGISTER(REG) (((REG) == ETH_MMCCR) || ((REG) == ETH_MMCRIR) || \
|
| 1369 |
((REG) == ETH_MMCTIR) || ((REG) == ETH_MMCRIMR) || \ |
| 1370 |
((REG) == ETH_MMCTIMR) || ((REG) == ETH_MMCTGFSCCR) || \ |
| 1371 |
((REG) == ETH_MMCTGFMSCCR) || ((REG) == ETH_MMCTGFCR) || \ |
| 1372 |
((REG) == ETH_MMCRFCECR) || ((REG) == ETH_MMCRFAECR) || \ |
| 1373 |
((REG) == ETH_MMCRGUFCR)) |
| 1374 |
|
| 1375 |
/**--------------------------------------------------------------------------**/
|
| 1376 |
/**
|
| 1377 |
* @brief Ethernet PTP defines
|
| 1378 |
*/
|
| 1379 |
/**--------------------------------------------------------------------------**/
|
| 1380 |
/**
|
| 1381 |
* @}
|
| 1382 |
*/
|
| 1383 |
|
| 1384 |
/** @defgroup ETH_PTP_time_update_method
|
| 1385 |
* @{
|
| 1386 |
*/
|
| 1387 |
#define ETH_PTP_FineUpdate ((uint32_t)0x00000001) /*!< Fine Update method */ |
| 1388 |
#define ETH_PTP_CoarseUpdate ((uint32_t)0x00000000) /*!< Coarse Update method */ |
| 1389 |
#define IS_ETH_PTP_UPDATE(UPDATE) (((UPDATE) == ETH_PTP_FineUpdate) || \
|
| 1390 |
((UPDATE) == ETH_PTP_CoarseUpdate)) |
| 1391 |
|
| 1392 |
/**
|
| 1393 |
* @}
|
| 1394 |
*/
|
| 1395 |
|
| 1396 |
|
| 1397 |
/** @defgroup ETH_PTP_Flags
|
| 1398 |
* @{
|
| 1399 |
*/
|
| 1400 |
#define ETH_PTP_FLAG_TSARU ((uint32_t)0x00000020) /*!< Addend Register Update */ |
| 1401 |
#define ETH_PTP_FLAG_TSITE ((uint32_t)0x00000010) /*!< Time Stamp Interrupt Trigger */ |
| 1402 |
#define ETH_PTP_FLAG_TSSTU ((uint32_t)0x00000008) /*!< Time Stamp Update */ |
| 1403 |
#define ETH_PTP_FLAG_TSSTI ((uint32_t)0x00000004) /*!< Time Stamp Initialize */ |
| 1404 |
#define IS_ETH_PTP_GET_FLAG(FLAG) (((FLAG) == ETH_PTP_FLAG_TSARU) || \
|
| 1405 |
((FLAG) == ETH_PTP_FLAG_TSITE) || \ |
| 1406 |
((FLAG) == ETH_PTP_FLAG_TSSTU) || \ |
| 1407 |
((FLAG) == ETH_PTP_FLAG_TSSTI)) |
| 1408 |
/**
|
| 1409 |
* @brief ETH PTP subsecond increment
|
| 1410 |
*/
|
| 1411 |
#define IS_ETH_PTP_SUBSECOND_INCREMENT(SUBSECOND) ((SUBSECOND) <= 0xFF) |
| 1412 |
|
| 1413 |
/**
|
| 1414 |
* @}
|
| 1415 |
*/
|
| 1416 |
|
| 1417 |
|
| 1418 |
/** @defgroup ETH_PTP_time_sign
|
| 1419 |
* @{
|
| 1420 |
*/
|
| 1421 |
#define ETH_PTP_PositiveTime ((uint32_t)0x00000000) /*!< Positive time value */ |
| 1422 |
#define ETH_PTP_NegativeTime ((uint32_t)0x80000000) /*!< Negative time value */ |
| 1423 |
#define IS_ETH_PTP_TIME_SIGN(SIGN) (((SIGN) == ETH_PTP_PositiveTime) || \
|
| 1424 |
((SIGN) == ETH_PTP_NegativeTime)) |
| 1425 |
|
| 1426 |
/**
|
| 1427 |
* @brief ETH PTP time stamp low update
|
| 1428 |
*/
|
| 1429 |
#define IS_ETH_PTP_TIME_STAMP_UPDATE_SUBSECOND(SUBSECOND) ((SUBSECOND) <= 0x7FFFFFFF) |
| 1430 |
|
| 1431 |
/**
|
| 1432 |
* @brief ETH PTP registers
|
| 1433 |
*/
|
| 1434 |
#define ETH_PTPTSCR ((uint32_t)0x00000700) /*!< PTP TSCR register */ |
| 1435 |
#define ETH_PTPSSIR ((uint32_t)0x00000704) /*!< PTP SSIR register */ |
| 1436 |
#define ETH_PTPTSHR ((uint32_t)0x00000708) /*!< PTP TSHR register */ |
| 1437 |
#define ETH_PTPTSLR ((uint32_t)0x0000070C) /*!< PTP TSLR register */ |
| 1438 |
#define ETH_PTPTSHUR ((uint32_t)0x00000710) /*!< PTP TSHUR register */ |
| 1439 |
#define ETH_PTPTSLUR ((uint32_t)0x00000714) /*!< PTP TSLUR register */ |
| 1440 |
#define ETH_PTPTSAR ((uint32_t)0x00000718) /*!< PTP TSAR register */ |
| 1441 |
#define ETH_PTPTTHR ((uint32_t)0x0000071C) /*!< PTP TTHR register */ |
| 1442 |
#define ETH_PTPTTLR ((uint32_t)0x00000720) /* PTP TTLR register */ |
| 1443 |
#define IS_ETH_PTP_REGISTER(REG) (((REG) == ETH_PTPTSCR) || ((REG) == ETH_PTPSSIR) || \
|
| 1444 |
((REG) == ETH_PTPTSHR) || ((REG) == ETH_PTPTSLR) || \ |
| 1445 |
((REG) == ETH_PTPTSHUR) || ((REG) == ETH_PTPTSLUR) || \ |
| 1446 |
((REG) == ETH_PTPTSAR) || ((REG) == ETH_PTPTTHR) || \ |
| 1447 |
((REG) == ETH_PTPTTLR)) |
| 1448 |
|
| 1449 |
/**
|
| 1450 |
* @}
|
| 1451 |
*/
|
| 1452 |
|
| 1453 |
|
| 1454 |
/**
|
| 1455 |
* @}
|
| 1456 |
*/
|
| 1457 |
|
| 1458 |
/** @defgroup ETH_Exported_Macros
|
| 1459 |
* @{
|
| 1460 |
*/
|
| 1461 |
/**
|
| 1462 |
* @}
|
| 1463 |
*/
|
| 1464 |
|
| 1465 |
/** @defgroup ETH_Exported_Functions
|
| 1466 |
* @{
|
| 1467 |
*/
|
| 1468 |
void ETH_DeInit(void); |
| 1469 |
uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, u16 PHYAddress); |
| 1470 |
void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct);
|
| 1471 |
void ETH_SoftwareReset(void); |
| 1472 |
FlagStatus ETH_GetSoftwareResetStatus(void);
|
| 1473 |
void ETH_Start(void); |
| 1474 |
uint32_t ETH_HandleTxPkt(u8 *ppkt, u16 FrameLength); |
| 1475 |
uint32_t ETH_HandleRxPkt(u8 *ppkt); |
| 1476 |
uint32_t ETH_GetRxPktSize(void);
|
| 1477 |
void ETH_DropRxPkt(void); |
| 1478 |
|
| 1479 |
/**
|
| 1480 |
* @brief PHY
|
| 1481 |
*/
|
| 1482 |
u16 ETH_ReadPHYRegister(u16 PHYAddress, u16 PHYReg); |
| 1483 |
uint32_t ETH_WritePHYRegister(u16 PHYAddress, u16 PHYReg, u16 PHYValue); |
| 1484 |
uint32_t ETH_PHYLoopBackCmd(u16 PHYAddress, FunctionalState NewState); |
| 1485 |
|
| 1486 |
/**
|
| 1487 |
* @brief MAC
|
| 1488 |
*/
|
| 1489 |
void ETH_MACTransmissionCmd(FunctionalState NewState);
|
| 1490 |
void ETH_MACReceptionCmd(FunctionalState NewState);
|
| 1491 |
FlagStatus ETH_GetFlowControlBusyStatus(void);
|
| 1492 |
void ETH_InitiatePauseControlFrame(void); |
| 1493 |
void ETH_BackPressureActivationCmd(FunctionalState NewState);
|
| 1494 |
FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG); |
| 1495 |
ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT); |
| 1496 |
void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState);
|
| 1497 |
void ETH_MACAddressConfig(uint32_t MacAddr, u8 *Addr);
|
| 1498 |
void ETH_GetMACAddress(uint32_t MacAddr, u8 *Addr);
|
| 1499 |
void ETH_MACAddressPerfectFilterCmd(uint32_t MacAddr, FunctionalState NewState);
|
| 1500 |
void ETH_MACAddressFilterConfig(uint32_t MacAddr, uint32_t Filter);
|
| 1501 |
void ETH_MACAddressMaskBytesFilterConfig(uint32_t MacAddr, uint32_t MaskByte);
|
| 1502 |
|
| 1503 |
/**
|
| 1504 |
* @brief DMA Tx/Rx descriptors
|
| 1505 |
*/
|
| 1506 |
void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, u8 *TxBuff, uint32_t TxBuffCount);
|
| 1507 |
void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, u8 *TxBuff1, u8 *TxBuff2, uint32_t TxBuffCount);
|
| 1508 |
FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ETH_DMATxDescFlag); |
| 1509 |
uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc); |
| 1510 |
void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc);
|
| 1511 |
void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
|
| 1512 |
void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_FrameSegment);
|
| 1513 |
void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Checksum);
|
| 1514 |
void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
|
| 1515 |
void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
|
| 1516 |
void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
|
| 1517 |
void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
|
| 1518 |
void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState);
|
| 1519 |
void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t BufferSize1, uint32_t BufferSize2);
|
| 1520 |
void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, u8 *RxBuff, uint32_t RxBuffCount);
|
| 1521 |
void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, u8 *RxBuff1, u8 *RxBuff2, uint32_t RxBuffCount);
|
| 1522 |
FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ETH_DMARxDescFlag); |
| 1523 |
void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc);
|
| 1524 |
uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc); |
| 1525 |
void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState);
|
| 1526 |
void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState);
|
| 1527 |
void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState);
|
| 1528 |
uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_Buffer); |
| 1529 |
|
| 1530 |
/**
|
| 1531 |
* @brief DMA
|
| 1532 |
*/
|
| 1533 |
FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG); |
| 1534 |
void ETH_DMAClearFlag(uint32_t ETH_DMA_FLAG);
|
| 1535 |
ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT); |
| 1536 |
void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT);
|
| 1537 |
uint32_t ETH_GetTransmitProcessState(void);
|
| 1538 |
uint32_t ETH_GetReceiveProcessState(void);
|
| 1539 |
void ETH_FlushTransmitFIFO(void); |
| 1540 |
FlagStatus ETH_GetFlushTransmitFIFOStatus(void);
|
| 1541 |
void ETH_DMATransmissionCmd(FunctionalState NewState);
|
| 1542 |
void ETH_DMAReceptionCmd(FunctionalState NewState);
|
| 1543 |
void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState);
|
| 1544 |
FlagStatus ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow); |
| 1545 |
uint32_t ETH_GetRxOverflowMissedFrameCounter(void);
|
| 1546 |
uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void);
|
| 1547 |
uint32_t ETH_GetCurrentTxDescStartAddress(void);
|
| 1548 |
uint32_t ETH_GetCurrentRxDescStartAddress(void);
|
| 1549 |
uint32_t ETH_GetCurrentTxBufferAddress(void);
|
| 1550 |
uint32_t ETH_GetCurrentRxBufferAddress(void);
|
| 1551 |
void ETH_ResumeDMATransmission(void); |
| 1552 |
void ETH_ResumeDMAReception(void); |
| 1553 |
|
| 1554 |
/**
|
| 1555 |
* @brief PMT
|
| 1556 |
*/
|
| 1557 |
void ETH_ResetWakeUpFrameFilterRegisterPointer(void); |
| 1558 |
void ETH_SetWakeUpFrameFilterRegister(uint32_t *Buffer);
|
| 1559 |
void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState);
|
| 1560 |
FlagStatus ETH_GetPMTFlagStatus(uint32_t ETH_PMT_FLAG); |
| 1561 |
void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState);
|
| 1562 |
void ETH_MagicPacketDetectionCmd(FunctionalState NewState);
|
| 1563 |
void ETH_PowerDownCmd(FunctionalState NewState);
|
| 1564 |
|
| 1565 |
/**
|
| 1566 |
* @brief MMC
|
| 1567 |
*/
|
| 1568 |
void ETH_MMCCounterFreezeCmd(FunctionalState NewState);
|
| 1569 |
void ETH_MMCResetOnReadCmd(FunctionalState NewState);
|
| 1570 |
void ETH_MMCCounterRolloverCmd(FunctionalState NewState);
|
| 1571 |
void ETH_MMCCountersReset(void); |
| 1572 |
void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState);
|
| 1573 |
ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT); |
| 1574 |
uint32_t ETH_GetMMCRegister(uint32_t ETH_MMCReg); |
| 1575 |
|
| 1576 |
/**
|
| 1577 |
* @brief PTP
|
| 1578 |
*/
|
| 1579 |
uint32_t ETH_HandlePTPTxPkt(u8 *ppkt, u16 FrameLength, uint32_t *PTPTxTab); |
| 1580 |
uint32_t ETH_HandlePTPRxPkt(u8 *ppkt, uint32_t *PTPRxTab); |
| 1581 |
void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab, u8* TxBuff, uint32_t TxBuffCount);
|
| 1582 |
void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCTypeDef *DMAPTPRxDescTab, u8 *RxBuff, uint32_t RxBuffCount);
|
| 1583 |
void ETH_EnablePTPTimeStampAddend(void); |
| 1584 |
void ETH_EnablePTPTimeStampInterruptTrigger(void); |
| 1585 |
void ETH_EnablePTPTimeStampUpdate(void); |
| 1586 |
void ETH_InitializePTPTimeStamp(void); |
| 1587 |
void ETH_PTPUpdateMethodConfig(uint32_t UpdateMethod);
|
| 1588 |
void ETH_PTPTimeStampCmd(FunctionalState NewState);
|
| 1589 |
FlagStatus ETH_GetPTPFlagStatus(uint32_t ETH_PTP_FLAG); |
| 1590 |
void ETH_SetPTPSubSecondIncrement(uint32_t SubSecondValue);
|
| 1591 |
void ETH_SetPTPTimeStampUpdate(uint32_t Sign, uint32_t SecondValue, uint32_t SubSecondValue);
|
| 1592 |
void ETH_SetPTPTimeStampAddend(uint32_t Value);
|
| 1593 |
void ETH_SetPTPTargetTime(uint32_t HighValue, uint32_t LowValue);
|
| 1594 |
uint32_t ETH_GetPTPRegister(uint32_t ETH_PTPReg); |
| 1595 |
|
| 1596 |
#ifdef __cplusplus
|
| 1597 |
} |
| 1598 |
#endif
|
| 1599 |
|
| 1600 |
#endif /* __STM32_ETH_H */ |
| 1601 |
/**
|
| 1602 |
* @}
|
| 1603 |
*/
|
| 1604 |
|
| 1605 |
|
| 1606 |
/**
|
| 1607 |
* @}
|
| 1608 |
*/
|
| 1609 |
|
| 1610 |
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
|