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amiro-blt / Target / Demo / ARMCM4_STM32F405_Power_Management_GCC / Boot / lib / ethernetlib / src / stm32_eth.c @ 69661903

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/**
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  ******************************************************************************
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  * @file    stm32_eth.c
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  * @author  MCD Application Team
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  * @version V1.0.0
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  * @date    06/19/2009
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  * @brief   This file provides all the ETH firmware functions.
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  ******************************************************************************
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  * @copy
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  *
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  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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  *
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  * <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
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  */ 
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/* Includes ------------------------------------------------------------------*/
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#include "stm32_eth.h"
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#include "stm32f4xx_rcc.h"
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/** @addtogroup STM32_ETH_Driver
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  * @brief ETH driver modules
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  * @{
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  */
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/** @defgroup ETH_Private_TypesDefinitions
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  * @{
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  */ 
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/**
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  * @}
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  */ 
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/** @defgroup ETH_Private_Defines
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  * @{
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  */ 
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/* Global pointers on Tx and Rx descriptor used to track transmit and receive descriptors */
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ETH_DMADESCTypeDef  *DMATxDescToSet;
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ETH_DMADESCTypeDef  *DMARxDescToGet;
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ETH_DMADESCTypeDef  *DMAPTPTxDescToSet;
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ETH_DMADESCTypeDef  *DMAPTPRxDescToGet;
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/* ETHERNET MAC address offsets */
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#define ETH_MAC_AddrHighBase   (ETH_MAC_BASE + 0x40)  /* ETHERNET MAC address high offset */
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#define ETH_MAC_AddrLowBase    (ETH_MAC_BASE + 0x44)  /* ETHERNET MAC address low offset */
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/* ETHERNET MACMIIAR register Mask */
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#define MACMIIAR_CR_Mask    ((uint32_t)0xFFFFFFE3) 
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/* ETHERNET MACCR register Mask */
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#define MACCR_CLEAR_Mask    ((uint32_t)0xFF20810F)  
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/* ETHERNET MACFCR register Mask */
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#define MACFCR_CLEAR_Mask   ((uint32_t)0x0000FF41)
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/* ETHERNET DMAOMR register Mask */
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#define DMAOMR_CLEAR_Mask   ((uint32_t)0xF8DE3F23)
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/* ETHERNET Remote Wake-up frame register length */
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#define ETH_WakeupRegisterLength      8
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/* ETHERNET Missed frames counter Shift */
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#define  ETH_DMA_RxOverflowMissedFramesCounterShift     17
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/* ETHERNET DMA Tx descriptors Collision Count Shift */
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#define  ETH_DMATxDesc_CollisionCountShift        3
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/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
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#define  ETH_DMATxDesc_BufferSize2Shift           16
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/* ETHERNET DMA Rx descriptors Frame Length Shift */
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#define  ETH_DMARxDesc_FrameLengthShift           16
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/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
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#define  ETH_DMARxDesc_Buffer2SizeShift           16
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/* ETHERNET errors */
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#define  ETH_ERROR              ((uint32_t)0)
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#define  ETH_SUCCESS            ((uint32_t)1)
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/**
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  * @}
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  */
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/** @defgroup ETH_Private_Macros
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  * @{
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  */ 
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/**
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  * @}
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  */
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/** @defgroup ETH_Private_Variables
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  * @{
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  */ 
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/**
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  * @}
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  */
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/** @defgroup ETH_Private_FunctionPrototypes
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  * @{
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  */ 
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/**
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  * @}
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  */
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/** @defgroup ETH_Private_Functions
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  * @{
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  */
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/**
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  * @brief  Deinitializes the ETHERNET peripheral registers to their
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  *   default reset values.
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  * @param  None 
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  * @retval : None
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  */
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void ETH_DeInit(void)
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{
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  RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_ETH_MAC, ENABLE);
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  RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_ETH_MAC, DISABLE);
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}
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/**
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  * @brief  Initializes the ETHERNET peripheral according to the specified
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  *   parameters in the ETH_InitStruct .
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  * @param ETH_InitStruct: pointer to a ETH_InitTypeDef structure
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  *   that contains the configuration information for the
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  *   specified ETHERNET peripheral.
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  * @param PHYAddress: external PHY address                    
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  * @retval : ETH_ERROR: Ethernet initialization failed
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  *   ETH_SUCCESS: Ethernet successfully initialized                 
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  */
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uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress)
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{
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  uint32_t RegValue = 0, tmpreg = 0;
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  __IO uint32_t i = 0;
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  RCC_ClocksTypeDef  rcc_clocks;
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  uint32_t hclk = 120000000;
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  __IO uint32_t timeout = 0;
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  /* Check the parameters */
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  /* MAC --------------------------*/ 
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  assert_param(IS_ETH_AUTONEGOTIATION(ETH_InitStruct->ETH_AutoNegotiation));
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  assert_param(IS_ETH_WATCHDOG(ETH_InitStruct->ETH_Watchdog));
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  assert_param(IS_ETH_JABBER(ETH_InitStruct->ETH_Jabber));
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  assert_param(IS_ETH_INTER_FRAME_GAP(ETH_InitStruct->ETH_InterFrameGap));
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  assert_param(IS_ETH_CARRIER_SENSE(ETH_InitStruct->ETH_CarrierSense));
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  assert_param(IS_ETH_SPEED(ETH_InitStruct->ETH_Speed));
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  assert_param(IS_ETH_RECEIVE_OWN(ETH_InitStruct->ETH_ReceiveOwn));
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  assert_param(IS_ETH_LOOPBACK_MODE(ETH_InitStruct->ETH_LoopbackMode));
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  assert_param(IS_ETH_DUPLEX_MODE(ETH_InitStruct->ETH_Mode));
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  assert_param(IS_ETH_CHECKSUM_OFFLOAD(ETH_InitStruct->ETH_ChecksumOffload));
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  assert_param(IS_ETH_RETRY_TRANSMISSION(ETH_InitStruct->ETH_RetryTransmission));
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  assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(ETH_InitStruct->ETH_AutomaticPadCRCStrip));
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  assert_param(IS_ETH_BACKOFF_LIMIT(ETH_InitStruct->ETH_BackOffLimit));
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  assert_param(IS_ETH_DEFERRAL_CHECK(ETH_InitStruct->ETH_DeferralCheck));
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  assert_param(IS_ETH_RECEIVE_ALL(ETH_InitStruct->ETH_ReceiveAll));
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  assert_param(IS_ETH_SOURCE_ADDR_FILTER(ETH_InitStruct->ETH_SourceAddrFilter));
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  assert_param(IS_ETH_CONTROL_FRAMES(ETH_InitStruct->ETH_PassControlFrames));
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  assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(ETH_InitStruct->ETH_BroadcastFramesReception));
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  assert_param(IS_ETH_DESTINATION_ADDR_FILTER(ETH_InitStruct->ETH_DestinationAddrFilter));
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  assert_param(IS_ETH_PROMISCUOUS_MODE(ETH_InitStruct->ETH_PromiscuousMode));
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  assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(ETH_InitStruct->ETH_MulticastFramesFilter));  
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  assert_param(IS_ETH_UNICAST_FRAMES_FILTER(ETH_InitStruct->ETH_UnicastFramesFilter));
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  assert_param(IS_ETH_PAUSE_TIME(ETH_InitStruct->ETH_PauseTime));
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  assert_param(IS_ETH_ZEROQUANTA_PAUSE(ETH_InitStruct->ETH_ZeroQuantaPause));
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  assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(ETH_InitStruct->ETH_PauseLowThreshold));
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  assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(ETH_InitStruct->ETH_UnicastPauseFrameDetect));
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  assert_param(IS_ETH_RECEIVE_FLOWCONTROL(ETH_InitStruct->ETH_ReceiveFlowControl));
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  assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(ETH_InitStruct->ETH_TransmitFlowControl));
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  assert_param(IS_ETH_VLAN_TAG_COMPARISON(ETH_InitStruct->ETH_VLANTagComparison));
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  assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(ETH_InitStruct->ETH_VLANTagIdentifier));
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  /* DMA --------------------------*/
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  assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame));
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  assert_param(IS_ETH_RECEIVE_STORE_FORWARD(ETH_InitStruct->ETH_ReceiveStoreForward));
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  assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(ETH_InitStruct->ETH_FlushReceivedFrame));
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  assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(ETH_InitStruct->ETH_TransmitStoreForward));
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  assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(ETH_InitStruct->ETH_TransmitThresholdControl));
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  assert_param(IS_ETH_FORWARD_ERROR_FRAMES(ETH_InitStruct->ETH_ForwardErrorFrames));
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  assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(ETH_InitStruct->ETH_ForwardUndersizedGoodFrames));
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  assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(ETH_InitStruct->ETH_ReceiveThresholdControl));
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  assert_param(IS_ETH_SECOND_FRAME_OPERATE(ETH_InitStruct->ETH_SecondFrameOperate));
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  assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(ETH_InitStruct->ETH_AddressAlignedBeats));
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  assert_param(IS_ETH_FIXED_BURST(ETH_InitStruct->ETH_FixedBurst));
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  assert_param(IS_ETH_RXDMA_BURST_LENGTH(ETH_InitStruct->ETH_RxDMABurstLength));
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  assert_param(IS_ETH_TXDMA_BURST_LENGTH(ETH_InitStruct->ETH_TxDMABurstLength)); 
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  assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(ETH_InitStruct->ETH_DescriptorSkipLength));  
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  assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(ETH_InitStruct->ETH_DMAArbitration));       
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  /*-------------------------------- MAC Config ------------------------------*/   
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  /*---------------------- ETHERNET MACMIIAR Configuration -------------------*/
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  /* Get the ETHERNET MACMIIAR value */
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  tmpreg = ETH->MACMIIAR;
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  /* Clear CSR Clock Range CR[2:0] bits */
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  tmpreg &= MACMIIAR_CR_Mask;
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  /* Get hclk frequency value */
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  RCC_GetClocksFreq(&rcc_clocks);
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  hclk = rcc_clocks.HCLK_Frequency;
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  /* Set CR bits depending on hclk value */
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  if((hclk >= 20000000)&&(hclk < 35000000))
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  {
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    /* CSR Clock Range between 20-35 MHz */
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    tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div16;
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  }
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  else if((hclk >= 35000000)&&(hclk < 60000000))
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  {
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    /* CSR Clock Range between 35-60 MHz */ 
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    tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div26;    
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  }  
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  else if((hclk >= 60000000)&&(hclk <= 100000000)) 
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  {
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    /* CSR Clock Range between 60-100 MHz */   
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    tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42;    
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  }
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  else /*if((hclk >= 100000000)&&(hclk <= 120000000)) */
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  {
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    /* CSR Clock Range between 100-120 MHz */   
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    tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div62;    
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  }
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  /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
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  ETH->MACMIIAR = (uint32_t)tmpreg;  
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  /*-------------------- PHY initialization and configuration ----------------*/
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  /* Put the PHY in reset mode */
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  if(!(ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_Reset)))
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  {
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    /* Return ERROR in case of write timeout */
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    return ETH_ERROR;
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  }
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  /* Delay to assure PHY reset */
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  for(i = PHY_ResetDelay; i != 0; i--)
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  {
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  }
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  if(ETH_InitStruct->ETH_AutoNegotiation != ETH_AutoNegotiation_Disable)
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  {  
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    /* We wait for linked satus... */
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    do
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    {
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      timeout++;
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    } while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_Linked_Status) && (timeout < PHY_READ_TO));
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    /* Return ERROR in case of timeout */
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    if(timeout == PHY_READ_TO)
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    {
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      return ETH_ERROR;
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    }
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    /* Reset Timeout counter */
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    timeout = 0;
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    /* Enable Auto-Negotiation */
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    if(!(ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_AutoNegotiation)))
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    {
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      /* Return ERROR in case of write timeout */
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      return ETH_ERROR;
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    }
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    /* Wait until the autonegotiation will be completed */
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    do
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    {
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      timeout++;
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    } while (!(ETH_ReadPHYRegister(PHYAddress, PHY_BSR) & PHY_AutoNego_Complete) && (timeout < (uint32_t)PHY_READ_TO));  
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    /* Return ERROR in case of timeout */
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    if(timeout == PHY_READ_TO)
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    {
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      return ETH_ERROR;
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    }
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    /* Reset Timeout counter */
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    timeout = 0;
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    /* Read the result of the autonegotiation */
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    RegValue = ETH_ReadPHYRegister(PHYAddress, PHY_SR);
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    /* Configure the MAC with the Duplex Mode fixed by the autonegotiation process */
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    if((RegValue & PHY_Duplex_Status) != (uint32_t)RESET)
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    {
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      /* Set Ethernet duplex mode to FullDuplex following the autonegotiation */
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      ETH_InitStruct->ETH_Mode = ETH_Mode_FullDuplex;
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    }
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    else
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    {
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      /* Set Ethernet duplex mode to HalfDuplex following the autonegotiation */
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      ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex;           
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    }
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    /* Configure the MAC with the speed fixed by the autonegotiation process */
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    if(RegValue & PHY_Speed_Status)
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    {  
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      /* Set Ethernet speed to 10M following the autonegotiation */    
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      ETH_InitStruct->ETH_Speed = ETH_Speed_10M; 
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    }
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    else
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    {   
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      /* Set Ethernet speed to 100M following the autonegotiation */ 
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      ETH_InitStruct->ETH_Speed = ETH_Speed_100M;      
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    }    
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  }
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  else
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  {
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    if(!ETH_WritePHYRegister(PHYAddress, PHY_BCR, ((uint16_t)(ETH_InitStruct->ETH_Mode >> 3) |
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                                                   (uint16_t)(ETH_InitStruct->ETH_Speed >> 1))))
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    {
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      /* Return ERROR in case of write timeout */
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      return ETH_ERROR;
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    }
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    /* Delay to assure PHY configuration */
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    for(i = PHY_ConfigDelay; i != 0; i--)
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    {
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    }
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  }
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  /*------------------------ ETHERNET MACCR Configuration --------------------*/
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  /* Get the ETHERNET MACCR value */  
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  tmpreg = ETH->MACCR;
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  /* Clear WD, PCE, PS, TE and RE bits */
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  tmpreg &= MACCR_CLEAR_Mask;
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  /* Set the WD bit according to ETH_Watchdog value */
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  /* Set the JD: bit according to ETH_Jabber value */
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  /* Set the IFG bit according to ETH_InterFrameGap value */ 
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  /* Set the DCRS bit according to ETH_CarrierSense value */  
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  /* Set the FES bit according to ETH_Speed value */ 
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  /* Set the DO bit according to ETH_ReceiveOwn value */ 
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  /* Set the LM bit according to ETH_LoopbackMode value */ 
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  /* Set the DM bit according to ETH_Mode value */ 
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  /* Set the IPC bit according to ETH_ChecksumOffload value */                   
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  /* Set the DR bit according to ETH_RetryTransmission value */ 
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  /* Set the ACS bit according to ETH_AutomaticPadCRCStrip value */ 
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  /* Set the BL bit according to ETH_BackOffLimit value */ 
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  /* Set the DC bit according to ETH_DeferralCheck value */                          
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  tmpreg |= (uint32_t)(ETH_InitStruct->ETH_Watchdog | 
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                  ETH_InitStruct->ETH_Jabber | 
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                  ETH_InitStruct->ETH_InterFrameGap |
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                  ETH_InitStruct->ETH_CarrierSense |
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                  ETH_InitStruct->ETH_Speed | 
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                  ETH_InitStruct->ETH_ReceiveOwn |
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                  ETH_InitStruct->ETH_LoopbackMode |
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                  ETH_InitStruct->ETH_Mode | 
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                  ETH_InitStruct->ETH_ChecksumOffload |    
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                  ETH_InitStruct->ETH_RetryTransmission | 
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                  ETH_InitStruct->ETH_AutomaticPadCRCStrip | 
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                  ETH_InitStruct->ETH_BackOffLimit | 
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                  ETH_InitStruct->ETH_DeferralCheck);
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  /* Write to ETHERNET MACCR */
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  ETH->MACCR = (uint32_t)tmpreg;
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  /*----------------------- ETHERNET MACFFR Configuration --------------------*/ 
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  /* Set the RA bit according to ETH_ReceiveAll value */
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  /* Set the SAF and SAIF bits according to ETH_SourceAddrFilter value */
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  /* Set the PCF bit according to ETH_PassControlFrames value */
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  /* Set the DBF bit according to ETH_BroadcastFramesReception value */
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  /* Set the DAIF bit according to ETH_DestinationAddrFilter value */
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  /* Set the PR bit according to ETH_PromiscuousMode value */
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  /* Set the PM, HMC and HPF bits according to ETH_MulticastFramesFilter value */
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  /* Set the HUC and HPF bits according to ETH_UnicastFramesFilter value */
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  /* Write to ETHERNET MACFFR */  
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  ETH->MACFFR = (uint32_t)(ETH_InitStruct->ETH_ReceiveAll | 
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                          ETH_InitStruct->ETH_SourceAddrFilter |
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                          ETH_InitStruct->ETH_PassControlFrames |
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                          ETH_InitStruct->ETH_BroadcastFramesReception | 
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                          ETH_InitStruct->ETH_DestinationAddrFilter |
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                          ETH_InitStruct->ETH_PromiscuousMode |
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                          ETH_InitStruct->ETH_MulticastFramesFilter |
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                          ETH_InitStruct->ETH_UnicastFramesFilter); 
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  /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
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  /* Write to ETHERNET MACHTHR */
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  ETH->MACHTHR = (uint32_t)ETH_InitStruct->ETH_HashTableHigh;
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  /* Write to ETHERNET MACHTLR */
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  ETH->