amiro-blt / Target / Demo / ARMCM4_STM32F405_Power_Management_GCC / Boot / lib / stdperiphlib / STM32F4xx_StdPeriph_Driver / src / stm32f4xx_fsmc.c @ 69661903
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/**
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******************************************************************************
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* @file stm32f4xx_fsmc.c
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* @author MCD Application Team
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* @version V1.1.0
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* @date 11-January-2013
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* @brief This file provides firmware functions to manage the following
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* functionalities of the FSMC peripheral:
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* + Interface with SRAM, PSRAM, NOR and OneNAND memories
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* + Interface with NAND memories
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* + Interface with 16-bit PC Card compatible memories
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* + Interrupts and flags management
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*
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
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*
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* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
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* You may not use this file except in compliance with the License.
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* You may obtain a copy of the License at:
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*
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* http://www.st.com/software_license_agreement_liberty_v2
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f4xx_fsmc.h" |
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#include "stm32f4xx_rcc.h" |
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/** @addtogroup STM32F4xx_StdPeriph_Driver
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* @{
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*/
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/** @defgroup FSMC
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* @brief FSMC driver modules
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* @{
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*/
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/* --------------------- FSMC registers bit mask ---------------------------- */
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/* FSMC BCRx Mask */
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#define BCR_MBKEN_SET ((uint32_t)0x00000001) |
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#define BCR_MBKEN_RESET ((uint32_t)0x000FFFFE) |
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#define BCR_FACCEN_SET ((uint32_t)0x00000040) |
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/* FSMC PCRx Mask */
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#define PCR_PBKEN_SET ((uint32_t)0x00000004) |
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#define PCR_PBKEN_RESET ((uint32_t)0x000FFFFB) |
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#define PCR_ECCEN_SET ((uint32_t)0x00000040) |
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#define PCR_ECCEN_RESET ((uint32_t)0x000FFFBF) |
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#define PCR_MEMORYTYPE_NAND ((uint32_t)0x00000008) |
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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/* Private functions ---------------------------------------------------------*/
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/** @defgroup FSMC_Private_Functions
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* @{
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*/
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/** @defgroup FSMC_Group1 NOR/SRAM Controller functions
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* @brief NOR/SRAM Controller functions
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*
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@verbatim
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===============================================================================
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##### NOR and SRAM Controller functions #####
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===============================================================================
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[..] The following sequence should be followed to configure the FSMC to interface
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with SRAM, PSRAM, NOR or OneNAND memory connected to the NOR/SRAM Bank:
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(#) Enable the clock for the FSMC and associated GPIOs using the following functions:
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RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE);
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RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
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(#) FSMC pins configuration
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(++) Connect the involved FSMC pins to AF12 using the following function
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GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC);
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(++) Configure these FSMC pins in alternate function mode by calling the function
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GPIO_Init();
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(#) Declare a FSMC_NORSRAMInitTypeDef structure, for example:
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FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure;
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and fill the FSMC_NORSRAMInitStructure variable with the allowed values of
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the structure member.
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(#) Initialize the NOR/SRAM Controller by calling the function
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FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
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(#) Then enable the NOR/SRAM Bank, for example:
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FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM2, ENABLE);
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(#) At this stage you can read/write from/to the memory connected to the NOR/SRAM Bank.
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@endverbatim
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* @{
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*/
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/**
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* @brief De-initializes the FSMC NOR/SRAM Banks registers to their default
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* reset values.
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* @param FSMC_Bank: specifies the FSMC Bank to be used
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* This parameter can be one of the following values:
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* @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
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* @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
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* @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
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* @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
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* @retval None
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*/
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void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)
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{ |
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/* Check the parameter */
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assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); |
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/* FSMC_Bank1_NORSRAM1 */
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if(FSMC_Bank == FSMC_Bank1_NORSRAM1)
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{ |
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FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;
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} |
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/* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */
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else
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{ |
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FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2;
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} |
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FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF; |
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FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;
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} |
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/**
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* @brief Initializes the FSMC NOR/SRAM Banks according to the specified
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* parameters in the FSMC_NORSRAMInitStruct.
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* @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef structure
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* that contains the configuration information for the FSMC NOR/SRAM
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* specified Banks.
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* @retval None
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*/
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void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
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{ |
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/* Check the parameters */
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assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank)); |
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assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux)); |
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assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType)); |
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assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth)); |
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assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode)); |
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assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait)); |
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assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity)); |
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assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode)); |
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assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive)); |
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assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation)); |
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assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal)); |
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assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode)); |
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assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst)); |
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assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime)); |
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assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime)); |
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assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime)); |
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assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration)); |
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assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision)); |
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assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency)); |
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assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode)); |
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/* Bank1 NOR/SRAM control register configuration */
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FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = |
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(uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux | |
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FSMC_NORSRAMInitStruct->FSMC_MemoryType | |
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FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth | |
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FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode | |
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FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait | |
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FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity | |
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FSMC_NORSRAMInitStruct->FSMC_WrapMode | |
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FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive | |
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FSMC_NORSRAMInitStruct->FSMC_WriteOperation | |
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FSMC_NORSRAMInitStruct->FSMC_WaitSignal | |
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FSMC_NORSRAMInitStruct->FSMC_ExtendedMode | |
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FSMC_NORSRAMInitStruct->FSMC_WriteBurst; |
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if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
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{ |
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FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_SET; |
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} |
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/* Bank1 NOR/SRAM timing register configuration */
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FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] =
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(uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime | |
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(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
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(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
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(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
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(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
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(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
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FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode; |
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/* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
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if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
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{ |
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assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime)); |
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assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime)); |
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assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime)); |
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assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision)); |
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assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency)); |
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assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode)); |
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FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = |
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(uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime | |
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(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
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(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
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(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
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(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
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FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode; |
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} |
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else
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{ |
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FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
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} |
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} |
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/**
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* @brief Fills each FSMC_NORSRAMInitStruct member with its default value.
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* @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef structure
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* which will be initialized.
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* @retval None
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*/
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void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
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{ |
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/* Reset NOR/SRAM Init structure parameters values */
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FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1; |
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FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable; |
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FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM; |
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FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; |
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FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; |
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FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; |
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FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; |
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FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable; |
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FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; |
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FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable; |
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FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable; |
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FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; |
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FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable; |
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FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;
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FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;
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FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;
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FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
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FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;
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FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;
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FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; |
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FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;
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FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;
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FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;
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FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
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FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;
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FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;
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FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; |
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} |
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/**
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* @brief Enables or disables the specified NOR/SRAM Memory Bank.
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* @param FSMC_Bank: specifies the FSMC Bank to be used
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* This parameter can be one of the following values:
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* @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
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* @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
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* @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
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* @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
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* @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
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* @retval None
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*/
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void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)
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{ |
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assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); |
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assert_param(IS_FUNCTIONAL_STATE(NewState)); |
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if (NewState != DISABLE)
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{ |
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/* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */
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FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_SET; |
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} |
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else
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{ |
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/* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */
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FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_RESET; |
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} |
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} |
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/**
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* @}
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*/
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/** @defgroup FSMC_Group2 NAND Controller functions
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* @brief NAND Controller functions
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*
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@verbatim
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===============================================================================
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##### NAND Controller functions #####
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===============================================================================
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[..] The following sequence should be followed to configure the FSMC to interface
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with 8-bit or 16-bit NAND memory connected to the NAND Bank:
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(#) Enable the clock for the FSMC and associated GPIOs using the following functions:
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(++) RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE);
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(++) RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
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(#) FSMC pins configuration
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(++) Connect the involved FSMC pins to AF12 using the following function
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GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC);
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(++) Configure these FSMC pins in alternate function mode by calling the function
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GPIO_Init();
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(#) Declare a FSMC_NANDInitTypeDef structure, for example:
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FSMC_NANDInitTypeDef FSMC_NANDInitStructure;
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and fill the FSMC_NANDInitStructure variable with the allowed values of
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the structure member.
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(#) Initialize the NAND Controller by calling the function
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FSMC_NANDInit(&FSMC_NANDInitStructure);
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(#) Then enable the NAND Bank, for example:
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FSMC_NANDCmd(FSMC_Bank3_NAND, ENABLE);
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(#) At this stage you can read/write from/to the memory connected to the NAND Bank.
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[..]
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(@) To enable the Error Correction Code (ECC), you have to use the function
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FSMC_NANDECCCmd(FSMC_Bank3_NAND, ENABLE);
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[..]
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(@) and to get the current ECC value you have to use the function
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ECCval = FSMC_GetECC(FSMC_Bank3_NAND);
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@endverbatim
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* @{
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*/
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/**
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* @brief De-initializes the FSMC NAND Banks registers to their default reset values.
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