AMiRo-OS

/**

  ******************************************************************************

  * @file    stm32f4xx_fsmc.c

  * @author  MCD Application Team

  * @version V1.1.0

  * @date    11-January-2013

 * @brief    This file provides firmware functions to manage the following 

  *          functionalities of the FSMC peripheral:           

  *           + Interface with SRAM, PSRAM, NOR and OneNAND memories

  *           + Interface with NAND memories

  *           + Interface with 16-bit PC Card compatible memories  

  *           + Interrupts and flags management   

  *           

  ******************************************************************************

  * @attention

  *

  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>

  *

  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");

  * You may not use this file except in compliance with the License.

  * You may obtain a copy of the License at:

  *

  *        http://www.st.com/software_license_agreement_liberty_v2

  *

  * Unless required by applicable law or agreed to in writing, software 

  * distributed under the License is distributed on an "AS IS" BASIS, 

  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

  * See the License for the specific language governing permissions and

  * limitations under the License.

  *

  ******************************************************************************

  */

/* Includes ------------------------------------------------------------------*/

#include "stm32f4xx_fsmc.h"

#include "stm32f4xx_rcc.h"

/** @addtogroup STM32F4xx_StdPeriph_Driver

  * @{

  */

/** @defgroup FSMC 

  * @brief FSMC driver modules

  * @{

  */ 

/* Private typedef -----------------------------------------------------------*/

/* Private define ------------------------------------------------------------*/

/* --------------------- FSMC registers bit mask ---------------------------- */

/* FSMC BCRx Mask */

#define BCR_MBKEN_SET          ((uint32_t)0x00000001)

#define BCR_MBKEN_RESET        ((uint32_t)0x000FFFFE)

#define BCR_FACCEN_SET         ((uint32_t)0x00000040)

/* FSMC PCRx Mask */

#define PCR_PBKEN_SET          ((uint32_t)0x00000004)

#define PCR_PBKEN_RESET        ((uint32_t)0x000FFFFB)

#define PCR_ECCEN_SET          ((uint32_t)0x00000040)

#define PCR_ECCEN_RESET        ((uint32_t)0x000FFFBF)

#define PCR_MEMORYTYPE_NAND    ((uint32_t)0x00000008)

/* Private macro -------------------------------------------------------------*/

/* Private variables ---------------------------------------------------------*/

/* Private function prototypes -----------------------------------------------*/

/* Private functions ---------------------------------------------------------*/

/** @defgroup FSMC_Private_Functions

  * @{

  */

/** @defgroup FSMC_Group1 NOR/SRAM Controller functions

 *  @brief   NOR/SRAM Controller functions 

 *

@verbatim   

 ===============================================================================

                    ##### NOR and SRAM Controller functions #####

 ===============================================================================  

 [..] The following sequence should be followed to configure the FSMC to interface

      with SRAM, PSRAM, NOR or OneNAND memory connected to the NOR/SRAM Bank:

   (#) Enable the clock for the FSMC and associated GPIOs using the following functions:

          RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE);

          RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);

   (#) FSMC pins configuration 

       (++) Connect the involved FSMC pins to AF12 using the following function 

            GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC); 

       (++) Configure these FSMC pins in alternate function mode by calling the function

            GPIO_Init();    

   (#) Declare a FSMC_NORSRAMInitTypeDef structure, for example:

          FSMC_NORSRAMInitTypeDef  FSMC_NORSRAMInitStructure;

      and fill the FSMC_NORSRAMInitStructure variable with the allowed values of

      the structure member.

   (#) Initialize the NOR/SRAM Controller by calling the function

          FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); 

   (#) Then enable the NOR/SRAM Bank, for example:

          FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM2, ENABLE);  

   (#) At this stage you can read/write from/to the memory connected to the NOR/SRAM Bank. 

@endverbatim

  * @{

  */

/**

  * @brief  De-initializes the FSMC NOR/SRAM Banks registers to their default 

  *   reset values.

  * @param  FSMC_Bank: specifies the FSMC Bank to be used

  *          This parameter can be one of the following values:

  *            @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1  

  *            @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 

  *            @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 

  *            @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 

  * @retval None

  */

void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)

{

  /* Check the parameter */

  assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));

  /* FSMC_Bank1_NORSRAM1 */

  if(FSMC_Bank == FSMC_Bank1_NORSRAM1)

  {

    FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;    

  }

  /* FSMC_Bank1_NORSRAM2,  FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */

  else

  {   

    FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; 

  }

  FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;

  FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;  

}

/**

  * @brief  Initializes the FSMC NOR/SRAM Banks according to the specified

  *         parameters in the FSMC_NORSRAMInitStruct.

  * @param  FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef structure

  *         that contains the configuration information for the FSMC NOR/SRAM 

  *         specified Banks.                       

  * @retval None

  */

void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)

{ 

  /* Check the parameters */

  assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));

  assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));

  assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));

  assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));

  assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));

  assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait));

  assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));

  assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));

  assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));

  assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));

  assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));

  assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));

  assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));  

  assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));

  assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));

  assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));

  assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));

  assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));

  assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));

  assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode)); 

  /* Bank1 NOR/SRAM control register configuration */ 

  FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 

            (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |

            FSMC_NORSRAMInitStruct->FSMC_MemoryType |

            FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |

            FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |

            FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait |

            FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |

            FSMC_NORSRAMInitStruct->FSMC_WrapMode |

            FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |

            FSMC_NORSRAMInitStruct->FSMC_WriteOperation |

            FSMC_NORSRAMInitStruct->FSMC_WaitSignal |

            FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |

            FSMC_NORSRAMInitStruct->FSMC_WriteBurst;

  if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)

  {

    FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_SET;

  }

  /* Bank1 NOR/SRAM timing register configuration */

  FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] = 

            (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |

            (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |

            (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |

            (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |

            (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |

            (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |

             FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;

  /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */

  if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)

  {

    assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));

    assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));

    assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));

    assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));

    assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));

    assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));

    FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 

              (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |

              (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|

              (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |

              (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |

              (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |

               FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;

  }

  else

  {

    FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;

  }

}

/**

  * @brief  Fills each FSMC_NORSRAMInitStruct member with its default value.

  * @param  FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef structure 

  *         which will be initialized.

  * @retval None

  */

void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)

{  

  /* Reset NOR/SRAM Init structure parameters values */

  FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;

  FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;

  FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;

  FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;

  FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;

  FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;

  FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;

  FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;

  FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;

  FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;

  FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;

  FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;

  FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;

  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;

  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;

  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;

  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;

  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;

  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;

  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; 

  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;

  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;

  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;

  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;

  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;

  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;

  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;

}

/**

  * @brief  Enables or disables the specified NOR/SRAM Memory Bank.

  * @param  FSMC_Bank: specifies the FSMC Bank to be used

  *          This parameter can be one of the following values:

  *            @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1  

  *            @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 

  *            @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 

  *            @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 

  * @param  NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.

  * @retval None

  */

void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)

{

  assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));

  assert_param(IS_FUNCTIONAL_STATE(NewState));

  if (NewState != DISABLE)

  {

    /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */

    FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_SET;

  }

  else

  {

    /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */

    FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_RESET;

  }

}

/**

  * @}

  */

/** @defgroup FSMC_Group2 NAND Controller functions

 *  @brief   NAND Controller functions 

 *

@verbatim   

 ===============================================================================

                    ##### NAND Controller functions #####

 ===============================================================================  

 [..]  The following sequence should be followed to configure the FSMC to interface 

       with 8-bit or 16-bit NAND memory connected to the NAND Bank:

  (#) Enable the clock for the FSMC and associated GPIOs using the following functions:

      (++)  RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE);

      (++)  RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);

  (#) FSMC pins configuration 

      (++) Connect the involved FSMC pins to AF12 using the following function 

           GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC); 

      (++) Configure these FSMC pins in alternate function mode by calling the function

           GPIO_Init();    

  (#) Declare a FSMC_NANDInitTypeDef structure, for example:

      FSMC_NANDInitTypeDef  FSMC_NANDInitStructure;

      and fill the FSMC_NANDInitStructure variable with the allowed values of

      the structure member.

  (#) Initialize the NAND Controller by calling the function

      FSMC_NANDInit(&FSMC_NANDInitStructure); 

  (#) Then enable the NAND Bank, for example:

      FSMC_NANDCmd(FSMC_Bank3_NAND, ENABLE);  

  (#) At this stage you can read/write from/to the memory connected to the NAND Bank. 

 [..]

  (@) To enable the Error Correction Code (ECC), you have to use the function

      FSMC_NANDECCCmd(FSMC_Bank3_NAND, ENABLE);  

 [..]

  (@) and to get the current ECC value you have to use the function

      ECCval = FSMC_GetECC(FSMC_Bank3_NAND); 

@endverbatim

  * @{

  */

/**

  * @brief  De-initializes the FSMC NAND Banks registers to their default reset values.