amiro-blt / Target / Demo / ARMCM4_STM32F405_Power_Management_GCC / Boot / lib / stdperiphlib / STM32F4xx_StdPeriph_Driver / src / stm32f4xx_hash.c @ 69661903
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/**
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******************************************************************************
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* @file stm32f4xx_hash.c
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* @author MCD Application Team
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* @version V1.1.0
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* @date 11-January-2013
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* @brief This file provides firmware functions to manage the following
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* functionalities of the HASH / HMAC Processor (HASH) peripheral:
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* - Initialization and Configuration functions
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* - Message Digest generation functions
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* - context swapping functions
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* - DMA interface function
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* - Interrupts and flags management
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*
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@verbatim
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===================================================================
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##### How to use this driver #####
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===================================================================
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*** HASH operation : ***
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========================
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[..]
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(#) Enable the HASH controller clock using
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RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE) function.
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(#) Initialise the HASH using HASH_Init() function.
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(#) Reset the HASH processor core, so that the HASH will be ready
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to compute he message digest of a new message by using HASH_Reset() function.
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(#) Enable the HASH controller using the HASH_Cmd() function.
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(#) if using DMA for Data input transfer, Activate the DMA Request
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using HASH_DMACmd() function
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(#) if DMA is not used for data transfer, use HASH_DataIn() function
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to enter data to IN FIFO.
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(#) Configure the Number of valid bits in last word of the message
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using HASH_SetLastWordValidBitsNbr() function.
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(#) if the message length is not an exact multiple of 512 bits,
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then the function HASH_StartDigest() must be called to launch the computation
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of the final digest.
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(#) Once computed, the digest can be read using HASH_GetDigest() function.
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(#) To control HASH events you can use one of the following wo methods:
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(++) Check on HASH flags using the HASH_GetFlagStatus() function.
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(++) Use HASH interrupts through the function HASH_ITConfig() at
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initialization phase and HASH_GetITStatus() function into
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interrupt routines in hashing phase.
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After checking on a flag you should clear it using HASH_ClearFlag()
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function. And after checking on an interrupt event you should
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clear it using HASH_ClearITPendingBit() function.
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(#) Save and restore hash processor context using
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HASH_SaveContext() and HASH_RestoreContext() functions.
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*** HMAC operation : ***
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========================
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[..] The HMAC algorithm is used for message authentication, by
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irreversibly binding the message being processed to a key chosen
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by the user.
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For HMAC specifications, refer to "HMAC: keyed-hashing for message
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authentication, H. Krawczyk, M. Bellare, R. Canetti, February 1997"
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[..] Basically, the HMAC algorithm consists of two nested hash operations:
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HMAC(message) = Hash[((key | pad) XOR 0x5C) | Hash(((key | pad) XOR 0x36) | message)]
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where:
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(+) "pad" is a sequence of zeroes needed to extend the key to the
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length of the underlying hash function data block (that is
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512 bits for both the SHA-1 and MD5 hash algorithms)
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(+) "|" represents the concatenation operator
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[..]To compute the HMAC, four different phases are required:
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(#) Initialise the HASH using HASH_Init() function to do HMAC
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operation.
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(#) The key (to be used for the inner hash function) is then given to the core.
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This operation follows the same mechanism as the one used to send the
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message in the hash operation (that is, by HASH_DataIn() function and,
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finally, HASH_StartDigest() function.
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(#) Once the last word has been entered and computation has started,
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the hash processor elaborates the key. It is then ready to accept the message
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text using the same mechanism as the one used to send the message in the
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hash operation.
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(#) After the first hash round, the hash processor returns "ready" to indicate
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that it is ready to receive the key to be used for the outer hash function
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(normally, this key is the same as the one used for the inner hash function).
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When the last word of the key is entered and computation starts, the HMAC
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result is made available using HASH_GetDigest() function.
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@endverbatim
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*
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
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*
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* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
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* You may not use this file except in compliance with the License.
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* You may obtain a copy of the License at:
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*
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* http://www.st.com/software_license_agreement_liberty_v2
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f4xx_hash.h" |
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#include "stm32f4xx_rcc.h" |
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/** @addtogroup STM32F4xx_StdPeriph_Driver
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* @{
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*/
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/** @defgroup HASH
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* @brief HASH driver modules
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* @{
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*/
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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/* Private functions ---------------------------------------------------------*/
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/** @defgroup HASH_Private_Functions
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* @{
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*/
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/** @defgroup HASH_Group1 Initialization and Configuration functions
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* @brief Initialization and Configuration functions
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*
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@verbatim
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===============================================================================
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##### Initialization and Configuration functions #####
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===============================================================================
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[..] This section provides functions allowing to
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(+) Initialize the HASH peripheral
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(+) Configure the HASH Processor
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(+) MD5/SHA1,
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(+) HASH/HMAC,
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(+) datatype
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(+) HMAC Key (if mode = HMAC)
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(+) Reset the HASH Processor
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@endverbatim
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* @{
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*/
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/**
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* @brief De-initializes the HASH peripheral registers to their default reset values
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* @param None
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* @retval None
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*/
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void HASH_DeInit(void) |
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{ |
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/* Enable HASH reset state */
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RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_HASH, ENABLE); |
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/* Release HASH from reset state */
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RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_HASH, DISABLE); |
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} |
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/**
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* @brief Initializes the HASH peripheral according to the specified parameters
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* in the HASH_InitStruct structure.
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* @note the hash processor is reset when calling this function so that the
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* HASH will be ready to compute the message digest of a new message.
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* There is no need to call HASH_Reset() function.
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* @param HASH_InitStruct: pointer to a HASH_InitTypeDef structure that contains
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* the configuration information for the HASH peripheral.
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* @note The field HASH_HMACKeyType in HASH_InitTypeDef must be filled only
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* if the algorithm mode is HMAC.
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* @retval None
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*/
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void HASH_Init(HASH_InitTypeDef* HASH_InitStruct)
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{ |
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/* Check the parameters */
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assert_param(IS_HASH_ALGOSELECTION(HASH_InitStruct->HASH_AlgoSelection)); |
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assert_param(IS_HASH_DATATYPE(HASH_InitStruct->HASH_DataType)); |
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assert_param(IS_HASH_ALGOMODE(HASH_InitStruct->HASH_AlgoMode)); |
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/* Configure the Algorithm used, algorithm mode and the datatype */
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HASH->CR &= ~ (HASH_CR_ALGO | HASH_CR_DATATYPE | HASH_CR_MODE); |
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HASH->CR |= (HASH_InitStruct->HASH_AlgoSelection | \ |
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HASH_InitStruct->HASH_DataType | \ |
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HASH_InitStruct->HASH_AlgoMode); |
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/* if algorithm mode is HMAC, set the Key */
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if(HASH_InitStruct->HASH_AlgoMode == HASH_AlgoMode_HMAC)
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{ |
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assert_param(IS_HASH_HMAC_KEYTYPE(HASH_InitStruct->HASH_HMACKeyType)); |
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HASH->CR &= ~HASH_CR_LKEY; |
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HASH->CR |= HASH_InitStruct->HASH_HMACKeyType; |
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} |
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/* Reset the HASH processor core, so that the HASH will be ready to compute
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the message digest of a new message */
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HASH->CR |= HASH_CR_INIT; |
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} |
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/**
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* @brief Fills each HASH_InitStruct member with its default value.
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* @param HASH_InitStruct : pointer to a HASH_InitTypeDef structure which will
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* be initialized.
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* @note The default values set are : Processor mode is HASH, Algorithm selected is SHA1,
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* Data type selected is 32b and HMAC Key Type is short key.
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* @retval None
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*/
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void HASH_StructInit(HASH_InitTypeDef* HASH_InitStruct)
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{ |
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/* Initialize the HASH_AlgoSelection member */
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HASH_InitStruct->HASH_AlgoSelection = HASH_AlgoSelection_SHA1; |
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/* Initialize the HASH_AlgoMode member */
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HASH_InitStruct->HASH_AlgoMode = HASH_AlgoMode_HASH; |
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/* Initialize the HASH_DataType member */
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HASH_InitStruct->HASH_DataType = HASH_DataType_32b; |
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/* Initialize the HASH_HMACKeyType member */
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HASH_InitStruct->HASH_HMACKeyType = HASH_HMACKeyType_ShortKey; |
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} |
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/**
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* @brief Resets the HASH processor core, so that the HASH will be ready
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* to compute the message digest of a new message.
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* @note Calling this function will clear the HASH_SR_DCIS (Digest calculation
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* completion interrupt status) bit corresponding to HASH_IT_DCI
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* interrupt and HASH_FLAG_DCIS flag.
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* @param None
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* @retval None
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*/
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void HASH_Reset(void) |
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{ |
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/* Reset the HASH processor core */
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HASH->CR |= HASH_CR_INIT; |
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} |
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/**
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* @}
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*/
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/** @defgroup HASH_Group2 Message Digest generation functions
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* @brief Message Digest generation functions
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*
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@verbatim
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===============================================================================
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##### Message Digest generation functions #####
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===============================================================================
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[..] This section provides functions allowing the generation of message digest:
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(+) Push data in the IN FIFO : using HASH_DataIn()
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(+) Get the number of words set in IN FIFO, use HASH_GetInFIFOWordsNbr()
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(+) set the last word valid bits number using HASH_SetLastWordValidBitsNbr()
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(+) start digest calculation : using HASH_StartDigest()
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(+) Get the Digest message : using HASH_GetDigest()
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@endverbatim
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* @{
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*/
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/**
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* @brief Configure the Number of valid bits in last word of the message
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* @param ValidNumber: Number of valid bits in last word of the message.
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* This parameter must be a number between 0 and 0x1F.
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* - 0x00: All 32 bits of the last data written are valid
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* - 0x01: Only bit [0] of the last data written is valid
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* - 0x02: Only bits[1:0] of the last data written are valid
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* - 0x03: Only bits[2:0] of the last data written are valid
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* - ...
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* - 0x1F: Only bits[30:0] of the last data written are valid
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* @note The Number of valid bits must be set before to start the message
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* digest competition (in Hash and HMAC) and key treatment(in HMAC).
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* @retval None
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*/
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void HASH_SetLastWordValidBitsNbr(uint16_t ValidNumber)
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{ |
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/* Check the parameters */
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assert_param(IS_HASH_VALIDBITSNUMBER(ValidNumber)); |
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/* Configure the Number of valid bits in last word of the message */
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HASH->STR &= ~(HASH_STR_NBW); |
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HASH->STR |= ValidNumber; |
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} |
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/**
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* @brief Writes data in the Data Input FIFO
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* @param Data: new data of the message to be processed.
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* @retval None
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*/
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void HASH_DataIn(uint32_t Data)
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{ |
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/* Write in the DIN register a new data */
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HASH->DIN = Data; |
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} |
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/**
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* @brief Returns the number of words already pushed into the IN FIFO.
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* @param None
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* @retval The value of words already pushed into the IN FIFO.
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*/
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uint8_t HASH_GetInFIFOWordsNbr(void)
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{ |
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/* Return the value of NBW bits */
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return ((HASH->CR & HASH_CR_NBW) >> 8); |
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} |
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/**
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* @brief Provides the message digest result.
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* @note In MD5 mode, Data[7] to Data[4] filed of HASH_MsgDigest structure is not used
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* and is read as zero.
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* In SHA-1 mode, Data[7] to Data[5] filed of HASH_MsgDigest structure is not used
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* and is read as zero.
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* In SHA-224 mode, Data[7] filed of HASH_MsgDigest structure is not used
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* and is read as zero.
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* @param HASH_MessageDigest: pointer to a HASH_MsgDigest structure which will
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* hold the message digest result
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* @retval None
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*/
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void HASH_GetDigest(HASH_MsgDigest* HASH_MessageDigest)
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{ |
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/* Get the data field */
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HASH_MessageDigest->Data[0] = HASH->HR[0]; |
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HASH_MessageDigest->Data[1] = HASH->HR[1]; |
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HASH_MessageDigest->Data[2] = HASH->HR[2]; |
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HASH_MessageDigest->Data[3] = HASH->HR[3]; |
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HASH_MessageDigest->Data[4] = HASH->HR[4]; |
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HASH_MessageDigest->Data[5] = HASH_DIGEST->HR[5]; |
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HASH_MessageDigest->Data[6] = HASH_DIGEST->HR[6]; |
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HASH_MessageDigest->Data[7] = HASH_DIGEST->HR[7]; |
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} |
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/**
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* @brief Starts the message padding and calculation of the final message
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* @param None
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* @retval None
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*/
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void HASH_StartDigest(void) |
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{ |
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/* Start the Digest calculation */
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HASH->STR |= HASH_STR_DCAL; |
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} |
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/**
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* @}
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*/
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/** @defgroup HASH_Group3 Context swapping functions
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* @brief Context swapping functions
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*
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@verbatim
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===============================================================================
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##### Context swapping functions #####
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===============================================================================
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[..] This section provides functions allowing to save and store HASH Context
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[..] It is possible to interrupt a HASH/HMAC process to perform another processing
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with a higher priority, and to complete the interrupted process later on, when
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the higher priority task is complete. To do so, the context of the interrupted
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task must be saved from the HASH registers to memory, and then be restored
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from memory to the HASH registers.
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(#) To save the current context, use HASH_SaveContext() function
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(#) To restore the saved context, use HASH_RestoreContext() function
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@endverbatim
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* @{
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*/
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/**
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* @brief Save the Hash peripheral Context.
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* @note The context can be saved only when no block is currently being
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* processed. So user must wait for DINIS = 1 (the last block has been
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* processed and the input FIFO is empty) or NBW != 0 (the FIFO is not
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* full and no processing is ongoing).
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* @param HASH_ContextSave: pointer to a HASH_Context structure that contains
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* the repository for current context.
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* @retval None
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*/
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void HASH_SaveContext(HASH_Context* HASH_ContextSave)
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{ |
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uint8_t i = 0;
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/* save context registers */
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HASH_ContextSave->HASH_IMR = HASH->IMR; |
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HASH_ContextSave->HASH_STR = HASH->STR; |
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HASH_ContextSave->HASH_CR = HASH->CR; |
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for(i=0; i<=53;i++) |
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{ |
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HASH_ContextSave->HASH_CSR[i] = HASH->CSR[i]; |
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} |
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} |
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/**
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* @brief Restore the Hash peripheral Context.
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* @note After calling this function, user can restart the processing from the
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* point where it has been interrupted.
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* @param HASH_ContextRestore: pointer to a HASH_Context structure that contains
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* the repository for saved context.
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* @retval None
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*/
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void HASH_RestoreContext(HASH_Context* HASH_ContextRestore)
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{ |
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uint8_t i = 0;
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/* restore context registers */
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HASH->IMR = HASH_ContextRestore->HASH_IMR; |
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HASH->STR = HASH_ContextRestore->HASH_STR; |
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HASH->CR = HASH_ContextRestore->HASH_CR; |
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/* Initialize the hash processor */
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HASH->CR |= HASH_CR_INIT; |
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/* continue restoring context registers */
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for(i=0; i<=53;i++) |
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{ |
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HASH->CSR[i] = HASH_ContextRestore->HASH_CSR[i]; |
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} |
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} |
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/**
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* @}
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*/
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/** @defgroup HASH_Group4 HASH's DMA interface Configuration function
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* @brief HASH's DMA interface Configuration function
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*
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@verbatim
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===============================================================================
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##### HASH's DMA interface Configuration function #####
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===============================================================================
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[..] This section provides functions allowing to configure the DMA interface for
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HASH/ HMAC data input transfer.
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[..] When the DMA mode is enabled (using the HASH_DMACmd() function), data can be
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sent to the IN FIFO using the DMA peripheral.
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@endverbatim
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* @{
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*/
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/**
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* @brief Enables or disables auto-start message padding and
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* calculation of the final message digest at the end of DMA transfer.
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* @param NewState: new state of the selected HASH DMA transfer request.
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* This parameter can be: ENABLE or DISABLE.
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* @retval None
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*/
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void HASH_AutoStartDigest(FunctionalState NewState)
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{ |
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/* Check the parameters */
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assert_param(IS_FUNCTIONAL_STATE(NewState)); |
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if (NewState != DISABLE)
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{ |
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/* Enable the auto start of the final message digest at the end of DMA transfer */
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HASH->CR &= ~HASH_CR_MDMAT; |
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} |
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else
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{ |
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/* Disable the auto start of the final message digest at the end of DMA transfer */
|
478 |
HASH->CR |= HASH_CR_MDMAT; |
479 |
} |
480 |
} |
481 |
|
482 |
/**
|
483 |
* @brief Enables or disables the HASH DMA interface.
|
484 |
* @note The DMA is disabled by hardware after the end of transfer.
|
485 |
* @param NewState: new state of the selected HASH DMA transfer request.
|
486 |
* This parameter can be: ENABLE or DISABLE.
|
487 |
* @retval None
|
488 |
*/
|
489 |
void HASH_DMACmd(FunctionalState NewState)
|
490 |
{ |
491 |
/* Check the parameters */
|
492 |
assert_param(IS_FUNCTIONAL_STATE(NewState)); |
493 |
|
494 |
if (NewState != DISABLE)
|
495 |
{ |
496 |
/* Enable the HASH DMA request */
|
497 |
HASH->CR |= HASH_CR_DMAE; |
498 |
} |
499 |
else
|
500 |
{ |
501 |
/* Disable the HASH DMA request */
|
502 |
HASH->CR &= ~HASH_CR_DMAE; |
503 |
} |
504 |
} |
505 |
/**
|
506 |
* @}
|
507 |
*/
|
508 |
|
509 |
/** @defgroup HASH_Group5 Interrupts and flags management functions
|
510 |
* @brief Interrupts and flags management functions
|
511 |
*
|
512 |
@verbatim
|
513 |
===============================================================================
|
514 |
##### Interrupts and flags management functions #####
|
515 |
===============================================================================
|
516 |
|
517 |
[..] This section provides functions allowing to configure the HASH Interrupts and
|
518 |
to get the status and clear flags and Interrupts pending bits.
|
519 |
|
520 |
[..] The HASH provides 2 Interrupts sources and 5 Flags:
|
521 |
|
522 |
*** Flags : ***
|
523 |
===============
|
524 |
[..]
|
525 |
(#) HASH_FLAG_DINIS : set when 16 locations are free in the Data IN FIFO
|
526 |
which means that a new block (512 bit) can be entered into the input buffer.
|
527 |
|
528 |
(#) HASH_FLAG_DCIS : set when Digest calculation is complete
|
529 |
|
530 |
(#) HASH_FLAG_DMAS : set when HASH's DMA interface is enabled (DMAE=1) or
|
531 |
a transfer is ongoing. This Flag is cleared only by hardware.
|
532 |
|
533 |
(#) HASH_FLAG_BUSY : set when The hash core is processing a block of data
|
534 |
This Flag is cleared only by hardware.
|
535 |
|
536 |
(#) HASH_FLAG_DINNE : set when Data IN FIFO is not empty which means that
|
537 |
the Data IN FIFO contains at least one word of data. This Flag is cleared
|
538 |
only by hardware.
|
539 |
|
540 |
*** Interrupts : ***
|
541 |
====================
|
542 |
[..]
|
543 |
(#) HASH_IT_DINI : if enabled, this interrupt source is pending when 16
|
544 |
locations are free in the Data IN FIFO which means that a new block (512 bit)
|
545 |
can be entered into the input buffer. This interrupt source is cleared using
|
546 |
HASH_ClearITPendingBit(HASH_IT_DINI) function.
|
547 |
|
548 |
(#) HASH_IT_DCI : if enabled, this interrupt source is pending when Digest
|
549 |
calculation is complete. This interrupt source is cleared using
|
550 |
HASH_ClearITPendingBit(HASH_IT_DCI) function.
|
551 |
|
552 |
*** Managing the HASH controller events : ***
|
553 |
=============================================
|
554 |
[..] The user should identify which mode will be used in his application to manage
|
555 |
the HASH controller events: Polling mode or Interrupt mode.
|
556 |
|
557 |
(#) In the Polling Mode it is advised to use the following functions:
|
558 |
(++) HASH_GetFlagStatus() : to check if flags events occur.
|
559 |
(++) HASH_ClearFlag() : to clear the flags events.
|
560 |
|
561 |
(#) In the Interrupt Mode it is advised to use the following functions:
|
562 |
(++) HASH_ITConfig() : to enable or disable the interrupt source.
|
563 |
(++) HASH_GetITStatus() : to check if Interrupt occurs.
|
564 |
(++) HASH_ClearITPendingBit() : to clear the Interrupt pending Bit
|
565 |
(corresponding Flag).
|
566 |
|
567 |
@endverbatim
|
568 |
* @{
|
569 |
*/
|
570 |
|
571 |
/**
|
572 |
* @brief Enables or disables the specified HASH interrupts.
|
573 |
* @param HASH_IT: specifies the HASH interrupt source to be enabled or disabled.
|
574 |
* This parameter can be any combination of the following values:
|
575 |
* @arg HASH_IT_DINI: Data Input interrupt
|
576 |
* @arg HASH_IT_DCI: Digest Calculation Completion Interrupt
|
577 |
* @param NewState: new state of the specified HASH interrupt.
|
578 |
* This parameter can be: ENABLE or DISABLE.
|
579 |
* @retval None
|
580 |
*/
|
581 |
void HASH_ITConfig(uint32_t HASH_IT, FunctionalState NewState)
|
582 |
{ |
583 |
/* Check the parameters */
|
584 |
assert_param(IS_HASH_IT(HASH_IT)); |
585 |
assert_param(IS_FUNCTIONAL_STATE(NewState)); |
586 |
|
587 |
if (NewState != DISABLE)
|
588 |
{ |
589 |
/* Enable the selected HASH interrupt */
|
590 |
HASH->IMR |= HASH_IT; |
591 |
} |
592 |
else
|
593 |
{ |
594 |
/* Disable the selected HASH interrupt */
|
595 |
HASH->IMR &= (uint32_t)(~HASH_IT); |
596 |
} |
597 |
} |
598 |
|
599 |
/**
|
600 |
* @brief Checks whether the specified HASH flag is set or not.
|
601 |
* @param HASH_FLAG: specifies the HASH flag to check.
|
602 |
* This parameter can be one of the following values:
|
603 |
* @arg HASH_FLAG_DINIS: Data input interrupt status flag
|
604 |
* @arg HASH_FLAG_DCIS: Digest calculation completion interrupt status flag
|
605 |
* @arg HASH_FLAG_BUSY: Busy flag
|
606 |
* @arg HASH_FLAG_DMAS: DMAS Status flag
|
607 |
* @arg HASH_FLAG_DINNE: Data Input register (DIN) not empty status flag
|
608 |
* @retval The new state of HASH_FLAG (SET or RESET)
|
609 |
*/
|
610 |
FlagStatus HASH_GetFlagStatus(uint32_t HASH_FLAG) |
611 |
{ |
612 |
FlagStatus bitstatus = RESET; |
613 |
uint32_t tempreg = 0;
|
614 |
|
615 |
/* Check the parameters */
|
616 |
assert_param(IS_HASH_GET_FLAG(HASH_FLAG)); |
617 |
|
618 |
/* check if the FLAG is in CR register */
|
619 |
if ((HASH_FLAG & HASH_FLAG_DINNE) != (uint32_t)RESET )
|
620 |
{ |
621 |
tempreg = HASH->CR; |
622 |
} |
623 |
else /* The FLAG is in SR register */ |
624 |
{ |
625 |
tempreg = HASH->SR; |
626 |
} |
627 |
|
628 |
/* Check the status of the specified HASH flag */
|
629 |
if ((tempreg & HASH_FLAG) != (uint32_t)RESET)
|
630 |
{ |
631 |
/* HASH is set */
|
632 |
bitstatus = SET; |
633 |
} |
634 |
else
|
635 |
{ |
636 |
/* HASH_FLAG is reset */
|
637 |
bitstatus = RESET; |
638 |
} |
639 |
|
640 |
/* Return the HASH_FLAG status */
|
641 |
return bitstatus;
|
642 |
} |
643 |
/**
|
644 |
* @brief Clears the HASH flags.
|
645 |
* @param HASH_FLAG: specifies the flag to clear.
|
646 |
* This parameter can be any combination of the following values:
|
647 |
* @arg HASH_FLAG_DINIS: Data Input Flag
|
648 |
* @arg HASH_FLAG_DCIS: Digest Calculation Completion Flag
|
649 |
* @retval None
|
650 |
*/
|
651 |
void HASH_ClearFlag(uint32_t HASH_FLAG)
|
652 |
{ |
653 |
/* Check the parameters */
|
654 |
assert_param(IS_HASH_CLEAR_FLAG(HASH_FLAG)); |
655 |
|
656 |
/* Clear the selected HASH flags */
|
657 |
HASH->SR = ~(uint32_t)HASH_FLAG; |
658 |
} |
659 |
/**
|
660 |
* @brief Checks whether the specified HASH interrupt has occurred or not.
|
661 |
* @param HASH_IT: specifies the HASH interrupt source to check.
|
662 |
* This parameter can be one of the following values:
|
663 |
* @arg HASH_IT_DINI: Data Input interrupt
|
664 |
* @arg HASH_IT_DCI: Digest Calculation Completion Interrupt
|
665 |
* @retval The new state of HASH_IT (SET or RESET).
|
666 |
*/
|
667 |
ITStatus HASH_GetITStatus(uint32_t HASH_IT) |
668 |
{ |
669 |
ITStatus bitstatus = RESET; |
670 |
uint32_t tmpreg = 0;
|
671 |
|
672 |
/* Check the parameters */
|
673 |
assert_param(IS_HASH_GET_IT(HASH_IT)); |
674 |
|
675 |
|
676 |
/* Check the status of the specified HASH interrupt */
|
677 |
tmpreg = HASH->SR; |
678 |
|
679 |
if (((HASH->IMR & tmpreg) & HASH_IT) != RESET)
|
680 |
{ |
681 |
/* HASH_IT is set */
|
682 |
bitstatus = SET; |
683 |
} |
684 |
else
|
685 |
{ |
686 |
/* HASH_IT is reset */
|
687 |
bitstatus = RESET; |
688 |
} |
689 |
/* Return the HASH_IT status */
|
690 |
return bitstatus;
|
691 |
} |
692 |
|
693 |
/**
|
694 |
* @brief Clears the HASH interrupt pending bit(s).
|
695 |
* @param HASH_IT: specifies the HASH interrupt pending bit(s) to clear.
|
696 |
* This parameter can be any combination of the following values:
|
697 |
* @arg HASH_IT_DINI: Data Input interrupt
|
698 |
* @arg HASH_IT_DCI: Digest Calculation Completion Interrupt
|
699 |
* @retval None
|
700 |
*/
|
701 |
void HASH_ClearITPendingBit(uint32_t HASH_IT)
|
702 |
{ |
703 |
/* Check the parameters */
|
704 |
assert_param(IS_HASH_IT(HASH_IT)); |
705 |
|
706 |
/* Clear the selected HASH interrupt pending bit */
|
707 |
HASH->SR = (uint32_t)(~HASH_IT); |
708 |
} |
709 |
|
710 |
/**
|
711 |
* @}
|
712 |
*/
|
713 |
|
714 |
/**
|
715 |
* @}
|
716 |
*/
|
717 |
|
718 |
/**
|
719 |
* @}
|
720 |
*/
|
721 |
|
722 |
/**
|
723 |
* @}
|
724 |
*/
|
725 |
|
726 |
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|