AMiRo-OS

/************************************************************************************//**

* \file         Demo\ARMCM4_STM32_Olimex_STM32E407_GCC\Boot\blt_conf.h

* \brief        Bootloader configuration header file.

* \ingroup      Boot_ARMCM4_STM32_Olimex_STM32E407_GCC

* \internal

*----------------------------------------------------------------------------------------

*                          C O P Y R I G H T

*----------------------------------------------------------------------------------------

*   Copyright (c) 2013  by Feaser    http://www.feaser.com    All rights reserved

*

*----------------------------------------------------------------------------------------

*                            L I C E N S E

*----------------------------------------------------------------------------------------

* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or

* modify it under the terms of the GNU General Public License as published by the Free

* Software Foundation, either version 3 of the License, or (at your option) any later

* version.

*

* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;

* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR

* PURPOSE. See the GNU General Public License for more details.

*

* You should have received a copy of the GNU General Public License along with OpenBLT.

* If not, see <http://www.gnu.org/licenses/>.

*

* A special exception to the GPL is included to allow you to distribute a combined work

* that includes OpenBLT without being obliged to provide the source code for any

* proprietary components. The exception text is included at the bottom of the license

* file <license.html>.

*

* \endinternal

****************************************************************************************/

#ifndef BLT_CONF_H

#define BLT_CONF_H

/****************************************************************************************

*   C P U   D R I V E R   C O N F I G U R A T I O N

****************************************************************************************/

/* To properly initialize the baudrate clocks of the communication interface, typically

 * the speed of the crystal oscillator and/or the speed at which the system runs is

 * needed. Set these through configurables BOOT_CPU_XTAL_SPEED_KHZ and

 * BOOT_CPU_SYSTEM_SPEED_KHZ, respectively. To enable data exchange with the host that is

 * not dependent on the targets architecture, the byte ordering needs to be known.

 * Setting BOOT_CPU_BYTE_ORDER_MOTOROLA to 1 selects little endian mode and 0 selects

 * big endian mode.

 *

 * Set BOOT_CPU_USER_PROGRAM_START_HOOK to 1 if you would like a hook function to be

 * called the moment the user program is about to be started. This could be used to

 * de-initialize application specific parts, for example to stop blinking an LED, etc.

 */

/** \brief Frequency of the external crystal oscillator. */

#define BOOT_CPU_XTAL_SPEED_KHZ          (8000)

/** \brief Desired system speed. */

#define BOOT_CPU_SYSTEM_SPEED_KHZ        (168000)

/** \brief Motorola or Intel style byte ordering. */

#define BOOT_CPU_BYTE_ORDER_MOTOROLA     (0)

/** \brief Enable/disable hook function call right before user program start. */

#define BOOT_CPU_USER_PROGRAM_START_HOOK (1)

/****************************************************************************************

*   B O O T L O A D E R   O F   M A I N   D E V I C E

****************************************************************************************/

/* It is important to initialize if the bootloader is part of the main device. In this

 * case some backdoor loops have to stay opened and backdoor loops of other bootloaders

 * have to be controlled by this bootloader. Additionally the bootloader should be able

 * to send program code of user programs for other devices.

 * Make sure that one of the communication interfaces is the gateway!

 */

/** \brief Bootloader of main device. */

#define BOOTLOADER_OF_MAIN_DEVICE       (1)

/****************************************************************************************

*   C O M M U N I C A T I O N   I N T E R F A C E   C O N F I G U R A T I O N

****************************************************************************************/

/* The CAN communication interface is selected by setting the BOOT_COM_CAN_ENABLE

 * configurable to 1. Configurable BOOT_COM_CAN_BAUDRATE selects the communication speed

 * in bits/second. Two CAN messages are reserved for communication with the host. The

 * message identifier for sending data from the target to the host is configured with

 * BOOT_COM_CAN_TXMSG_ID. The one for receiving data from the host is configured with

 * BOOT_COM_CAN_RXMSG_ID. The maximum amount of data bytes in a message for data

 * transmission and reception is set through BOOT_COM_CAN_TX_MAX_DATA and

 * BOOT_COM_CAN_RX_MAX_DATA, respectively. It is common for a microcontroller to have more

 * than 1 CAN controller on board. The zero-based BOOT_COM_CAN_CHANNEL_INDEX selects the

 * CAN controller channel.

 *

 */

/** \brief Enable/disable CAN transport layer. */

#define BOOT_GATE_CAN_ENABLE            (1)

/** \brief Configure the desired CAN baudrate. */

#define BOOT_COM_CAN_BAUDRATE           (1000000)

/** \brief Configure CAN message ID target->host. */

#define BOOT_COM_CAN_TX_MSG_ID          (0x700)

/** \brief Configure number of bytes in the target->host CAN message. */

#define BOOT_COM_CAN_TX_MAX_DATA        (255)

/** \brief Configure CAN message ID host->target. */

#define BOOT_COM_CAN_RX_MSG_ID          (0x600)

/** \brief Configure number of bytes in the host->target CAN message. */

#define BOOT_COM_CAN_RX_MAX_DATA        (255)

/** \brief Select the desired CAN peripheral as a zero based index. */

#define BOOT_COM_CAN_CHANNEL_INDEX      (0)

/** \brief Configure CAN message acknowledgement ID addition (ORed with original ID). */

#define BOOT_COM_CAN_MSG_ACK            (0x001)

/** \brief Configure CAN message ID addition for continuous messages (ORed with original ID). */

#define BOOT_COM_CAN_MSG_SUBSEQUENT     (0x002)

/**

 * \brief Configure device ID for communication (start with 1).

 * \details The device ID is a 32 bit integer, which can be interpreted bytewise:

 *            <AMiRo_revision>:<moduleID>:<moduleVersion_major>:<moduleVersion_minor>

 *          For this module the according values are

 *            1:1:1:1 = 0x01010101

 */

#define BOOT_COM_DEVICE_ID              (0x01010102)

/* The UART communication interface is selected by setting the BOOT_COM_UART_ENABLE

 * configurable to 1. Configurable BOOT_COM_UART_BAUDRATE selects the communication speed

 * in bits/second. The maximum amount of data bytes in a message for data transmission

 * and reception is set through BOOT_COM_UART_TX_MAX_DATA and BOOT_COM_UART_RX_MAX_DATA,

 * respectively. It is common for a microcontroller to have more than 1 UART interface

 * on board. The zero-based BOOT_COM_UART_CHANNEL_INDEX selects the UART interface.

 *

 */

/** \brief Enable/disable UART transport layer. */

#define BOOT_COM_UART_ENABLE            (1)

/** \brief Enable/disable BLUETOOTH UART transport layer. */

#define BOOT_COM_BLUETOOTH_UART_ENABLE  (0)

/** \brief Configure the desired communication speed. */

#define BOOT_COM_UART_BAUDRATE          (115200)

/** \brief Configure number of bytes in the target->host data packet. */

#define BOOT_COM_UART_TX_MAX_DATA       (255)

/** \brief Configure number of bytes in the host->target data packet. */

#define BOOT_COM_UART_RX_MAX_DATA       (255)

/** \brief Select the desired UART peripheral as a zero based index. */

#define BOOT_COM_UART_CHANNEL_INDEX     (0)

/** \brief Select the desired BLUETOOTH UART peripheral as a zero based index. */

#define BOOT_COM_BLUETOOTH_UART_CHANNEL_INDEX (2)

/* The NET communication interface for firmware updates via TCP/IP is selected by setting

 * the BOOT_COM_NET_ENABLE configurable to 1. The maximum amount of data bytes in a

 * message for data transmission and reception is set through BOOT_COM_NET_TX_MAX_DATA

 * and BOOT_COM_NET_RX_MAX_DATA, respectively. The default IP address is configured

 * with the macros BOOT_COM_NET_IPADDRx. The default netmask is configued with the macros

 * BOOT_COM_NET_NETMASKx. The default gateway is configured with the macros

 * BOOT_COM_NET_GATEWAYx. The bootloader acts and a TCP/IP server. The port the server

 * listen on for connections is configured with BOOT_COM_NET_PORT.

 */

/** \brief Enable/disable the NET transport layer. */

#define BOOT_COM_NET_ENABLE              (0)

/** \brief Configure number of bytes in the target->host data packet. */

#define BOOT_COM_NET_TX_MAX_DATA         (64)

/** \brief Configure number of bytes in the host->target data packet. */

#define BOOT_COM_NET_RX_MAX_DATA         (64)

/** \brief Configure the port that the TCP/IP server listens on */

#define BOOT_COM_NET_PORT                (1000)

/** \brief Configure the 1st byte of the IP address */

#define BOOT_COM_NET_IPADDR0             (169)

/** \brief Configure the 2nd byte of the IP address */

#define BOOT_COM_NET_IPADDR1             (254)

/** \brief Configure the 3rd byte of the IP address */

#define BOOT_COM_NET_IPADDR2             (19)

/** \brief Configure the 4th byte of the IP address */

#define BOOT_COM_NET_IPADDR3             (63)

/** \brief Configure the 1st byte of the network mask */

#define BOOT_COM_NET_NETMASK0            (255)

/** \brief Configure the 2nd byte of the network mask */

#define BOOT_COM_NET_NETMASK1            (255)

/** \brief Configure the 3rd byte of the network mask */

#define BOOT_COM_NET_NETMASK2            (0)

/** \brief Configure the 4th byte of the network mask */

#define BOOT_COM_NET_NETMASK3            (0)

/** \brief Configure the 1st byte of the gateway address */

#define BOOT_COM_NET_GATEWAY0            (169)

/** \brief Configure the 2nd byte of the gateway address */

#define BOOT_COM_NET_GATEWAY1            (254)

/** \brief Configure the 3rd byte of the gateway address */

#define BOOT_COM_NET_GATEWAY2            (19)

/** \brief Configure the 4th byte of the gateway address */

#define BOOT_COM_NET_GATEWAY3            (1)

/** \brief Enable/disable a hook function that is called when the IP address is about

 *         to be set. This allows a dynamic override of the BOOT_COM_NET_IPADDRx values.

 */

#define BOOT_COM_NET_IPADDR_HOOK_ENABLE  (0)

/** \brief Enable/disable a hook function that is called when the netmask is about

 *         to be set. This allows a dynamic override of the BOOT_COM_NET_NETMASKx values.

 */

#define BOOT_COM_NET_NETMASK_HOOK_ENABLE (0)

/** \brief Enable/disable a hook function that is called when the gateway address is

 *         about to be set. This allows a dynamic override of the BOOT_COM_NET_GATEWAYx

 *         values.

 */

#define BOOT_COM_NET_GATEWAY_HOOK_ENABLE (0)

/****************************************************************************************

*   B A C K D O O R    C O N F I G U R A T I O N

****************************************************************************************/

#if (BOOT_COM_NET_ENABLE > 0)

/* Override the default time that the backdoor is open if firmware updates via TCP/IP

 * are supported. in this case a reactivation of the bootloader results in a re-

 * initialization of the ethernet MAC. when directly connected to the ethernet port of

 * a PC this will go relatively fast (depending on what MS Windows is being used), but

 * when connected to the network via a router this can take several seconds. feel free to

 * shorten/lengthen this time for finetuning. the only downside of a long backdoor open

 * time is that the starting of the user program will also be delayed for this time.

 *

 * Also note that when the target is directly connected to the ethernet port of a PC,

 * the checkbox "Automatically retry socket connection" should be checked in the

 * Microboot settings. if connecting via a router the uncheck this checkbox.

 */

#define BACKDOOR_ENTRY_TIMEOUT_MS  (10000)

#endif

/****************************************************************************************

*   F I L E   S Y S T E M   I N T E R F A C E   C O N F I G U R A T I O N

****************************************************************************************/

/* The file system interface is selected by setting the BOOT_FILE_SYS_ENABLE configurable

 * to 1. This enables support for firmware updates from a file stored on a locally

 * attached file system such as an SD-card. Note that this interface can be enabled

 * together with one of the remote communication interfaces such as UART, CAN or USB.

 *

 * Set BOOT_FILE_LOGGING_ENABLE to 1 if you would like log messages to be created during

 * a firmware update. The hook function FileFirmwareUpdateLogHook() will be called each

 * time a new string formatted log entry is available. This could be used during testing

 * by outputting the string on UART or to create a log file on the file system itself.

 *

 * Set BOOT_FILE_ERROR_HOOK_ENABLE to 1 if you would like to be informed in case an error

 * occurs during the firmware update. This could for example be used to turn on an error

 * LED to inform the user that something went wrong. Inspecting the log messages provides

 * additional information on the error cause.

 *

 * Set BOOT_FILE_STARTED_HOOK_ENABLE to 1 if you would like to be informed when a new

 * firmware update is started by the bootloader.

 *

 * Set BOOT_FILE_COMPLETED_HOOK_ENABLE to 1 if you would like to be informed when a

 * firmware update is completed by the bootloader.

 */

/** \brief Enable/disable support for firmware updates from a locally attached storage.*/

#define BOOT_FILE_SYS_ENABLE            (0)

/** \brief Enable/disable logging messages during firmware updates. */

#define BOOT_FILE_LOGGING_ENABLE        (1)

/** \brief Enable/disable a hook function that is called upon detection of an error. */

#define BOOT_FILE_ERROR_HOOK_ENABLE     (1)

/** \brief Enable/disable a hook function that is called at the start of the update. */

#define BOOT_FILE_STARTED_HOOK_ENABLE   (1)

/** \brief Enable/disable a hook function that is called at the end of the update. */

#define BOOT_FILE_COMPLETED_HOOK_ENABLE (1)

/****************************************************************************************

*   B A C K D O O R   E N T R Y   C O N F I G U R A T I O N

****************************************************************************************/

/* It is possible to implement an application specific method to force the bootloader to

 * stay active after a reset. Such a backdoor entry into the bootloader is desired in

 * situations where the user program does not run properly and therefore cannot

 * reactivate the bootloader. By enabling these hook functions, the application can

 * implement the backdoor, which overrides the default backdoor entry that is programmed

 * into the bootloader. When desired for security purposes, these hook functions can

 * also be implemented in a way that disables the backdoor entry altogether.

 */

/** \brief Enable/disable the backdoor override hook functions. */

#define BOOT_BACKDOOR_HOOKS_ENABLE      (1)

/****************************************************************************************

*   N O N - V O L A T I L E   M E M O R Y   D R I V E R   C O N F I G U R A T I O N

****************************************************************************************/

/* The NVM driver typically supports erase and program operations of the internal memory

 * present on the microcontroller. Through these hook functions the NVM driver can be

 * extended to support additional memory types such as external flash memory and serial

 * eeproms. The size of the internal memory in kilobytes is specified with configurable

 * BOOT_NVM_SIZE_KB. If desired the internal checksum writing and verification method can

 * be overridden with a application specific method by enabling configuration switch

 * BOOT_NVM_CHECKSUM_HOOKS_ENABLE.

 */

/** \brief Enable/disable the NVM hook function for supporting additional memory devices. */

#define BOOT_NVM_HOOKS_ENABLE           (0)

/** \brief Configure the size of the default memory device (typically flash EEPROM). */

#define BOOT_NVM_SIZE_KB                (1024)

/** \brief Enable/disable hooks functions to override the user program checksum handling. */

#define BOOT_NVM_CHECKSUM_HOOKS_ENABLE  (0)

/****************************************************************************************

*   W A T C H D O G   D R I V E R   C O N F I G U R A T I O N

****************************************************************************************/

/* The COP driver cannot be configured internally in the bootloader, because its use

 * and configuration is application specific. The bootloader does need to service the

 * watchdog in case it is used. When the application requires the use of a watchdog,

 * set BOOT_COP_HOOKS_ENABLE to be able to initialize and service the watchdog through

 * hook functions.

 */

/** \brief Enable/disable the hook functions for controlling the watchdog. */

#define BOOT_COP_HOOKS_ENABLE           (0)

/****************************************************************************************

*   S E E D / K E Y   S E C U R I T Y   C O N F I G U R A T I O N

****************************************************************************************/

/* A security mechanism can be enabled in the bootloader's XCP module by setting configu-

 * rable BOOT_XCP_SEED_KEY_ENABLE to 1. Before any memory erase or programming

 * operations can be performed, access to this resource need to be unlocked.

 * In the Microboot settings on tab "XCP Protection" you need to specify a DLL that

 * implements the unlocking algorithm. The demo programs are configured for the (simple)

 * algorithm in "FeaserKey.dll". The source code for this DLL is available so it can be

 * customized to your needs.

 * During the unlock sequence, Microboot requests a seed from the bootloader, which is in

 * the format of a byte array. Using this seed the unlock algorithm in the DLL computes

 * a key, which is also a byte array, and sends this back to the bootloader. The

 * bootloader then verifies this key to determine if programming and erase operations are

 * permitted.

 * After enabling this feature the hook functions XcpGetSeedHook() and XcpVerifyKeyHook()

 * are called by the bootloader to obtain the seed and to verify the key, respectively.

 */

#define BOOT_XCP_SEED_KEY_ENABLE        (0)

#endif /* BLT_CONF_H */

/*********************************** end of blt_conf.h *********************************/

/**

\defgroup   Boot_ARMCM4_STM32_Olimex_STM32E407_GCC Bootloader

\brief      Bootloader. 

\ingroup    ARMCM4_STM32_Olimex_STM32E407_GCC

*/

@echo off

cs-make --directory=../ all

@echo off

cs-make --directory=../ clean

/************************************************************************************//**

* \file         Demo\ARMCM3_STM32_Olimex_STM32P103_GCC\Boot\hooks.c

* \brief        Bootloader callback source file.

* \ingroup      Boot_ARMCM3_STM32_Olimex_STM32P103_GCC

* \internal

*----------------------------------------------------------------------------------------

*                          C O P Y R I G H T

*----------------------------------------------------------------------------------------

*   Copyright (c) 2012  by Feaser    http://www.feaser.com    All rights reserved

*

*----------------------------------------------------------------------------------------

*                            L I C E N S E

*----------------------------------------------------------------------------------------

* This file is part of OpenBLT. OpenBLT is free software: you can redistribute it and/or

* modify it under the terms of the GNU General Public License as published by the Free

* Software Foundation, either version 3 of the License, or (at your option) any later

* version.

*

* OpenBLT is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;

* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR

* PURPOSE. See the GNU General Public License for more details.

*

* You should have received a copy of the GNU General Public License along with OpenBLT.

* If not, see <http://www.gnu.org/licenses/>.

*

* A special exception to the GPL is included to allow you to distribute a combined work 

* that includes OpenBLT without being obliged to provide the source code for any 

* proprietary components. The exception text is included at the bottom of the license

* file <license.html>.

* 

* \endinternal

****************************************************************************************/

/****************************************************************************************

* Include files

****************************************************************************************/

#include "boot.h"                                /* bootloader generic header          */

#if (BOOT_FILE_LOGGING_ENABLE > 0)

#include "stm32f4xx.h"                           /* STM32 registers                    */

#include "stm32f4xx_conf.h"                      /* STM32 peripheral drivers           */

#endif

/****************************************************************************************

*   B A C K D O O R   E N T R Y   H O O K   F U N C T I O N S

****************************************************************************************/

#if (BOOT_BACKDOOR_HOOKS_ENABLE > 0)

static blt_int32u backdoorOpenTime;

#define BACKDOOR_ENTRY_TIMEOUT_MS 500

static blt_bool timeRanOut = BLT_FALSE;

static blt_int32u osSyncTime;

#define OS_SYNC_MS 1

#define OS_WAIT_MS 1

enum BOOT_STATE {BOOT_FLASH_CHECK,

                 BOOT_FLASH_WAIT,

                 BOOT_OS_SYNC,

                 BOOT_OS_START,

                 BOOT_OS_WAIT

                } boot_state;

#define SYS_PD_N_PIN        GPIO_Pin_13

#define SYS_PD_N_GPIO       GPIOC

#define SYS_SYNC_N_PIN      GPIO_Pin_12

#define SYS_SYNC_N_GPIO     GPIOC

#define BT_RST_PIN          GPIO_Pin_15

#define BT_RST_GPIO         GPIOC

/************************************************************************************//**

** \brief     Initializes the backdoor entry option.

** \return    none.

**

****************************************************************************************/

void BackDoorInitHook(void)

{

  backdoorOpenTime = TimerGet();

  boot_state = BOOT_FLASH_CHECK;

} /*** end of BackDoorInitHook ***/

/************************************************************************************//**

** \brief     Checks if it has to stay in backdoor.

** \return    BLT_TRUE if the backdoor entry is requested, BLT_FALSE otherwise.

**

****************************************************************************************/

blt_bool BackDoorEntryCheck(void) {

  /* evaluate the fsm state */

  switch (boot_state) {

    case BOOT_FLASH_CHECK:

    {

      /* wait for a timeout */

      if (timeRanOut == BLT_FALSE) {

        if (TimerGet() > backdoorOpenTime+BACKDOOR_ENTRY_TIMEOUT_MS) {

          timeRanOut = BLT_TRUE;

          boot_state = BOOT_FLASH_WAIT;

          GPIO_SetBits(SYS_SYNC_N_GPIO, SYS_SYNC_N_PIN);

        }

      }

      return BLT_TRUE;

      break;

    }

    case BOOT_FLASH_WAIT:

    {

      /* wait for the SYS_SYNC_N signal to go up */

      if (GPIO_ReadInputDataBit(SYS_SYNC_N_GPIO, SYS_SYNC_N_PIN) == Bit_RESET) {

        return BLT_TRUE;

      } else {

        osSyncTime = TimerGet();

        boot_state = BOOT_OS_SYNC;

        return BLT_FALSE;

      }

      break;

    }

    default:

      return BLT_FALSE;

      break;

  }

  return BLT_FALSE;

}

/************************************************************************************//**

** \brief     Checks if a backdoor entry is requested.

** \return    BLT_TRUE if the backdoor entry is requested, BLT_FALSE otherwise.

**

****************************************************************************************/

blt_bool BackDoorEntryHook(void)

{

  /* default implementation always activates the bootloader after a reset */

  return BLT_TRUE;

} /*** end of BackDoorEntryHook ***/

#endif /* BOOT_BACKDOOR_HOOKS_ENABLE > 0 */

/************************************************************************************//**

** \brief     Notice that there is still an open connection over COM 

** \return    -

**

****************************************************************************************/

void BackDoorComIsConnected(void)

{

  backdoorOpenTime = TimerGet();

}

/****************************************************************************************

*   C P U   D R I V E R   H O O K   F U N C T I O N S

****************************************************************************************/

#if (BOOT_CPU_USER_PROGRAM_START_HOOK > 0)

#if (BOOT_COM_BLUETOOTH_UART_CHANNEL_INDEX == 0)

/** \brief Set BLUETOOTH UART base address to USART1. */

#define BLUETOOTH_USART_CHANNEL   USART1

#elif (BOOT_COM_BLUETOOTH_UART_CHANNEL_INDEX == 1)

/** \brief Set BLUETOOTH UART base address to USART2. */

#define BLUETOOTH_USART_CHANNEL   USART2

#elif (BOOT_COM_BLUETOOTH_UART_CHANNEL_INDEX == 2)

/** \brief Set BLUETOOTH UART base address to USART3. */

#define BLUETOOTH_USART_CHANNEL   USART3

#elif (BOOT_COM_BLUETOOTH_UART_CHANNEL_INDEX == 3)

/** \brief Set BLUETOOTH UART base address to USART4. */

#define BLUETOOTH_USART_CHANNEL   USART4

#elif (BOOT_COM_BLUETOOTH_UART_CHANNEL_INDEX == 4)

/** \brief Set BLUETOOTH UART base address to USART5. */

#define BLUETOOTH_USART_CHANNEL   USART5

#elif (BOOT_COM_BLUETOOTH_UART_CHANNEL_INDEX == 5)

/** \brief Set BLUETOOTH UART base address to USART6. */

#define BLUETOOTH_USART_CHANNEL   USART6

#endif

/************************************************************************************//**

** \brief     Callback that gets called when the bootloader is about to exit and

**            hand over control to the user program. This is the last moment that

**            some final checking can be performed and if necessary prevent the

**            bootloader from activiting the user program.

** \return    BLT_TRUE if it is okay to start the user program, BLT_FALSE to keep

**            keep the bootloader active.

**

****************************************************************************************/

blt_bool CpuUserProgramStartHook(void)

{

  /* evaluate the fsm state */

  switch (boot_state) {

    case BOOT_OS_SYNC:

    {

      /* wait some time so all modules can detect the high SYS_SYNC_N signal */

      GPIO_SetBits(BT_RST_GPIO, BT_RST_PIN);

      USART_Cmd(BLUETOOTH_USART_CHANNEL, DISABLE);

      USART_DeInit(BLUETOOTH_USART_CHANNEL);

      if (TimerGet() > osSyncTime + OS_SYNC_MS) {

        boot_state = BOOT_OS_START;

      }

      return BLT_FALSE;

      break;

    }

    case BOOT_OS_START:

    {

      /* pull down SYS_SYNC_N to indicate that all modules shall exit the bootloader and start the OS */

      GPIO_ResetBits(SYS_SYNC_N_GPIO, SYS_SYNC_N_PIN);

      osSyncTime = TimerGet();

      boot_state = BOOT_OS_WAIT;

      return BLT_FALSE;

      break;

    }

    case BOOT_OS_WAIT:

    {

      /* wait some time so all module can detect the low SYS_SYNC_N signal */

      if (TimerGet() > osSyncTime + OS_WAIT_MS) {

        return BLT_TRUE;

      } else {

        return BLT_FALSE;

      }

    }

    default:

      return BLT_FALSE;

      break;

  }

  /* okay to start the user program */

  return BLT_TRUE;

} /*** end of CpuUserProgramStartHook ***/

#endif /* BOOT_CPU_USER_PROGRAM_START_HOOK > 0 */

/****************************************************************************************

*   N O N - V O L A T I L E   M E M O R Y   D R I V E R   H O O K   F U N C T I O N S

****************************************************************************************/

#if (BOOT_NVM_HOOKS_ENABLE > 0)

/************************************************************************************//**

** \brief     Callback that gets called at the start of the internal NVM driver

**            initialization routine. 

** \return    none.

**

****************************************************************************************/

void NvmInitHook(void)

{

} /*** end of NvmInitHook ***/

/************************************************************************************//**

** \brief     Callback that gets called at the start of the NVM driver write 

**            routine. It allows additional memory to be operated on. If the address

**            is not within the range of the additional memory, then 

**            BLT_NVM_NOT_IN_RANGE must be returned to indicate that the data hasn't

**            been written yet.

** \param     addr Start address.

** \param     len  Length in bytes.

** \param     data Pointer to the data buffer.

** \return    BLT_NVM_OKAY if successful, BLT_NVM_NOT_IN_RANGE if the address is

**            not within the supported memory range, or BLT_NVM_ERROR is the write

**            operation failed.

**

****************************************************************************************/

blt_int8u NvmWriteHook(blt_addr addr, blt_int32u len, blt_int8u *data)

{

  return BLT_NVM_NOT_IN_RANGE;

} /*** end of NvmWriteHook ***/

/************************************************************************************//**

** \brief     Callback that gets called at the start of the NVM driver erase 

**            routine. It allows additional memory to be operated on. If the address

**            is not within the range of the additional memory, then

**            BLT_NVM_NOT_IN_RANGE must be returned to indicate that the memory

**            hasn't been erased yet.

** \param     addr Start address.

** \param     len  Length in bytes.

** \return    BLT_NVM_OKAY if successful, BLT_NVM_NOT_IN_RANGE if the address is

**            not within the supported memory range, or BLT_NVM_ERROR is the erase

**            operation failed.

**

****************************************************************************************/

blt_int8u NvmEraseHook(blt_addr addr, blt_int32u len)

{

  return BLT_NVM_NOT_IN_RANGE;

} /*** end of NvmEraseHook ***/

/************************************************************************************//**

** \brief     Callback that gets called at the end of the NVM programming session.

** \return    BLT_TRUE is successful, BLT_FALSE otherwise.

**

****************************************************************************************/

blt_bool NvmDoneHook(void)

{

  return BLT_TRUE;

} /*** end of NvmDoneHook ***/

#endif /* BOOT_NVM_HOOKS_ENABLE > 0 */

#if (BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0)

/************************************************************************************//**

** \brief     Verifies the checksum, which indicates that a valid user program is

**            present and can be started.

** \return    BLT_TRUE if successful, BLT_FALSE otherwise.

**

****************************************************************************************/

blt_bool NvmVerifyChecksumHook(void)

{

  return BLT_TRUE;

} /*** end of NvmVerifyChecksum ***/

/************************************************************************************//**

** \brief     Writes a checksum of the user program to non-volatile memory. This is

**            performed once the entire user program has been programmed. Through

**            the checksum, the bootloader can check if a valid user programming is

**            present and can be started.

** \return    BLT_TRUE if successful, BLT_FALSE otherwise. 

**

****************************************************************************************/

blt_bool NvmWriteChecksumHook(void)

{

  return BLT_TRUE;

}

#endif /* BOOT_NVM_CHECKSUM_HOOKS_ENABLE > 0 */

/****************************************************************************************

*   W A T C H D O G   D R I V E R   H O O K   F U N C T I O N S

****************************************************************************************/

#if (BOOT_COP_HOOKS_ENABLE > 0)

/************************************************************************************//**

** \brief     Callback that gets called at the end of the internal COP driver

**            initialization routine. It can be used to configure and enable the

**            watchdog.

** \return    none.

**

****************************************************************************************/

void CopInitHook(void)

{

} /*** end of CopInitHook ***/

/************************************************************************************//**

** \brief     Callback that gets called at the end of the internal COP driver

**            service routine. This gets called upon initialization and during

**            potential long lasting loops and routine. It can be used to service

**            the watchdog to prevent a watchdog reset.

** \return    none.

**

****************************************************************************************/

void CopServiceHook(void)

{

} /*** end of CopServiceHook ***/

#endif /* BOOT_COP_HOOKS_ENABLE > 0 */

/****************************************************************************************

*   F I L E   S Y S T E M   I N T E R F A C E   H O O K   F U N C T I O N S

****************************************************************************************/

#if (BOOT_FILE_SYS_ENABLE > 0)

/****************************************************************************************

* Constant data declarations

****************************************************************************************/

/** \brief Firmware filename. */

static const blt_char firmwareFilename[] = "/demoprog_olimex_stm32p103.srec";

/****************************************************************************************

* Local data declarations

****************************************************************************************/

#if (BOOT_FILE_LOGGING_ENABLE > 0)

/** \brief Data structure for grouping log-file related information. */

static struct 

{

  FIL      handle;                  /**< FatFS handle to the log-file.                 */

  blt_bool canUse;                  /**< Flag to indicate if the log-file can be used. */

} logfile;

#endif

/************************************************************************************//**

** \brief     Callback that gets called to check whether a firmware update from 

**            local file storage should be started. This could for example be when

**            a switch is pressed, when a certain file is found on the local file 

**            storage, etc.

** \return    BLT_TRUE if a firmware update is requested, BLT_FALSE otherwise.

**

****************************************************************************************/

blt_bool FileIsFirmwareUpdateRequestedHook(void)

{

  FILINFO fileInfoObject = { 0 }; /* needs to be zeroed according to f_stat docs */;

  /* Current example implementation looks for a predetermined firmware file on the 

   * SD-card. If the SD-card is accessible and the firmware file was found the firmware

   * update is started. When successfully completed, the firmware file is deleted.

   * During the firmware update, progress information is written to a file called

   * bootlog.txt and additionally outputted on UART @57600 bps for debugging purposes.

   */

  /* check if firmware file is present and SD-card is accessible */

  if (f_stat(firmwareFilename, &fileInfoObject) == FR_OK) 

  {

    /* check if the filesize is valid and that it is not a directory */

    if ( (fileInfoObject.fsize > 0) && (!(fileInfoObject.fattrib & AM_DIR)) )

    {

      /* all conditions are met to start a firmware update from local file storage */

      return BLT_TRUE;

    }

  }

  /* still here so no firmware update request is pending */  

  return BLT_FALSE;

} /*** end of FileIsFirmwareUpdateRequestedHook ***/

/************************************************************************************//**

** \brief     Callback to obtain the filename of the firmware file that should be

**            used during the firmware update from the local file storage. This 

**            hook function is called at the beginning of the firmware update from

**            local storage sequence. 

** \return    valid firmware filename with full path or BLT_NULL.

**

****************************************************************************************/

const blt_char *FileGetFirmwareFilenameHook(void)

{

  return firmwareFilename;

} /*** end of FileGetFirmwareFilenameHook ***/

#if (BOOT_FILE_STARTED_HOOK_ENABLE > 0)

/************************************************************************************//**

** \brief     Callback that gets called to inform the application that a firmware

**            update from local storage just started. 

** \return    none.

**

****************************************************************************************/

void FileFirmwareUpdateStartedHook(void)

{

  #if (BOOT_FILE_LOGGING_ENABLE > 0)

  /* create/overwrite the logfile */

  logfile.canUse = BLT_FALSE;

  if (f_open(&logfile.handle, "/bootlog.txt", FA_CREATE_ALWAYS | FA_WRITE) == FR_OK)

  {

    logfile.canUse = BLT_TRUE;

  }

  #endif

} /*** end of FileFirmwareUpdateStartedHook ***/

#endif /* BOOT_FILE_STARTED_HOOK_ENABLE > 0 */

#if (BOOT_FILE_COMPLETED_HOOK_ENABLE > 0)

/************************************************************************************//**

** \brief     Callback that gets called to inform the application that a firmware

**            update was successfully completed.

** \return    none.

**

****************************************************************************************/

void FileFirmwareUpdateCompletedHook(void)

{

  #if (BOOT_FILE_LOGGING_ENABLE > 0)

  /* close the log file */

  if (logfile.canUse == BLT_TRUE)

  {

    f_close(&logfile.handle);

  }

  /* wait for all logging related transmission to complete */

  while(USART_GetFlagStatus(USART2, USART_FLAG_TC) == RESET);

  #endif

  /* now delete the firmware file from the disk since the update was successful */

  f_unlink(firmwareFilename);

} /*** end of FileFirmwareUpdateCompletedHook ***/

#endif /* BOOT_FILE_COMPLETED_HOOK_ENABLE > 0 */

#if (BOOT_FILE_ERROR_HOOK_ENABLE > 0)

/************************************************************************************//**

** \brief     Callback that gets called in case an error occurred during a firmware

**            update. Refer to <file.h> for a list of available error codes.

** \return    none.

**

****************************************************************************************/

void FileFirmwareUpdateErrorHook(blt_int8u error_code)

{

  #if (BOOT_FILE_LOGGING_ENABLE > 0)

  /* error detected which stops the firmware update, so close the log file */

  if (logfile.canUse == BLT_TRUE)

  {

    f_close(&logfile.handle);

  }

  #endif

} /*** end of FileFirmwareUpdateErrorHook ***/

#endif /* BOOT_FILE_ERROR_HOOK_ENABLE > 0 */

#if (BOOT_FILE_LOGGING_ENABLE > 0)

/************************************************************************************//**

** \brief     Callback that gets called each time new log information becomes 

**            available during a firmware update.

** \param     info_string Pointer to a character array with the log entry info.

** \return    none.

**

****************************************************************************************/

void FileFirmwareUpdateLogHook(blt_char *info_string)

{

  /* write the string to the log file */

  if (logfile.canUse == BLT_TRUE)

  {

    if (f_puts(info_string, &logfile.handle) < 0)

    {

      logfile.canUse = BLT_FALSE;

      f_close(&logfile.handle);

    }

  }

  /* echo all characters in the string on UART */

  while(*info_string != '\0')

  {

    /* write character to transmit holding register */

    USART_SendData(USART2, *info_string);

    /* wait for tx holding register to be empty */

    while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET);

    /* point to the next character in the string */

    info_string++;

  }

} /*** end of FileFirmwareUpdateLogHook ***/

#endif /* BOOT_FILE_LOGGING_ENABLE > 0 */

#endif /* BOOT_FILE_SYS_ENABLE > 0 */

/****************************************************************************************

*   S E E D / K E Y   S E C U R I T Y   H O O K   F U N C T I O N S

****************************************************************************************/

#if (BOOT_XCP_SEED_KEY_ENABLE > 0)

/************************************************************************************//**

** \brief     Provides a seed to the XCP master that will be used for the key 

**            generation when the master attempts to unlock the specified resource. 

**            Called by the GET_SEED command.

** \param     resource  Resource that the seed if requested for (XCP_RES_XXX).

** \param     seed      Pointer to byte buffer wher the seed will be stored.

** \return    Length of the seed in bytes.

**

****************************************************************************************/

blt_int8u XcpGetSeedHook(blt_int8u resource, blt_int8u *seed)

{

  /* request seed for unlocking ProGraMming resource */

  if ((resource & XCP_RES_PGM) != 0)

  {

    seed[0] = 0x55;

  }

  /* return seed length */

  return 1;

} /*** end of XcpGetSeedHook ***/

/************************************************************************************//**

** \brief     Called by the UNLOCK command and checks if the key to unlock the 

**            specified resource was correct. If so, then the resource protection 

**            will be removed.

** \param     resource  resource to unlock (XCP_RES_XXX).

** \param     key       pointer to the byte buffer holding the key.

** \param     len       length of the key in bytes.

** \return    1 if the key was correct, 0 otherwise.

**

****************************************************************************************/

blt_int8u XcpVerifyKeyHook(blt_int8u resource, blt_int8u *key, blt_int8u len)

{

  /* suppress compiler warning for unused parameter */

  len = len;

  /* the example key algorithm in "FeaserKey.dll" works as follows:

   *  - PGM will be unlocked if key = seed - 1

   */

  /* check key for unlocking ProGraMming resource */

  if ((resource == XCP_RES_PGM) && (key[0] == (0x55-1)))

  {

    /* correct key received for unlocking PGM resource */

    return 1;

  }

  /* still here so key incorrect */

  return 0;

} /*** end of XcpVerifyKeyHook ***/

#endif /* BOOT_XCP_SEED_KEY_ENABLE > 0 */

/*********************************** end of hooks.c ************************************/

#ifndef IODEF_H

#define IODEF_H

#include "stm32f4xx.h"

#include "stm32f4xx_conf.h"

#define WKUP_GPIO               GPIOA

#define WKUP_PIN                GPIO_Pin_0

#define SWITCH_STATUS_N_GPIO    GPIOA

#define SWITCH_STATUS_N_PIN     GPIO_Pin_1

#define SYS_UART_TX_GPIO        GPIOA

#define SYS_UART_TX_PIN         GPIO_Pin_2

#define SYS_UART_RX_GPIO        GPIOA

#define SYS_UART_RX_PIN         GPIO_Pin_3

#define SYS_SPI_SS0_N_GPIO      GPIOA

#define SYS_SPI_SS0_N_PIN       GPIO_Pin_4

#define SYS_SPI_SCLK_GPIO       GPIOA

#define SYS_SPI_SCLK_PIN        GPIO_Pin_5

#define SYS_SPI_MISO_GPIO       GPIOA

#define SYS_SPI_MISO_PIN        GPIO_Pin_6

#define SYS_SPI_MOSI_GPIO       GPIOA

#define SYS_SPI_MOSI_PIN        GPIO_Pin_7

#define SYS_REG_EN_GPIO         GPIOA

#define SYS_REG_EN_PIN          GPIO_Pin_8

#define PROG_RX_GPIO            GPIOA

#define PROG_RX_PIN             GPIO_Pin_9

#define PROG_TX_GPIO            GPIOA

#define PROG_TX_PIN             GPIO_Pin_10

#define CAN_RX_GPIO             GPIOA

#define CAN_RX_PIN              GPIO_Pin_11

#define CAN_TX_GPIO             GPIOA

#define CAN_TX_PIN              GPIO_Pin_12

#define SWDIO_GPIO              GPIOA

#define SWDIO_PIN               GPIO_Pin_13

#define SWCLK_GPIO              GPIOA

#define SWCLK_PIN               GPIO_Pin_14

#define SYS_SPI_SS1_N_GPIO      GPIOA

#define SYS_SPI_SS1_N_PIN       GPIO_Pin_15

#define IR_INT1_N_GPIO          GPIOB

#define IR_INT1_N_PIN           GPIO_Pin_0

#define VSYS_SENSE_GPIO         GPIOB

#define VSYS_SENSE_PIN          GPIO_Pin_1

#define POWER_EN_GPIO           GPIOB

#define POWER_EN_PIN            GPIO_Pin_2

#define SYS_UART_DN_GPIO        GPIOB

#define SYS_UART_DN_PIN         GPIO_Pin_3

#define CHARGE_STAT2A_GPIO      GPIOB

#define CHARGE_STAT2A_PIN       GPIO_Pin_4

#define BUZZER_GPIO             GPIOB

#define BUZZER_PIN              GPIO_Pin_5

#define GAUGE_BATLOW2_GPIO      GPIOB

#define GAUGE_BATLOW2_PIN       GPIO_Pin_6

#define GAUGE_BATGD2_N_GPIO     GPIOB

#define GAUGE_BATGD2_N_PIN      GPIO_Pin_7

#define GAUGE_SCL2_GPIO         GPIOB

#define GAUGE_SCL2_PIN          GPIO_Pin_8

#define GAUGE_SDA2_GPIO         GPIOB

#define GAUGE_SDA2_PIN          GPIO_Pin_9

#define GAUGE_SCL1_GPIO         GPIOB

#define GAUGE_SCL1_PIN          GPIO_Pin_10

#define GAUGE_SDA1_GPIO         GPIOB

#define GAUGE_SDA1_PIN          GPIO_Pin_11

#define LED_GPIO                GPIOB

#define LED_PIN                 GPIO_Pin_12

#define BT_RTS_GPIO             GPIOB

#define BT_RTS_PIN              GPIO_Pin_13

#define BT_CTS_GPIO             GPIOB

#define BT_CTS_PIN              GPIO_Pin_14

#define SYS_UART_UP_GPIO        GPIOB

#define SYS_UART_UP_PIN         GPIO_Pin_15

#define CHARGE_STAT1A_GPIO      GPIOC

#define CHARGE_STAT1A_PIN       GPIO_Pin_0

#define GAUGE_BATLOW1_GPIO      GPIOC

#define GAUGE_BATLOW1_PIN       GPIO_Pin_1

#define GAUGE_BATGD1_N_GPIO     GPIOC

#define GAUGE_BATGD1_N_PIN      GPIO_Pin_2

#define CHARGE_EN1_N_GPIO       GPIOC

#define CHARGE_EN1_N_PIN        GPIO_Pin_3

#define IR_INT2_N_GPIO          GPIOC

#define IR_INT2_N_PIN           GPIO_Pin_4

#define TOUCH_INT_N_GPIO        GPIOC

#define TOUCH_INT_N_PIN         GPIO_Pin_5

#define SYS_DONE_GPIO           GPIOC

#define SYS_DONE_PIN            GPIO_Pin_6

#define SYS_PROG_N_GPIO         GPIOC

#define SYS_PROG_N_PIN          GPIO_Pin_7

#define PATH_DC_GPIO            GPIOC

#define PATH_DC_PIN             GPIO_Pin_8

#define SYS_SPI_DIR_GPIO        GPIOC

#define SYS_SPI_DIR_PIN         GPIO_Pin_9

#define BT_RX_GPIO              GPIOC

#define BT_RX_PIN               GPIO_Pin_10

#define BT_TX_GPIO              GPIOC

#define BT_TX_PIN               GPIO_Pin_11

#define SYS_SYNC_N_GPIO         GPIOC

#define SYS_SYNC_N_PIN          GPIO_Pin_12

#define SYS_PD_N_GPIO           GPIOC

#define SYS_PD_N_PIN            GPIO_Pin_13

#define SYS_WARMRST_N_GPIO      GPIOC

#define SYS_WARMRST_N_PIN       GPIO_Pin_14

#define BT_RST_GPIO             GPIOC

#define BT_RST_PIN              GPIO_Pin_15

#define OSC_IN_GPIO             GPIOD

#define OSC_IN_PIN              GPIO_Pin_0

#define OSC_OUT_GPIO            GPIOD

#define OSC_OUT_PIN             GPIO_Pin_1

#define CHARGE_EN2_N_GPIO       GPIOD

#define CHARGE_EN2_N_PIN        GPIO_Pin_2

#endif /* IODEF_H */

/**

  ******************************************************************************

  * @file    stm32_eth.h

  * @author  MCD Application Team

  * @version V1.0.0

  * @date    06/19/2009

  * @brief   This file contains all the functions prototypes for the Ethernet

  *          firmware library.

  ******************************************************************************

  * @copy

  *

  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS

  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE

  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY

  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING

  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE

  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

  *

  * <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>

  */ 

/* Define to prevent recursive inclusion -------------------------------------*/

#ifndef __STM32_ETH_H

#define __STM32_ETH_H

#ifdef __cplusplus

 extern "C" {

#endif

/* Includes ------------------------------------------------------------------*/

#include "stm32f4xx.h"                               /* STM32 registers                */

/** @addtogroup STM32_ETH_Driver

  * @{

  */

/** @defgroup ETH_Exported_Types

  * @{

  */

/** 

  * @brief  ETH MAC Init structure definition

  */ 

typedef struct {

/** 

  * @brief / * MAC  

  */ 

  uint32_t             ETH_AutoNegotiation;           /*!< Selects or not the AutoNegotiation with the external PHY */  

  uint32_t             ETH_Watchdog;                  /*!< Enable/disable Watchdog timer */  

  uint32_t             ETH_Jabber;                    /*!< Enable/disable Jabber timer */ 

  uint32_t             ETH_InterFrameGap;             /*!< Selects minimum IFG between frames during transmission */   

  uint32_t             ETH_CarrierSense;              /*!< Enable/disable Carrier Sense */ 

  uint32_t             ETH_Speed;                     /*!< Indicates the Ethernet speed: 10/100 Mbps */  

  uint32_t             ETH_ReceiveOwn;                /*!< Enable/disable the reception of frames when the TX_EN signal is asserted in Half-Duplex mode */  

  uint32_t             ETH_LoopbackMode;              /*!< Enable/disable internal MAC MII Loopback mode */ 

  uint32_t             ETH_Mode;                      /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode */ 

  uint32_t             ETH_ChecksumOffload;           /*!< Enable/disable the calculation of complement sum of all received Ethernet frame payloads */   

  uint32_t             ETH_RetryTransmission;         /*!< Enable/disable the MAC attempt retries transmission, based on the settings of BL, when a colision occurs (Half-Duplex mode) */

  uint32_t             ETH_AutomaticPadCRCStrip;      /*!< Enable/disable Automatic MAC Pad/CRC Stripping */ 

  uint32_t             ETH_BackOffLimit;              /*!< Selects the BackOff limit value */ 

  uint32_t             ETH_DeferralCheck;             /*!< Enable/disable deferral check function (Half-Duplex mode) */                                                                                                       

  uint32_t             ETH_ReceiveAll;                /*!< Enable/disable all frames reception by the MAC (No fitering)*/ 

  uint32_t             ETH_SourceAddrFilter;          /*!< Selects EnableNormal/EnableInverse/disable Source Address Filter comparison */                  

  uint32_t             ETH_PassControlFrames;         /*!< Selects None/All/FilterPass of all control frames (including unicast and multicast PAUSE frames) */ 

  uint32_t             ETH_BroadcastFramesReception;  /*!< Enable/disable reception of Broadcast Frames */

  uint32_t             ETH_DestinationAddrFilter;     /*!< Selects EnableNormal/EnableInverse destination filter for both unicast and multicast frames */ 

  uint32_t             ETH_PromiscuousMode;           /*!< Enable/disable Promiscuous Mode */

  uint32_t             ETH_MulticastFramesFilter;     /*!< Selects the Multicast Frames filter: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter */ 

  uint32_t             ETH_UnicastFramesFilter;       /*!< Selects the Unicast Frames filter: HashTableFilter/PerfectFilter/PerfectHashTableFilter  */

  uint32_t             ETH_HashTableHigh;             /*!< This field contains the higher 32 bits of Hash table.  */    

  uint32_t             ETH_HashTableLow;              /*!< This field contains the lower 32 bits of Hash table.  */    

  uint32_t             ETH_PauseTime;                 /*!< This field holds the value to be used in the Pause Time field in the transmit control frame */

  uint32_t             ETH_ZeroQuantaPause;           /*!< Enable/disable the automatic generation of Zero-Quanta Pause Control frames */ 

  uint32_t             ETH_PauseLowThreshold;         /*!< This field configures the threshold of the PAUSE to be checked for automatic retransmission of PAUSE Frame */

  uint32_t             ETH_UnicastPauseFrameDetect;   /*!< Enable/disable MAC to detect the Pause frames (with MAC Address0 unicast address and unique multicast address) */ 

  uint32_t             ETH_ReceiveFlowControl;        /*!< Enable/disable the MAC to decode the received Pause frame and disable its transmitter for a specified (Pause Time) time */

  uint32_t             ETH_TransmitFlowControl;       /*!< Enable/disable the MAC to transmit Pause frames (Full-Duplex mode) or the MAC back-pressure operation (Half-Duplex mode) */     

  uint32_t             ETH_VLANTagComparison;         /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for comparison and filtering */ 

  uint32_t             ETH_VLANTagIdentifier;         /*!< VLAN tag identifier for receive frames */

/** 

  * @brief / * DMA  

  */ 

  uint32_t             ETH_DropTCPIPChecksumErrorFrame; /*!< Enable/disable Dropping of TCP/IP Checksum Error Frames */

  uint32_t             ETH_ReceiveStoreForward;         /*!< Enable/disable Receive store and forward */

  uint32_t             ETH_FlushReceivedFrame;          /*!< Enable/disable flushing of received frames */

  uint32_t             ETH_TransmitStoreForward;        /*!< Enable/disable Transmit store and forward */

  uint32_t             ETH_TransmitThresholdControl;    /*!< Selects the Transmit Threshold Control */

  uint32_t             ETH_ForwardErrorFrames;          /*!< Enable/disable forward to DMA of all frames except runt error frames */

  uint32_t             ETH_ForwardUndersizedGoodFrames; /*!< Enable/disable Rx FIFO to forward Undersized frames (frames with no Error and length less than 64 bytes) including pad-bytes and CRC) */

  uint32_t             ETH_ReceiveThresholdControl;     /*!< Selects the threshold level of the Receive FIFO */

  uint32_t             ETH_SecondFrameOperate;          /*!< Enable/disable the DMA process of a second frame of Transmit data even before status for first frame is obtained */

  uint32_t             ETH_AddressAlignedBeats;         /*!< Enable/disable Address Aligned Beats */

  uint32_t             ETH_FixedBurst;                  /*!< Enable/disable the AHB Master interface fixed burst transfers */

  uint32_t             ETH_RxDMABurstLength;            /*!< Indicate the maximum number of beats to be transferred in one Rx DMA transaction */

  uint32_t             ETH_TxDMABurstLength;            /*!< Indicate the maximum number of beats to be transferred in one Tx DMA transaction */                                                 

  uint32_t             ETH_DescriptorSkipLength;        /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode) */

  uint32_t             ETH_DMAArbitration;              /*!< Selects DMA Tx/Rx arbitration */  

}ETH_InitTypeDef;

/**--------------------------------------------------------------------------**/

/** 

  * @brief                           DMA descriptors types

  */ 

/**--------------------------------------------------------------------------**/

/** 

  * @brief  ETH DMA Desciptors data structure definition

  */ 

typedef struct  {

  uint32_t   Status;                /*!< Status */

  uint32_t   ControlBufferSize;     /*!< Control and Buffer1, Buffer2 lengths */

  uint32_t   Buffer1Addr;           /*!< Buffer1 address pointer */

  uint32_t   Buffer2NextDescAddr;   /*!< Buffer2 or next descriptor address pointer */

} ETH_DMADESCTypeDef;

/**

  * @}

  */

/** @defgroup ETH_Exported_Constants

  * @{

  */ 

/**--------------------------------------------------------------------------**/

/** 

  * @brief                          ETH Frames defines

  */ 

/**--------------------------------------------------------------------------**/

/** @defgroup ENET_Buffers_setting 

  * @{

  */ 

#define ETH_MAX_PACKET_SIZE    1520    /*!< ETH_HEADER + ETH_EXTRA + MAX_ETH_PAYLOAD + ETH_CRC */

#define ETH_HEADER               14    /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */

#define ETH_CRC                   4    /*!< Ethernet CRC */

#define ETH_EXTRA                 2    /*!< Extra bytes in some cases */   

#define VLAN_TAG                  4    /*!< optional 802.1q VLAN Tag */

#define MIN_ETH_PAYLOAD          46    /*!< Minimum Ethernet payload size */

#define MAX_ETH_PAYLOAD        1500    /*!< Maximum Ethernet payload size */

#define JUMBO_FRAME_PAYLOAD    9000    /*!< Jumbo frame payload size */      

/**--------------------------------------------------------------------------**/

/** 

  * @brief                 Ethernet DMA descriptors registers bits definition

  */ 

/**--------------------------------------------------------------------------**/

/* DMA Tx Desciptor -----------------------------------------------------------*/

/**----------------------------------------------------------------------------------------------

  TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |

  -----------------------------------------------------------------------------------------------

  TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |

  -----------------------------------------------------------------------------------------------

  TDES2 |                         Buffer1 Address [31:0]                                         |

  -----------------------------------------------------------------------------------------------

  TDES3 |                   Buffer2 Address [31:0] / Next Desciptor Address [31:0]               |

  ---------------------------------------------------------------------------------------------**/

/** 

  * @brief  Bit definition of TDES0 register: DMA Tx descriptor status register

  */ 

#define ETH_DMATxDesc_OWN                     ((uint32_t)0x80000000)  /*!< OWN bit: descriptor is owned by DMA engine */

#define ETH_DMATxDesc_IC                      ((uint32_t)0x40000000)  /*!< Interrupt on Completion */

#define ETH_DMATxDesc_LS                      ((uint32_t)0x20000000)  /*!< Last Segment */

#define ETH_DMATxDesc_FS                      ((uint32_t)0x10000000)  /*!< First Segment */

#define ETH_DMATxDesc_DC                      ((uint32_t)0x08000000)  /*!< Disable CRC */

#define ETH_DMATxDesc_DP                      ((uint32_t)0x04000000)  /*!< Disable Padding */

#define ETH_DMATxDesc_TTSE                    ((uint32_t)0x02000000)  /*!< Transmit Time Stamp Enable */

#define ETH_DMATxDesc_CIC                     ((uint32_t)0x00C00000)  /*!< Checksum Insertion Control: 4 cases */

#define ETH_DMATxDesc_CIC_ByPass              ((uint32_t)0x00000000)  /*!< Do Nothing: Checksum Engine is bypassed */ 

#define ETH_DMATxDesc_CIC_IPV4Header          ((uint32_t)0x00400000)  /*!< IPV4 header Checksum Insertion */ 

#define ETH_DMATxDesc_CIC_TCPUDPICMP_Segment  ((uint32_t)0x00800000)  /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ 

#define ETH_DMATxDesc_CIC_TCPUDPICMP_Full     ((uint32_t)0x00C00000)  /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ 

#define ETH_DMATxDesc_TER                     ((uint32_t)0x00200000)  /*!< Transmit End of Ring */

#define ETH_DMATxDesc_TCH                     ((uint32_t)0x00100000)  /*!< Second Address Chained */

#define ETH_DMATxDesc_TTSS                    ((uint32_t)0x00020000)  /*!< Tx Time Stamp Status */

#define ETH_DMATxDesc_IHE                     ((uint32_t)0x00010000)  /*!< IP Header Error */

#define ETH_DMATxDesc_ES                      ((uint32_t)0x00008000)  /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */

#define ETH_DMATxDesc_JT                      ((uint32_t)0x00004000)  /*!< Jabber Timeout */

#define ETH_DMATxDesc_FF                      ((uint32_t)0x00002000)  /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */

#define ETH_DMATxDesc_PCE                     ((uint32_t)0x00001000)  /*!< Payload Checksum Error */

#define ETH_DMATxDesc_LCA                     ((uint32_t)0x00000800)  /*!< Loss of Carrier: carrier lost during tramsmission */

#define ETH_DMATxDesc_NC                      ((uint32_t)0x00000400)  /*!< No Carrier: no carrier signal from the tranceiver */

#define ETH_DMATxDesc_LCO                     ((uint32_t)0x00000200)  /*!< Late Collision: transmission aborted due to collision */

#define ETH_DMATxDesc_EC                      ((uint32_t)0x00000100)  /*!< Excessive Collision: transmission aborted after 16 collisions */

#define ETH_DMATxDesc_VF                      ((uint32_t)0x00000080)  /*!< VLAN Frame */

#define ETH_DMATxDesc_CC                      ((uint32_t)0x00000078)  /*!< Collision Count */

#define ETH_DMATxDesc_ED                      ((uint32_t)0x00000004)  /*!< Excessive Deferral */

#define ETH_DMATxDesc_UF                      ((uint32_t)0x00000002)  /*!< Underflow Error: late data arrival from the memory */

#define ETH_DMATxDesc_DB                      ((uint32_t)0x00000001)  /*!< Deferred Bit */

/** 

  * @brief  Bit definition of TDES1 register

  */ 

#define ETH_DMATxDesc_TBS2  ((uint32_t)0x1FFF0000)  /*!< Transmit Buffer2 Size */

#define ETH_DMATxDesc_TBS1  ((uint32_t)0x00001FFF)  /*!< Transmit Buffer1 Size */

/** 

  * @brief  Bit definition of TDES2 register

  */ 

#define ETH_DMATxDesc_B1AP  ((uint32_t)0xFFFFFFFF)  /*!< Buffer1 Address Pointer */

/** 

  * @brief  Bit definition of TDES3 register

  */ 

#define ETH_DMATxDesc_B2AP  ((uint32_t)0xFFFFFFFF)  /*!< Buffer2 Address Pointer */

/**

  * @}

  */ 

/** @defgroup DMA_Rx_descriptor 

  * @{

  */

/**--------------------------------------------------------------------------------------------------------------------

  RDES0 | OWN(31) |                                             Status [30:0]                                          |

  ---------------------------------------------------------------------------------------------------------------------

  RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |

  ---------------------------------------------------------------------------------------------------------------------

  RDES2 |                                       Buffer1 Address [31:0]                                                 |

  ---------------------------------------------------------------------------------------------------------------------

  RDES3 |                          Buffer2 Address [31:0] / Next Desciptor Address [31:0]                              |

  -------------------------------------------------------------------------------------------------------------------**/

/** 

  * @brief  Bit definition of RDES0 register: DMA Rx descriptor status register

  */ 

#define ETH_DMARxDesc_OWN         ((uint32_t)0x80000000)  /*!< OWN bit: descriptor is owned by DMA engine  */

#define ETH_DMARxDesc_AFM         ((uint32_t)0x40000000)  /*!< DA Filter Fail for the rx frame  */

#define ETH_DMARxDesc_FL          ((uint32_t)0x3FFF0000)  /*!< Receive descriptor frame length  */

#define ETH_DMARxDesc_ES          ((uint32_t)0x00008000)  /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */

#define ETH_DMARxDesc_DE          ((uint32_t)0x00004000)  /*!< Desciptor error: no more descriptors for receive frame  */

#define ETH_DMARxDesc_SAF         ((uint32_t)0x00002000)  /*!< SA Filter Fail for the received frame */

#define ETH_DMARxDesc_LE          ((uint32_t)0x00001000)  /*!< Frame size not matching with length field */

#define ETH_DMARxDesc_OE          ((uint32_t)0x00000800)  /*!< Overflow Error: Frame was damaged due to buffer overflow */

#define ETH_DMARxDesc_VLAN        ((uint32_t)0x00000400)  /*!< VLAN Tag: received frame is a VLAN frame */

#define ETH_DMARxDesc_FS          ((uint32_t)0x00000200)  /*!< First descriptor of the frame  */

#define ETH_DMARxDesc_LS          ((uint32_t)0x00000100)  /*!< Last descriptor of the frame  */ 

#define ETH_DMARxDesc_IPV4HCE     ((uint32_t)0x00000080)  /*!< IPC Checksum Error: Rx Ipv4 header checksum error   */    

#define ETH_DMARxDesc_LC          ((uint32_t)0x00000040)  /*!< Late collision occurred during reception   */

#define ETH_DMARxDesc_FT          ((uint32_t)0x00000020)  /*!< Frame type - Ethernet, otherwise 802.3    */

#define ETH_DMARxDesc_RWT         ((uint32_t)0x00000010)  /*!< Receive Watchdog Timeout: watchdog timer expired during reception    */

#define ETH_DMARxDesc_RE          ((uint32_t)0x00000008)  /*!< Receive error: error reported by MII interface  */

#define ETH_DMARxDesc_DBE         ((uint32_t)0x00000004)  /*!< Dribble bit error: frame contains non int multiple of 8 bits  */

#define ETH_DMARxDesc_CE          ((uint32_t)0x00000002)  /*!< CRC error */

#define ETH_DMARxDesc_MAMPCE      ((uint32_t)0x00000001)  /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */

/** 

  * @brief  Bit definition of RDES1 register

  */ 

#define ETH_DMARxDesc_DIC   ((uint32_t)0x80000000)  /*!< Disable Interrupt on Completion */

#define ETH_DMARxDesc_RBS2  ((uint32_t)0x1FFF0000)  /*!< Receive Buffer2 Size */

#define ETH_DMARxDesc_RER   ((uint32_t)0x00008000)  /*!< Receive End of Ring */

#define ETH_DMARxDesc_RCH   ((uint32_t)0x00004000)  /*!< Second Address Chained */

#define ETH_DMARxDesc_RBS1  ((uint32_t)0x00001FFF)  /*!< Receive Buffer1 Size */

/** 

  * @brief  Bit definition of RDES2 register  

  */ 

#define ETH_DMARxDesc_B1AP  ((uint32_t)0xFFFFFFFF)  /*!< Buffer1 Address Pointer */

/** 

  * @brief  Bit definition of RDES3 register  

  */ 

#define ETH_DMARxDesc_B2AP  ((uint32_t)0xFFFFFFFF)  /*!< Buffer2 Address Pointer */

/**--------------------------------------------------------------------------**/

/** 

  * @brief                     Desciption of common PHY registers

  */ 

/**--------------------------------------------------------------------------**/

/**

  * @}

  */

/** @defgroup PHY_Read_write_Timeouts 

  * @{

  */ 

#define PHY_READ_TO                     ((uint32_t)0x0004FFFF)

#define PHY_WRITE_TO                    ((uint32_t)0x0004FFFF)

/**

  * @}

  */

/** @defgroup PHY_Reset_Delay 

  * @{

  */ 

#define PHY_ResetDelay                  ((uint32_t)0x04000000) 

/**

  * @}

  */

/** @defgroup PHY_Config_Delay 

  * @{

  */ 

#define PHY_ConfigDelay                 ((uint32_t)0x00FFFFFF)

/**

  * @}

  */

/** @defgroup PHY_Register_address 

  * @{

  */ 

#define PHY_BCR                          0          /*!< Tranceiver Basic Control Register */

#define PHY_BSR                          1          /*!< Tranceiver Basic Status Register */

/**

  * @}

  */

/** @defgroup PHY_basic_Control_register 

  * @{

  */ 

#define PHY_Reset                       ((u16)0x8000)      /*!< PHY Reset */

#define PHY_Loopback                    ((u16)0x4000)      /*!< Select loop-back mode */

#define PHY_FULLDUPLEX_100M             ((u16)0x2100)      /*!< Set the full-duplex mode at 100 Mb/s */

#define PHY_HALFDUPLEX_100M             ((u16)0x2000)      /*!< Set the half-duplex mode at 100 Mb/s */

#define PHY_FULLDUPLEX_10M              ((u16)0x0100)      /*!< Set the full-duplex mode at 10 Mb/s */

#define PHY_HALFDUPLEX_10M              ((u16)0x0000)      /*!< Set the half-duplex mode at 10 Mb/s */

#define PHY_AutoNegotiation             ((u16)0x1000)      /*!< Enable auto-negotiation function */

#define PHY_Restart_AutoNegotiation     ((u16)0x0200)      /*!< Restart auto-negotiation function */

#define PHY_Powerdown                   ((u16)0x0800)      /*!< Select the power down mode */

#define PHY_Isolate                     ((u16)0x0400)      /*!< Isolate PHY from MII */

/**

  * @}

  */

/** @defgroup PHY_basic_status_register 

  * @{

  */ 

#define PHY_AutoNego_Complete           ((u16)0x0020)      /*!< Auto-Negotioation process completed */

#define PHY_Linked_Status               ((u16)0x0004)      /*!< Valid link established */

#define PHY_Jabber_detection            ((u16)0x0002)      /*!< Jabber condition detected */

/**

  * @}

  */

/** @defgroup PHY_status_register 

  * @{

  */ 

/* The PHY status register value change from a PHY to another so the user have 

   to update this value depending on the used external PHY */

/** 

  * @brief  For LAN8700  

  */ 

//#define PHY_SR                           31         /*!< Tranceiver Status Register */

/** 

  * @brief  For DP83848  

  */ 

#define PHY_SR                           16     /*!< Tranceiver Status Register */

/* The Speed and Duplex mask values change from a PHY to another so the user have to update

   this value depending on the used external PHY */

/** 

  * @brief  For LAN8700  

  */ 

//#define PHY_Speed_Status            ((u16)0x0004)       /*!< Configured information of Speed: 10Mbps */

//#define PHY_Duplex_Status           ((u16)0x0010)       /*!< Configured information of Duplex: Full-duplex */

/** 

  * @brief  For DP83848  

  */ 

#define PHY_Speed_Status            ((u16)0x0002)    /*!< Configured information of Speed: 10Mbps */

#define PHY_Duplex_Status           ((u16)0x0004)    /*!< Configured information of Duplex: Full-duplex */

#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)

#define IS_ETH_PHY_REG(REG) (((REG) == PHY_BCR) || \

                             ((REG) == PHY_BSR) || \

                             ((REG) == PHY_SR))

/**--------------------------------------------------------------------------**/

/** 

  * @brief                                  MAC defines

  */ 

/**--------------------------------------------------------------------------**/

/**

  * @}

  */ 

/** @defgroup ETH_AutoNegotiation 

  * @{

  */ 

#define ETH_AutoNegotiation_Enable     ((uint32_t)0x00000001)

#define ETH_AutoNegotiation_Disable    ((uint32_t)0x00000000)

#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AutoNegotiation_Enable) || \

                                     ((CMD) == ETH_AutoNegotiation_Disable))

/**

  * @}

  */

/** @defgroup ETH_watchdog 

  * @{

  */ 

#define ETH_Watchdog_Enable       ((uint32_t)0x00000000)

#define ETH_Watchdog_Disable      ((uint32_t)0x00800000)

#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_Watchdog_Enable) || \

                              ((CMD) == ETH_Watchdog_Disable))

/**

  * @}

  */

/** @defgroup ETH_Jabber 

  * @{

  */ 

#define ETH_Jabber_Enable    ((uint32_t)0x00000000)

#define ETH_Jabber_Disable   ((uint32_t)0x00400000)