amiro-blt / Target / Modules / LightRing_1-0 / Boot / lib / STM32F10x_StdPeriph_Driver / inc / stm32f10x_fsmc.h @ f7d2c786
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1 | 69661903 | Thomas Schöpping | /**
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2 | ******************************************************************************
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3 | * @file stm32f10x_fsmc.h
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4 | * @author MCD Application Team
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5 | * @version V3.5.0
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6 | * @date 11-March-2011
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7 | * @brief This file contains all the functions prototypes for the FSMC firmware
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8 | * library.
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9 | ******************************************************************************
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10 | * @attention
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11 | *
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12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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18 | *
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19 | * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
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20 | ******************************************************************************
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21 | */
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22 | |||
23 | /* Define to prevent recursive inclusion -------------------------------------*/
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24 | #ifndef __STM32F10x_FSMC_H
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25 | #define __STM32F10x_FSMC_H
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26 | |||
27 | #ifdef __cplusplus
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28 | extern "C" { |
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29 | #endif
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30 | |||
31 | /* Includes ------------------------------------------------------------------*/
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32 | #include "stm32f10x.h" |
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33 | |||
34 | /** @addtogroup STM32F10x_StdPeriph_Driver
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35 | * @{
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36 | */
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37 | |||
38 | /** @addtogroup FSMC
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39 | * @{
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40 | */
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41 | |||
42 | /** @defgroup FSMC_Exported_Types
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43 | * @{
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44 | */
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45 | |||
46 | /**
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47 | * @brief Timing parameters For NOR/SRAM Banks
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48 | */
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49 | |||
50 | typedef struct |
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51 | { |
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52 | uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
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53 | the duration of the address setup time.
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54 | This parameter can be a value between 0 and 0xF.
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55 | @note: It is not used with synchronous NOR Flash memories. */
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56 | |||
57 | uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
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58 | the duration of the address hold time.
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59 | This parameter can be a value between 0 and 0xF.
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60 | @note: It is not used with synchronous NOR Flash memories.*/
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61 | |||
62 | uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure
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63 | the duration of the data setup time.
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64 | This parameter can be a value between 0 and 0xFF.
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65 | @note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
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66 | |||
67 | uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
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68 | the duration of the bus turnaround.
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69 | This parameter can be a value between 0 and 0xF.
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70 | @note: It is only used for multiplexed NOR Flash memories. */
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71 | |||
72 | uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
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73 | This parameter can be a value between 1 and 0xF.
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74 | @note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
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75 | |||
76 | uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue
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77 | to the memory before getting the first data.
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78 | The value of this parameter depends on the memory type as shown below:
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79 | - It must be set to 0 in case of a CRAM
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80 | - It is don't care in asynchronous NOR, SRAM or ROM accesses
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81 | - It may assume a value between 0 and 0xF in NOR Flash memories
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82 | with synchronous burst mode enable */
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83 | |||
84 | uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode.
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85 | This parameter can be a value of @ref FSMC_Access_Mode */
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86 | }FSMC_NORSRAMTimingInitTypeDef; |
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87 | |||
88 | /**
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89 | * @brief FSMC NOR/SRAM Init structure definition
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90 | */
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91 | |||
92 | typedef struct |
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93 | { |
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94 | uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used.
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95 | This parameter can be a value of @ref FSMC_NORSRAM_Bank */
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96 | |||
97 | uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are
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98 | multiplexed on the databus or not.
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99 | This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
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100 | |||
101 | uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to
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102 | the corresponding memory bank.
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103 | This parameter can be a value of @ref FSMC_Memory_Type */
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104 | |||
105 | uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.
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106 | This parameter can be a value of @ref FSMC_Data_Width */
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107 | |||
108 | uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
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109 | valid only with synchronous burst Flash memories.
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110 | This parameter can be a value of @ref FSMC_Burst_Access_Mode */
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111 | |||
112 | uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
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113 | valid only with asynchronous Flash memories.
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114 | This parameter can be a value of @ref FSMC_AsynchronousWait */
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115 | |||
116 | uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
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117 | the Flash memory in burst mode.
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118 | This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
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119 | |||
120 | uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
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121 | memory, valid only when accessing Flash memories in burst mode.
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122 | This parameter can be a value of @ref FSMC_Wrap_Mode */
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123 | |||
124 | uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
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125 | clock cycle before the wait state or during the wait state,
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126 | valid only when accessing memories in burst mode.
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127 | This parameter can be a value of @ref FSMC_Wait_Timing */
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128 | |||
129 | uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC.
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130 | This parameter can be a value of @ref FSMC_Write_Operation */
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131 | |||
132 | uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait
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133 | signal, valid for Flash memory access in burst mode.
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134 | This parameter can be a value of @ref FSMC_Wait_Signal */
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135 | |||
136 | uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode.
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137 | This parameter can be a value of @ref FSMC_Extended_Mode */
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138 | |||
139 | uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation.
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140 | This parameter can be a value of @ref FSMC_Write_Burst */
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141 | |||
142 | FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/
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143 | |||
144 | FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/
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145 | }FSMC_NORSRAMInitTypeDef; |
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146 | |||
147 | /**
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148 | * @brief Timing parameters For FSMC NAND and PCCARD Banks
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149 | */
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150 | |||
151 | typedef struct |
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152 | { |
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153 | uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before
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154 | the command assertion for NAND-Flash read or write access
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155 | to common/Attribute or I/O memory space (depending on
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156 | the memory space timing to be configured).
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157 | This parameter can be a value between 0 and 0xFF.*/
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158 | |||
159 | uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
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160 | command for NAND-Flash read or write access to
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161 | common/Attribute or I/O memory space (depending on the
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162 | memory space timing to be configured).
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163 | This parameter can be a number between 0x00 and 0xFF */
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164 | |||
165 | uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
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166 | (and data for write access) after the command deassertion
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167 | for NAND-Flash read or write access to common/Attribute
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168 | or I/O memory space (depending on the memory space timing
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169 | to be configured).
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170 | This parameter can be a number between 0x00 and 0xFF */
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171 | |||
172 | uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
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173 | databus is kept in HiZ after the start of a NAND-Flash
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174 | write access to common/Attribute or I/O memory space (depending
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175 | on the memory space timing to be configured).
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176 | This parameter can be a number between 0x00 and 0xFF */
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177 | }FSMC_NAND_PCCARDTimingInitTypeDef; |
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178 | |||
179 | /**
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180 | * @brief FSMC NAND Init structure definition
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181 | */
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182 | |||
183 | typedef struct |
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184 | { |
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185 | uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used.
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186 | This parameter can be a value of @ref FSMC_NAND_Bank */
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187 | |||
188 | uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank.
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189 | This parameter can be any value of @ref FSMC_Wait_feature */
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190 | |||
191 | uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.
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192 | This parameter can be any value of @ref FSMC_Data_Width */
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193 | |||
194 | uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation.
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195 | This parameter can be any value of @ref FSMC_ECC */
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196 | |||
197 | uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC.
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198 | This parameter can be any value of @ref FSMC_ECC_Page_Size */
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199 | |||
200 | uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
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201 | delay between CLE low and RE low.
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202 | This parameter can be a value between 0 and 0xFF. */
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203 | |||
204 | uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
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205 | delay between ALE low and RE low.
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206 | This parameter can be a number between 0x0 and 0xFF */
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207 | |||
208 | FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
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209 | |||
210 | FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
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211 | }FSMC_NANDInitTypeDef; |
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212 | |||
213 | /**
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214 | * @brief FSMC PCCARD Init structure definition
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215 | */
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216 | |||
217 | typedef struct |
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218 | { |
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219 | uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank.
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220 | This parameter can be any value of @ref FSMC_Wait_feature */
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221 | |||
222 | uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
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223 | delay between CLE low and RE low.
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224 | This parameter can be a value between 0 and 0xFF. */
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225 | |||
226 | uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
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227 | delay between ALE low and RE low.
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228 | This parameter can be a number between 0x0 and 0xFF */
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229 | |||
230 | |||
231 | FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
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232 | |||
233 | FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
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234 | |||
235 | FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */
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236 | }FSMC_PCCARDInitTypeDef; |
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237 | |||
238 | /**
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239 | * @}
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240 | */
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241 | |||
242 | /** @defgroup FSMC_Exported_Constants
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243 | * @{
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244 | */
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245 | |||
246 | /** @defgroup FSMC_NORSRAM_Bank
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247 | * @{
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248 | */
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249 | #define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000) |
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250 | #define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002) |
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251 | #define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004) |
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252 | #define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006) |
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253 | /**
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254 | * @}
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255 | */
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256 | |||
257 | /** @defgroup FSMC_NAND_Bank
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258 | * @{
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259 | */
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260 | #define FSMC_Bank2_NAND ((uint32_t)0x00000010) |
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261 | #define FSMC_Bank3_NAND ((uint32_t)0x00000100) |
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262 | /**
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263 | * @}
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264 | */
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265 | |||
266 | /** @defgroup FSMC_PCCARD_Bank
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267 | * @{
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268 | */
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269 | #define FSMC_Bank4_PCCARD ((uint32_t)0x00001000) |
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270 | /**
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271 | * @}
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272 | */
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273 | |||
274 | #define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \
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275 | ((BANK) == FSMC_Bank1_NORSRAM2) || \ |
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276 | ((BANK) == FSMC_Bank1_NORSRAM3) || \ |
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277 | ((BANK) == FSMC_Bank1_NORSRAM4)) |
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278 | |||
279 | #define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
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280 | ((BANK) == FSMC_Bank3_NAND)) |
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281 | |||
282 | #define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
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283 | ((BANK) == FSMC_Bank3_NAND) || \ |
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284 | ((BANK) == FSMC_Bank4_PCCARD)) |
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285 | |||
286 | #define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
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287 | ((BANK) == FSMC_Bank3_NAND) || \ |
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288 | ((BANK) == FSMC_Bank4_PCCARD)) |
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289 | |||
290 | /** @defgroup NOR_SRAM_Controller
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291 | * @{
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292 | */
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293 | |||
294 | /** @defgroup FSMC_Data_Address_Bus_Multiplexing
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295 | * @{
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296 | */
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297 | |||
298 | #define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000) |
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299 | #define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002) |
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300 | #define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
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301 | ((MUX) == FSMC_DataAddressMux_Enable)) |
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302 | |||
303 | /**
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304 | * @}
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305 | */
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306 | |||
307 | /** @defgroup FSMC_Memory_Type
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308 | * @{
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309 | */
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310 | |||
311 | #define FSMC_MemoryType_SRAM ((uint32_t)0x00000000) |
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312 | #define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004) |
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313 | #define FSMC_MemoryType_NOR ((uint32_t)0x00000008) |
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314 | #define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
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315 | ((MEMORY) == FSMC_MemoryType_PSRAM)|| \ |
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316 | ((MEMORY) == FSMC_MemoryType_NOR)) |
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317 | |||
318 | /**
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319 | * @}
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320 | */
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321 | |||
322 | /** @defgroup FSMC_Data_Width
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323 | * @{
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324 | */
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325 | |||
326 | #define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000) |
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327 | #define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010) |
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328 | #define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
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329 | ((WIDTH) == FSMC_MemoryDataWidth_16b)) |
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330 | |||
331 | /**
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332 | * @}
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333 | */
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334 | |||
335 | /** @defgroup FSMC_Burst_Access_Mode
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336 | * @{
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337 | */
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338 | |||
339 | #define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000) |
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340 | #define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100) |
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341 | #define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
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342 | ((STATE) == FSMC_BurstAccessMode_Enable)) |
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343 | /**
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344 | * @}
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345 | */
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346 | |||
347 | /** @defgroup FSMC_AsynchronousWait
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348 | * @{
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349 | */
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350 | #define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000) |
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351 | #define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000) |
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352 | #define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \
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353 | ((STATE) == FSMC_AsynchronousWait_Enable)) |
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354 | |||
355 | /**
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356 | * @}
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357 | */
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358 | |||
359 | /** @defgroup FSMC_Wait_Signal_Polarity
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360 | * @{
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361 | */
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362 | |||
363 | #define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000) |
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364 | #define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200) |
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365 | #define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
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366 | ((POLARITY) == FSMC_WaitSignalPolarity_High)) |
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367 | |||
368 | /**
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369 | * @}
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370 | */
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371 | |||
372 | /** @defgroup FSMC_Wrap_Mode
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373 | * @{
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374 | */
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375 | |||
376 | #define FSMC_WrapMode_Disable ((uint32_t)0x00000000) |
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377 | #define FSMC_WrapMode_Enable ((uint32_t)0x00000400) |
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378 | #define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
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379 | ((MODE) == FSMC_WrapMode_Enable)) |
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380 | |||
381 | /**
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382 | * @}
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383 | */
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384 | |||
385 | /** @defgroup FSMC_Wait_Timing
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386 | * @{
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387 | */
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388 | |||
389 | #define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000) |
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390 | #define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) |
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391 | #define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
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392 | ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState)) |
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393 | |||
394 | /**
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395 | * @}
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396 | */
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397 | |||
398 | /** @defgroup FSMC_Write_Operation
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399 | * @{
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400 | */
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401 | |||
402 | #define FSMC_WriteOperation_Disable ((uint32_t)0x00000000) |
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403 | #define FSMC_WriteOperation_Enable ((uint32_t)0x00001000) |
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404 | #define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
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405 | ((OPERATION) == FSMC_WriteOperation_Enable)) |
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406 | |||
407 | /**
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408 | * @}
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409 | */
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410 | |||
411 | /** @defgroup FSMC_Wait_Signal
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412 | * @{
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413 | */
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414 | |||
415 | #define FSMC_WaitSignal_Disable ((uint32_t)0x00000000) |
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416 | #define FSMC_WaitSignal_Enable ((uint32_t)0x00002000) |
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417 | #define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
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418 | ((SIGNAL) == FSMC_WaitSignal_Enable)) |
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419 | /**
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420 | * @}
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421 | */
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422 | |||
423 | /** @defgroup FSMC_Extended_Mode
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424 | * @{
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425 | */
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426 | |||
427 | #define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000) |
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428 | #define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000) |
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429 | |||
430 | #define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
|
||
431 | ((MODE) == FSMC_ExtendedMode_Enable)) |
||
432 | |||
433 | /**
|
||
434 | * @}
|
||
435 | */
|
||
436 | |||
437 | /** @defgroup FSMC_Write_Burst
|
||
438 | * @{
|
||
439 | */
|
||
440 | |||
441 | #define FSMC_WriteBurst_Disable ((uint32_t)0x00000000) |
||
442 | #define FSMC_WriteBurst_Enable ((uint32_t)0x00080000) |
||
443 | #define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
|
||
444 | ((BURST) == FSMC_WriteBurst_Enable)) |
||
445 | /**
|
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446 | * @}
|
||
447 | */
|
||
448 | |||
449 | /** @defgroup FSMC_Address_Setup_Time
|
||
450 | * @{
|
||
451 | */
|
||
452 | |||
453 | #define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF) |
||
454 | |||
455 | /**
|
||
456 | * @}
|
||
457 | */
|
||
458 | |||
459 | /** @defgroup FSMC_Address_Hold_Time
|
||
460 | * @{
|
||
461 | */
|
||
462 | |||
463 | #define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF) |
||
464 | |||
465 | /**
|
||
466 | * @}
|
||
467 | */
|
||
468 | |||
469 | /** @defgroup FSMC_Data_Setup_Time
|
||
470 | * @{
|
||
471 | */
|
||
472 | |||
473 | #define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF)) |
||
474 | |||
475 | /**
|
||
476 | * @}
|
||
477 | */
|
||
478 | |||
479 | /** @defgroup FSMC_Bus_Turn_around_Duration
|
||
480 | * @{
|
||
481 | */
|
||
482 | |||
483 | #define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF) |
||
484 | |||
485 | /**
|
||
486 | * @}
|
||
487 | */
|
||
488 | |||
489 | /** @defgroup FSMC_CLK_Division
|
||
490 | * @{
|
||
491 | */
|
||
492 | |||
493 | #define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF) |
||
494 | |||
495 | /**
|
||
496 | * @}
|
||
497 | */
|
||
498 | |||
499 | /** @defgroup FSMC_Data_Latency
|
||
500 | * @{
|
||
501 | */
|
||
502 | |||
503 | #define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF) |
||
504 | |||
505 | /**
|
||
506 | * @}
|
||
507 | */
|
||
508 | |||
509 | /** @defgroup FSMC_Access_Mode
|
||
510 | * @{
|
||
511 | */
|
||
512 | |||
513 | #define FSMC_AccessMode_A ((uint32_t)0x00000000) |
||
514 | #define FSMC_AccessMode_B ((uint32_t)0x10000000) |
||
515 | #define FSMC_AccessMode_C ((uint32_t)0x20000000) |
||
516 | #define FSMC_AccessMode_D ((uint32_t)0x30000000) |
||
517 | #define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \
|
||
518 | ((MODE) == FSMC_AccessMode_B) || \ |
||
519 | ((MODE) == FSMC_AccessMode_C) || \ |
||
520 | ((MODE) == FSMC_AccessMode_D)) |
||
521 | |||
522 | /**
|
||
523 | * @}
|
||
524 | */
|
||
525 | |||
526 | /**
|
||
527 | * @}
|
||
528 | */
|
||
529 | |||
530 | /** @defgroup NAND_PCCARD_Controller
|
||
531 | * @{
|
||
532 | */
|
||
533 | |||
534 | /** @defgroup FSMC_Wait_feature
|
||
535 | * @{
|
||
536 | */
|
||
537 | |||
538 | #define FSMC_Waitfeature_Disable ((uint32_t)0x00000000) |
||
539 | #define FSMC_Waitfeature_Enable ((uint32_t)0x00000002) |
||
540 | #define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \
|
||
541 | ((FEATURE) == FSMC_Waitfeature_Enable)) |
||
542 | |||
543 | /**
|
||
544 | * @}
|
||
545 | */
|
||
546 | |||
547 | |||
548 | /** @defgroup FSMC_ECC
|
||
549 | * @{
|
||
550 | */
|
||
551 | |||
552 | #define FSMC_ECC_Disable ((uint32_t)0x00000000) |
||
553 | #define FSMC_ECC_Enable ((uint32_t)0x00000040) |
||
554 | #define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \
|
||
555 | ((STATE) == FSMC_ECC_Enable)) |
||
556 | |||
557 | /**
|
||
558 | * @}
|
||
559 | */
|
||
560 | |||
561 | /** @defgroup FSMC_ECC_Page_Size
|
||
562 | * @{
|
||
563 | */
|
||
564 | |||
565 | #define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000) |
||
566 | #define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000) |
||
567 | #define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000) |
||
568 | #define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000) |
||
569 | #define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000) |
||
570 | #define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000) |
||
571 | #define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \
|
||
572 | ((SIZE) == FSMC_ECCPageSize_512Bytes) || \ |
||
573 | ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \ |
||
574 | ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \ |
||
575 | ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \ |
||
576 | ((SIZE) == FSMC_ECCPageSize_8192Bytes)) |
||
577 | |||
578 | /**
|
||
579 | * @}
|
||
580 | */
|
||
581 | |||
582 | /** @defgroup FSMC_TCLR_Setup_Time
|
||
583 | * @{
|
||
584 | */
|
||
585 | |||
586 | #define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF) |
||
587 | |||
588 | /**
|
||
589 | * @}
|
||
590 | */
|
||
591 | |||
592 | /** @defgroup FSMC_TAR_Setup_Time
|
||
593 | * @{
|
||
594 | */
|
||
595 | |||
596 | #define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF) |
||
597 | |||
598 | /**
|
||
599 | * @}
|
||
600 | */
|
||
601 | |||
602 | /** @defgroup FSMC_Setup_Time
|
||
603 | * @{
|
||
604 | */
|
||
605 | |||
606 | #define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF) |
||
607 | |||
608 | /**
|
||
609 | * @}
|
||
610 | */
|
||
611 | |||
612 | /** @defgroup FSMC_Wait_Setup_Time
|
||
613 | * @{
|
||
614 | */
|
||
615 | |||
616 | #define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF) |
||
617 | |||
618 | /**
|
||
619 | * @}
|
||
620 | */
|
||
621 | |||
622 | /** @defgroup FSMC_Hold_Setup_Time
|
||
623 | * @{
|
||
624 | */
|
||
625 | |||
626 | #define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF) |
||
627 | |||
628 | /**
|
||
629 | * @}
|
||
630 | */
|
||
631 | |||
632 | /** @defgroup FSMC_HiZ_Setup_Time
|
||
633 | * @{
|
||
634 | */
|
||
635 | |||
636 | #define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF) |
||
637 | |||
638 | /**
|
||
639 | * @}
|
||
640 | */
|
||
641 | |||
642 | /** @defgroup FSMC_Interrupt_sources
|
||
643 | * @{
|
||
644 | */
|
||
645 | |||
646 | #define FSMC_IT_RisingEdge ((uint32_t)0x00000008) |
||
647 | #define FSMC_IT_Level ((uint32_t)0x00000010) |
||
648 | #define FSMC_IT_FallingEdge ((uint32_t)0x00000020) |
||
649 | #define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000)) |
||
650 | #define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \
|
||
651 | ((IT) == FSMC_IT_Level) || \ |
||
652 | ((IT) == FSMC_IT_FallingEdge)) |
||
653 | /**
|
||
654 | * @}
|
||
655 | */
|
||
656 | |||
657 | /** @defgroup FSMC_Flags
|
||
658 | * @{
|
||
659 | */
|
||
660 | |||
661 | #define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001) |
||
662 | #define FSMC_FLAG_Level ((uint32_t)0x00000002) |
||
663 | #define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004) |
||
664 | #define FSMC_FLAG_FEMPT ((uint32_t)0x00000040) |
||
665 | #define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \
|
||
666 | ((FLAG) == FSMC_FLAG_Level) || \ |
||
667 | ((FLAG) == FSMC_FLAG_FallingEdge) || \ |
||
668 | ((FLAG) == FSMC_FLAG_FEMPT)) |
||
669 | |||
670 | #define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000)) |
||
671 | |||
672 | /**
|
||
673 | * @}
|
||
674 | */
|
||
675 | |||
676 | /**
|
||
677 | * @}
|
||
678 | */
|
||
679 | |||
680 | /**
|
||
681 | * @}
|
||
682 | */
|
||
683 | |||
684 | /** @defgroup FSMC_Exported_Macros
|
||
685 | * @{
|
||
686 | */
|
||
687 | |||
688 | /**
|
||
689 | * @}
|
||
690 | */
|
||
691 | |||
692 | /** @defgroup FSMC_Exported_Functions
|
||
693 | * @{
|
||
694 | */
|
||
695 | |||
696 | void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
|
||
697 | void FSMC_NANDDeInit(uint32_t FSMC_Bank);
|
||
698 | void FSMC_PCCARDDeInit(void); |
||
699 | void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
|
||
700 | void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
|
||
701 | void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
|
||
702 | void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
|
||
703 | void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
|
||
704 | void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
|
||
705 | void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
|
||
706 | void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);
|
||
707 | void FSMC_PCCARDCmd(FunctionalState NewState);
|
||
708 | void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);
|
||
709 | uint32_t FSMC_GetECC(uint32_t FSMC_Bank); |
||
710 | void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);
|
||
711 | FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); |
||
712 | void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
|
||
713 | ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT); |
||
714 | void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);
|
||
715 | |||
716 | #ifdef __cplusplus
|
||
717 | } |
||
718 | #endif
|
||
719 | |||
720 | #endif /*__STM32F10x_FSMC_H */ |
||
721 | /**
|
||
722 | * @}
|
||
723 | */
|
||
724 | |||
725 | /**
|
||
726 | * @}
|
||
727 | */
|
||
728 | |||
729 | /**
|
||
730 | * @}
|
||
731 | */
|
||
732 | |||
733 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|