amiro-lld / include / L3G4200D / v1 / alld_L3G4200D_v1.h @ 067c98f7
History | View | Annotate | Download (11.057 KB)
| 1 | d6728c5b | Thomas Schöpping | /*
|
|---|---|---|---|
| 2 | AMiRo-LLD is a compilation of low-level hardware drivers for the Autonomous Mini Robot (AMiRo) platform.
|
||
| 3 | f125ae07 | Thomas Schöpping | Copyright (C) 2016..2019 Thomas Schöpping et al.
|
| 4 | d6728c5b | Thomas Schöpping | |
| 5 | This program is free software: you can redistribute it and/or modify
|
||
| 6 | f0ca400f | Thomas Schöpping | it under the terms of the GNU Lesser General Public License as published by
|
| 7 | d6728c5b | Thomas Schöpping | the Free Software Foundation, either version 3 of the License, or
|
| 8 | (at your option) any later version.
|
||
| 9 | |||
| 10 | This program is distributed in the hope that it will be useful,
|
||
| 11 | but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||
| 12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||
| 13 | f0ca400f | Thomas Schöpping | GNU Lesser General Public License for more details.
|
| 14 | d6728c5b | Thomas Schöpping | |
| 15 | f0ca400f | Thomas Schöpping | You should have received a copy of the GNU Lesser General Public License
|
| 16 | d6728c5b | Thomas Schöpping | along with this program. If not, see <http://www.gnu.org/licenses/>.
|
| 17 | */
|
||
| 18 | |||
| 19 | 5e2f673b | Marc Rothmann | /**
|
| 20 | 1d5bcc82 | Thomas Schöpping | * @file alld_L3G4200D_v1.h
|
| 21 | 5e2f673b | Marc Rothmann | * @brief Gyroscope macros and structures.
|
| 22 | *
|
||
| 23 | * @addtogroup lld_gyroscope
|
||
| 24 | * @{
|
||
| 25 | */
|
||
| 26 | |||
| 27 | 1d5bcc82 | Thomas Schöpping | #ifndef AMIROLLD_L3G4200D_V1_H
|
| 28 | #define AMIROLLD_L3G4200D_V1_H
|
||
| 29 | d6728c5b | Thomas Schöpping | |
| 30 | #include <amiro-lld.h> |
||
| 31 | |||
| 32 | 1d5bcc82 | Thomas Schöpping | #if (defined(AMIROLLD_CFG_L3G4200D) && (AMIROLLD_CFG_L3G4200D == 1)) || defined(__DOXYGEN__) |
| 33 | d6728c5b | Thomas Schöpping | |
| 34 | ef078306 | Thomas Schöpping | /******************************************************************************/
|
| 35 | /* CONSTANTS */
|
||
| 36 | /******************************************************************************/
|
||
| 37 | |||
| 38 | d6728c5b | Thomas Schöpping | /**
|
| 39 | * @brief A rising edge indicates an interrupt.
|
||
| 40 | */
|
||
| 41 | #define L3G4200D_LLD_INT_EDGE APAL_GPIO_EDGE_RISING
|
||
| 42 | |||
| 43 | ef078306 | Thomas Schöpping | /******************************************************************************/
|
| 44 | /* SETTINGS */
|
||
| 45 | /******************************************************************************/
|
||
| 46 | |||
| 47 | /******************************************************************************/
|
||
| 48 | /* CHECKS */
|
||
| 49 | /******************************************************************************/
|
||
| 50 | |||
| 51 | /******************************************************************************/
|
||
| 52 | /* DATA STRUCTURES AND TYPES */
|
||
| 53 | /******************************************************************************/
|
||
| 54 | |||
| 55 | d6728c5b | Thomas Schöpping | /**
|
| 56 | * @brief The L3G4200D driver struct
|
||
| 57 | */
|
||
| 58 | typedef struct { |
||
| 59 | apalSPIDriver_t* spid; /**< @brief The SPI Driver */
|
||
| 60 | } L3G4200DDriver; |
||
| 61 | |||
| 62 | /**
|
||
| 63 | * @brief SPI access modes.
|
||
| 64 | */
|
||
| 65 | typedef enum { |
||
| 66 | L3G4200D_LLD_SPI_MULT = 0x40u,
|
||
| 67 | L3G4200D_LLD_SPI_READ = 0x80u,
|
||
| 68 | L3G4200D_LLD_SPI_WRITE = 0x00u,
|
||
| 69 | } l3g4200d_lld_SPI_mode_t; |
||
| 70 | |||
| 71 | /**
|
||
| 72 | * @brief Registers.
|
||
| 73 | */
|
||
| 74 | typedef enum { |
||
| 75 | L3G4200D_LLD_REGISTER_WHO_AM_I = 0x0F,
|
||
| 76 | L3G4200D_LLD_REGISTER_CTRL_REG1 = 0x20,
|
||
| 77 | L3G4200D_LLD_REGISTER_CTRL_REG2 = 0x21,
|
||
| 78 | L3G4200D_LLD_REGISTER_CTRL_REG3 = 0x22,
|
||
| 79 | L3G4200D_LLD_REGISTER_CTRL_REG4 = 0x23,
|
||
| 80 | L3G4200D_LLD_REGISTER_CTRL_REG5 = 0x24,
|
||
| 81 | L3G4200D_LLD_REGISTER_REFERECE = 0x25,
|
||
| 82 | L3G4200D_LLD_REGISTER_OUT_TEMP = 0x26,
|
||
| 83 | L3G4200D_LLD_REGISTER_STATUS_REG = 0x27,
|
||
| 84 | L3G4200D_LLD_REGISTER_OUT_X_L = 0x28,
|
||
| 85 | L3G4200D_LLD_REGISTER_OUT_X_H = 0x29,
|
||
| 86 | L3G4200D_LLD_REGISTER_OUT_Y_L = 0x2A,
|
||
| 87 | L3G4200D_LLD_REGISTER_OUT_Y_H = 0x2B,
|
||
| 88 | L3G4200D_LLD_REGISTER_OUT_Z_L = 0x2C,
|
||
| 89 | L3G4200D_LLD_REGISTER_OUT_Z_H = 0x2D,
|
||
| 90 | L3G4200D_LLD_REGISTER_FIFO_CTRL_REG = 0x2E,
|
||
| 91 | L3G4200D_LLD_REGISTER_FIFO_SRC_REG = 0x2F,
|
||
| 92 | L3G4200D_LLD_REGISTER_INT1_CFG = 0x30,
|
||
| 93 | L3G4200D_LLD_REGISTER_INT1_SRC = 0x31,
|
||
| 94 | L3G4200D_LLD_REGISTER_INT1_TSH_XH = 0x32,
|
||
| 95 | L3G4200D_LLD_REGISTER_INT1_TSH_XL = 0x33,
|
||
| 96 | L3G4200D_LLD_REGISTER_INT1_TSH_YH = 0x34,
|
||
| 97 | L3G4200D_LLD_REGISTER_INT1_TSH_YL = 0x35,
|
||
| 98 | L3G4200D_LLD_REGISTER_INT1_TSH_ZH = 0x36,
|
||
| 99 | L3G4200D_LLD_REGISTER_INT1_TSH_ZL = 0x37,
|
||
| 100 | L3G4200D_LLD_REGISTER_INT1_DURATION = 0x38,
|
||
| 101 | } l3g4200d_lld_register_t; |
||
| 102 | |||
| 103 | /**
|
||
| 104 | * @brief WHO_AM_I register constant content.
|
||
| 105 | */
|
||
| 106 | typedef enum { |
||
| 107 | L3G4200D_LLD_WHO_AM_I = 0xD3,
|
||
| 108 | } l3g4200d_lld_whoami_t; |
||
| 109 | |||
| 110 | /**
|
||
| 111 | * @brief Control register 1 flags.
|
||
| 112 | */
|
||
| 113 | typedef enum { |
||
| 114 | L3G4200D_LLD_DR_100_HZ = 0x00,
|
||
| 115 | L3G4200D_LLD_DR_200_HZ = 0x40,
|
||
| 116 | L3G4200D_LLD_DR_400_HZ = 0x80,
|
||
| 117 | L3G4200D_LLD_DR_800_HZ = 0xC0,
|
||
| 118 | L3G4200D_LLD_BW_12_5 = 0x00,
|
||
| 119 | L3G4200D_LLD_BW_20 = 0x00,
|
||
| 120 | L3G4200D_LLD_BW_25 = 0x10,
|
||
| 121 | L3G4200D_LLD_BW_30 = 0x00,
|
||
| 122 | L3G4200D_LLD_BW_35 = 0x10,
|
||
| 123 | L3G4200D_LLD_BW_50 = 0x20,
|
||
| 124 | L3G4200D_LLD_BW_70 = 0x30,
|
||
| 125 | L3G4200D_LLD_BW_110 = 0x30,
|
||
| 126 | L3G4200D_LLD_PD = 0x08,
|
||
| 127 | L3G4200D_LLD_ZEN = 0x04,
|
||
| 128 | L3G4200D_LLD_YEN = 0x02,
|
||
| 129 | L3G4200D_LLD_XEN = 0x01,
|
||
| 130 | } l3g4200d_lld_ctrl_reg1_t; |
||
| 131 | |||
| 132 | /**
|
||
| 133 | * @brief Control register 2 flags.
|
||
| 134 | */
|
||
| 135 | typedef enum { |
||
| 136 | L3G4200D_LLD_HPM_NORMAL_RST = 0x00,
|
||
| 137 | L3G4200D_LLD_HPM_REFERENCE = 0x10,
|
||
| 138 | L3G4200D_LLD_HPM_NORMAL = 0x20,
|
||
| 139 | L3G4200D_LLD_HPM_AUTO_RST = 0x30,
|
||
| 140 | L3G4200D_LLD_HPCF_2 = 0x00,
|
||
| 141 | L3G4200D_LLD_HPCF_4 = 0x01,
|
||
| 142 | L3G4200D_LLD_HPCF_8 = 0x02,
|
||
| 143 | L3G4200D_LLD_HPCF_16 = 0x03,
|
||
| 144 | L3G4200D_LLD_HPCF_32 = 0x04,
|
||
| 145 | L3G4200D_LLD_HPCF_64 = 0x05,
|
||
| 146 | L3G4200D_LLD_HPCF_128 = 0x06,
|
||
| 147 | L3G4200D_LLD_HPCF_256 = 0x07,
|
||
| 148 | L3G4200D_LLD_HPCF_512 = 0x08,
|
||
| 149 | L3G4200D_LLD_HPCF_1024 = 0x09,
|
||
| 150 | } l3g4200d_lld_ctrl_reg2_t; |
||
| 151 | |||
| 152 | /**
|
||
| 153 | * @brief Control register 3 flags.
|
||
| 154 | */
|
||
| 155 | typedef enum { |
||
| 156 | L3G4200D_LLD_I1_INT1 = 0x80,
|
||
| 157 | L3G4200D_LLD_I1_BOOT = 0x40,
|
||
| 158 | L3G4200D_LLD_H_IACTIVE = 0x20,
|
||
| 159 | L3G4200D_LLD_PP_OD = 0x10,
|
||
| 160 | L3G4200D_LLD_I2_DRDY = 0x08,
|
||
| 161 | L3G4200D_LLD_I2_WTM = 0x04,
|
||
| 162 | L3G4200D_LLD_I2_ORUN = 0x02,
|
||
| 163 | L3G4200D_LLD_I2_EMPTY = 0x01,
|
||
| 164 | } l3g4200d_lld_ctrl_reg3_t; |
||
| 165 | |||
| 166 | /**
|
||
| 167 | * @brief Control register 4 flags.
|
||
| 168 | */
|
||
| 169 | typedef enum { |
||
| 170 | L3G4200D_LLD_BDU_CONT = 0x00,
|
||
| 171 | L3G4200D_LLD_BDU_SINGLE = 0x80,
|
||
| 172 | L3G4200D_LLD_BLE_MSB = 0x40,
|
||
| 173 | L3G4200D_LLD_BLE_LSB = 0x00,
|
||
| 174 | L3G4200D_LLD_FS_250_DPS = 0x00,
|
||
| 175 | L3G4200D_LLD_FS_500_DPS = 0x10,
|
||
| 176 | L3G4200D_LLD_FS_2000_DPS = 0x20,
|
||
| 177 | L3G4200D_LLD_ST_SIGN_M = 0x04,
|
||
| 178 | L3G4200D_LLD_ST_SIGN_P = 0x00,
|
||
| 179 | L3G4200D_LLD_ST_EN = 0x02,
|
||
| 180 | L3G4200D_LLD_SIM_3W = 0x01,
|
||
| 181 | L3G4200D_LLD_SIM_4W = 0x00,
|
||
| 182 | } l3g4200d_lld_ctrl_reg4_t; |
||
| 183 | |||
| 184 | /**
|
||
| 185 | * @brief Control register 5 flags.
|
||
| 186 | */
|
||
| 187 | typedef enum { |
||
| 188 | L3G4200D_LLD_BOOT = 0x80,
|
||
| 189 | L3G4200D_LLD_FIFO_EN = 0x40,
|
||
| 190 | L3G4200D_LLD_HP_EN = 0x10,
|
||
| 191 | L3G4200D_LLD_INT1_SEL_NOHP = 0x00,
|
||
| 192 | L3G4200D_LLD_INT1_SEL_HP = 0x04,
|
||
| 193 | L3G4200D_LLD_INT1_SEL_LP = 0x08,
|
||
| 194 | L3G4200D_LLD_OUT_SEL_NOHP = 0x00,
|
||
| 195 | L3G4200D_LLD_OUT_SEL_HP = 0x01,
|
||
| 196 | L3G4200D_LLD_OUT_SEL_LP = 0x02,
|
||
| 197 | } l3g4200d_lld_ctrl_reg5_t; |
||
| 198 | |||
| 199 | /**
|
||
| 200 | * @brief Status register flags.
|
||
| 201 | */
|
||
| 202 | typedef enum { |
||
| 203 | L3G4200D_LLD_ZYXOR = 0x80,
|
||
| 204 | L3G4200D_LLD_ZOR = 0x40,
|
||
| 205 | L3G4200D_LLD_YOR = 0x20,
|
||
| 206 | L3G4200D_LLD_XOR = 0x10,
|
||
| 207 | L3G4200D_LLD_ZYXDA = 0x08,
|
||
| 208 | L3G4200D_LLD_ZDA = 0x04,
|
||
| 209 | L3G4200D_LLD_YDA = 0x02,
|
||
| 210 | L3G4200D_LLD_XDA = 0x01,
|
||
| 211 | } l3g4200d_lld_status_reg_t; |
||
| 212 | |||
| 213 | /**
|
||
| 214 | * @brief Fifo control register masks.
|
||
| 215 | */
|
||
| 216 | typedef enum { |
||
| 217 | L3G4200D_LLD_FM_BYPASS = 0x00,
|
||
| 218 | L3G4200D_LLD_FM_FMMODE = 0x20,
|
||
| 219 | L3G4200D_LLD_FM_STREAM = 0x40,
|
||
| 220 | L3G4200D_LLD_FM_STREAM2FIFO = 0x60,
|
||
| 221 | L3G4200D_LLD_FM_BYPASS2STREAM = 0x80,
|
||
| 222 | L3G4200D_LLD_WTM_MASK = 0x1F,
|
||
| 223 | } l3g4200d_lld_fifo_ctrl_reg_t; |
||
| 224 | |||
| 225 | /**
|
||
| 226 | * @brief FIFO source register masks.
|
||
| 227 | */
|
||
| 228 | typedef enum { |
||
| 229 | L3G4200D_LLD_WTM = 0x80,
|
||
| 230 | L3G4200D_LLD_OVRN = 0x40,
|
||
| 231 | L3G4200D_LLD_EMPTY = 0x20,
|
||
| 232 | L3G4200D_LLD_FSS_MASK = 0x1F,
|
||
| 233 | } l3g4200d_lld_fifo_src_reg_t; |
||
| 234 | |||
| 235 | /**
|
||
| 236 | * @brief Interrupt 1 config register flags.
|
||
| 237 | */
|
||
| 238 | typedef enum { |
||
| 239 | L3G4200D_LLD_ANDOR = 0x80,
|
||
| 240 | L3G4200D_LLD_LIR = 0x40,
|
||
| 241 | L3G4200D_LLD_ZHIE = 0x20,
|
||
| 242 | L3G4200D_LLD_ZLIE = 0x10,
|
||
| 243 | L3G4200D_LLD_YHIE = 0x08,
|
||
| 244 | L3G4200D_LLD_YLIE = 0x04,
|
||
| 245 | L3G4200D_LLD_XHIE = 0x02,
|
||
| 246 | L3G4200D_LLD_XLIE = 0x01,
|
||
| 247 | } l3g4200d_lld_int1_cfg_reg_t; |
||
| 248 | |||
| 249 | /**
|
||
| 250 | * @brief Interrupt 1 source register flags.
|
||
| 251 | */
|
||
| 252 | typedef enum { |
||
| 253 | L3G4200D_LLD_IA = 0x40,
|
||
| 254 | L3G4200D_LLD_ZH = 0x20,
|
||
| 255 | L3G4200D_LLD_ZL = 0x10,
|
||
| 256 | L3G4200D_LLD_YH = 0x08,
|
||
| 257 | L3G4200D_LLD_YL = 0x04,
|
||
| 258 | L3G4200D_LLD_XH = 0x02,
|
||
| 259 | L3G4200D_LLD_XL = 0x01,
|
||
| 260 | } l3g4200d_lld_int1_src_t; |
||
| 261 | |||
| 262 | /**
|
||
| 263 | * @brief Threshold mask.
|
||
| 264 | */
|
||
| 265 | enum {
|
||
| 266 | L3G4200D_LLD_THS_L_MASK = 0x7F
|
||
| 267 | }; |
||
| 268 | |||
| 269 | /**
|
||
| 270 | * @brief Interrupt duration register masks.
|
||
| 271 | */
|
||
| 272 | typedef enum { |
||
| 273 | L3G4200D_LLD_INT1_WAIT = 0x80,
|
||
| 274 | L3G4200D_LLD_INT1_DURATION_MASK = 0x7F,
|
||
| 275 | } l3g4200d_lld_int1_duration_reg_t; |
||
| 276 | |||
| 277 | /**
|
||
| 278 | * @brief Axis enum.
|
||
| 279 | */
|
||
| 280 | typedef enum { |
||
| 281 | L3G4200D_LLD_X_AXIS = 0x00,
|
||
| 282 | L3G4200D_LLD_Y_AXIS = 0x01,
|
||
| 283 | L3G4200D_LLD_Z_AXIS = 0x02,
|
||
| 284 | } l3g4200d_lld_axis_t; |
||
| 285 | |||
| 286 | /**
|
||
| 287 | * @brief Config register struct.
|
||
| 288 | */
|
||
| 289 | typedef union { |
||
| 290 | uint8_t data[5];
|
||
| 291 | struct {
|
||
| 292 | uint8_t ctrl_reg1; |
||
| 293 | uint8_t ctrl_reg2; |
||
| 294 | uint8_t ctrl_reg3; |
||
| 295 | uint8_t ctrl_reg4; |
||
| 296 | uint8_t ctrl_reg5; |
||
| 297 | } registers; |
||
| 298 | } l3g4200d_lld_cfg_t; |
||
| 299 | |||
| 300 | /**
|
||
| 301 | * @brief Interrupt config struct.
|
||
| 302 | */
|
||
| 303 | typedef union { |
||
| 304 | uint8_t data[9];
|
||
| 305 | struct {
|
||
| 306 | uint8_t int1_cfg; |
||
| 307 | uint8_t int1_src; |
||
| 308 | uint8_t int1_tsh_xh; |
||
| 309 | uint8_t int1_tsh_xl; |
||
| 310 | uint8_t int1_tsh_yh; |
||
| 311 | uint8_t int1_tsh_yl; |
||
| 312 | uint8_t int1_tsh_zh; |
||
| 313 | uint8_t int1_tsh_zl; |
||
| 314 | uint8_t int1_duration; |
||
| 315 | } registers; |
||
| 316 | } l3g4200d_lld_int_cfg_t; |
||
| 317 | |||
| 318 | ef078306 | Thomas Schöpping | /******************************************************************************/
|
| 319 | /* MACROS */
|
||
| 320 | /******************************************************************************/
|
||
| 321 | |||
| 322 | /******************************************************************************/
|
||
| 323 | /* EXTERN DECLARATIONS */
|
||
| 324 | /******************************************************************************/
|
||
| 325 | |||
| 326 | d6728c5b | Thomas Schöpping | #ifdef __cplusplus
|
| 327 | extern "C" { |
||
| 328 | #endif
|
||
| 329 | apalExitStatus_t l3g4200d_lld_read_register(const L3G4200DDriver* const l3gd, const l3g4200d_lld_register_t regaddr, uint8_t* const data, const uint8_t length); |
||
| 330 | apalExitStatus_t l3g4200d_lld_write_register(const L3G4200DDriver* const l3gd, const l3g4200d_lld_register_t regaddr, const uint8_t* const data, const uint8_t length); |
||
| 331 | apalExitStatus_t l3g4200d_lld_read_all_data(const L3G4200DDriver* const l3gd, int16_t* const data, const l3g4200d_lld_cfg_t* const cfg); |
||
| 332 | apalExitStatus_t l3g4200d_lld_read_data(const L3G4200DDriver* const l3gd, int16_t* const data, const l3g4200d_lld_axis_t axis, const l3g4200d_lld_cfg_t* const cfg); |
||
| 333 | apalExitStatus_t l3g4200d_lld_read_config(const L3G4200DDriver* const l3gd, l3g4200d_lld_cfg_t* const cfg); |
||
| 334 | apalExitStatus_t l3g4200d_lld_write_config(const L3G4200DDriver* const l3gd, const l3g4200d_lld_cfg_t cfg); |
||
| 335 | apalExitStatus_t l3g4200d_lld_read_int_config(const L3G4200DDriver* const l3gd, l3g4200d_lld_int_cfg_t* const cfg); |
||
| 336 | apalExitStatus_t l3g4200d_lld_write_int_config(const L3G4200DDriver* const l3gd, const l3g4200d_lld_int_cfg_t cfg); |
||
| 337 | apalExitStatus_t l3g4200d_lld_read_int_src(const L3G4200DDriver* const l3gd, uint8_t* const cfg); |
||
| 338 | apalExitStatus_t l3g4200d_lld_read_status_register(const L3G4200DDriver* const l3gd, uint8_t* const status); |
||
| 339 | apalExitStatus_t l3g4200d_lld_read_fifo_ctrl_register(const L3G4200DDriver* const l3gd, uint8_t* const fifo); |
||
| 340 | apalExitStatus_t l3g4200d_lld_write_fifo_ctrl_register(const L3G4200DDriver* const l3gd, const uint8_t fifo); |
||
| 341 | apalExitStatus_t l3g4200d_lld_read_fifo_src_register(const L3G4200DDriver* const l3gdd, uint8_t* const fifo); |
||
| 342 | #ifdef __cplusplus
|
||
| 343 | } |
||
| 344 | #endif
|
||
| 345 | |||
| 346 | ef078306 | Thomas Schöpping | /******************************************************************************/
|
| 347 | /* INLINE FUNCTIONS */
|
||
| 348 | /******************************************************************************/
|
||
| 349 | |||
| 350 | 1d5bcc82 | Thomas Schöpping | #endif /* defined(AMIROLLD_CFG_L3G4200D) && (AMIROLLD_CFG_L3G4200D == 1) */ |
| 351 | d6728c5b | Thomas Schöpping | |
| 352 | 1d5bcc82 | Thomas Schöpping | #endif /* AMIROLLD_L3G4200D_V1_H */ |
| 353 | 5e2f673b | Marc Rothmann | |
| 354 | /** @} */ |