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/*! ------------------------------------------------------------------------------------------------------------------
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* @file deca_regs.h
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* @brief DW1000 Register Definitions
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* This file supports assembler and C development for DW1000 enabled devices
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*
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* @attention
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*
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* Copyright 2013 (c) Decawave Ltd, Dublin, Ireland.
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*
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* All rights reserved.
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*
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*/
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#ifndef _DECA_REGS_H_
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#define _DECA_REGS_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <amiro-lld.h>
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#if defined(AMIROLLD_CFG_USE_DW1000) || defined(__DOXYGEN__)
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/****************************************************************************//**
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* @brief Bit definitions for register DEV_ID
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**/
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#define DEV_ID_ID 0x00 /* Device ID register, includes revision info (0xDECA0130) */
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#define DEV_ID_LEN (4)
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/* mask and shift */
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#define DEV_ID_REV_MASK 0x0000000FUL /* Revision */
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#define DEV_ID_VER_MASK 0x000000F0UL /* Version */
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#define DEV_ID_MODEL_MASK 0x0000FF00UL /* The MODEL identifies the device. The DW1000 is device type 0x01 */
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#define DEV_ID_RIDTAG_MASK 0xFFFF0000UL /* Register Identification Tag 0XDECA */
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/****************************************************************************//**
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* @brief Bit definitions for register EUI_64
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**/
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#define EUI_64_ID 0x01 /* IEEE Extended Unique Identifier (63:0) */
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#define EUI_64_OFFSET 0x00
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#define EUI_64_LEN (8)
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/****************************************************************************//**
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* @brief Bit definitions for register PANADR
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**/
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#define PANADR_ID 0x03 /* PAN ID (31:16) and Short Address (15:0) */
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#define PANADR_LEN (4)
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/*mask and shift */
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#define PANADR_SHORT_ADDR_OFFSET 0 /* In bytes */
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#define PANADR_SHORT_ADDR_MASK 0x0000FFFFUL /* Short Address */
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#define PANADR_PAN_ID_OFFSET 2 /* In bytes */
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#define PANADR_PAN_ID_MASK 0xFFFF00F0UL /* PAN Identifier */
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/****************************************************************************//**
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* @brief Bit definitions for register 0x05
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**/
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#define REG_05_ID_RESERVED 0x05
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/****************************************************************************//**
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* @brief Bit definitions for register SYS_CFG
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**/
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#define SYS_CFG_ID 0x04 /* System Configuration (31:0) */
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#define SYS_CFG_LEN (4)
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/*mask and shift */
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#define SYS_CFG_MASK 0xF047FFFFUL /* access mask to SYS_CFG_ID */
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#define SYS_CFG_FF_ALL_EN 0x000001FEUL /* Frame filtering options all frames allowed */
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/*offset 0 */
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#define SYS_CFG_FFE 0x00000001UL /* Frame Filtering Enable. This bit enables the frame filtering functionality */
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#define SYS_CFG_FFBC 0x00000002UL /* Frame Filtering Behave as a Co-ordinator */
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#define SYS_CFG_FFAB 0x00000004UL /* Frame Filtering Allow Beacon frame reception */
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#define SYS_CFG_FFAD 0x00000008UL /* Frame Filtering Allow Data frame reception */
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#define SYS_CFG_FFAA 0x00000010UL /* Frame Filtering Allow Acknowledgment frame reception */
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#define SYS_CFG_FFAM 0x00000020UL /* Frame Filtering Allow MAC command frame reception */
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#define SYS_CFG_FFAR 0x00000040UL /* Frame Filtering Allow Reserved frame types */
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#define SYS_CFG_FFA4 0x00000080UL /* Frame Filtering Allow frames with frame type field of 4, (binary 100) */
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/*offset 8 */
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#define SYS_CFG_FFA5 0x00000100UL /* Frame Filtering Allow frames with frame type field of 5, (binary 101) */
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#define SYS_CFG_HIRQ_POL 0x00000200UL /* Host interrupt polarity */
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#define SYS_CFG_SPI_EDGE 0x00000400UL /* SPI data launch edge */
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#define SYS_CFG_DIS_FCE 0x00000800UL /* Disable frame check error handling */
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#define SYS_CFG_DIS_DRXB 0x00001000UL /* Disable Double RX Buffer */
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#define SYS_CFG_DIS_PHE 0x00002000UL /* Disable receiver abort on PHR error */
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#define SYS_CFG_DIS_RSDE 0x00004000UL /* Disable Receiver Abort on RSD error */
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#define SYS_CFG_FCS_INIT2F 0x00008000UL /* initial seed value for the FCS generation and checking function */
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/*offset 16 */
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#define SYS_CFG_PHR_MODE_SHFT 16
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#define SYS_CFG_PHR_MODE_00 0x00000000UL /* Standard Frame mode */
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#define SYS_CFG_PHR_MODE_11 0x00030000UL /* Long Frames mode */
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#define SYS_CFG_DIS_STXP 0x00040000UL /* Disable Smart TX Power control */
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#define SYS_CFG_RXM110K 0x00400000UL /* Receiver Mode 110 kbps data rate */
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/*offset 24 */
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#define SYS_CFG_RXWTOE 0x10000000UL /* Receive Wait Timeout Enable. */
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#define SYS_CFG_RXAUTR 0x20000000UL /* Receiver Auto-Re-enable. This bit is used to cause the receiver to re-enable automatically */
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#define SYS_CFG_AUTOACK 0x40000000UL /* Automatic Acknowledgement Enable */
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#define SYS_CFG_AACKPEND 0x80000000UL /* Automatic Acknowledgement Pending bit control */
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/****************************************************************************//**
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* @brief Bit definitions for register SYS_TIME
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**/
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#define SYS_TIME_ID 0x06 /* System Time Counter (40-bit) */
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#define SYS_TIME_OFFSET 0x00
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#define SYS_TIME_LEN (5) /* Note 40 bit register */
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/****************************************************************************//**
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* @brief Bit definitions for register 0x07
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**/
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#define REG_07_ID_RESERVED 0x07
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/****************************************************************************//**
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* @brief Bit definitions for register TX_FCTRL
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**/
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#define TX_FCTRL_ID 0x08 /* Transmit Frame Control */
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#define TX_FCTRL_LEN (5) /* Note 40 bit register */
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/*masks (low 32 bit) */
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#define TX_FCTRL_TFLEN_MASK 0x0000007FUL /* bit mask to access Transmit Frame Length */
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#define TX_FCTRL_TFLE_MASK 0x00000380UL /* bit mask to access Transmit Frame Length Extension */
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#define TX_FCTRL_FLE_MASK 0x000003FFUL /* bit mask to access Frame Length field */
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#define TX_FCTRL_TXBR_MASK 0x00006000UL /* bit mask to access Transmit Bit Rate */
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#define TX_FCTRL_TXPRF_MASK 0x00030000UL /* bit mask to access Transmit Pulse Repetition Frequency */
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#define TX_FCTRL_TXPSR_MASK 0x000C0000UL /* bit mask to access Transmit Preamble Symbol Repetitions (PSR). */
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#define TX_FCTRL_PE_MASK 0x00300000UL /* bit mask to access Preamble Extension */
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#define TX_FCTRL_TXPSR_PE_MASK 0x003C0000UL /* bit mask to access Transmit Preamble Symbol Repetitions (PSR). */
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#define TX_FCTRL_SAFE_MASK_32 0xFFFFE3FFUL /* FSCTRL has fields which should always be writen zero */
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/*offset 0 */
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/*offset 8 */
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#define TX_FCTRL_TXBR_110k 0x00000000UL /* Transmit Bit Rate = 110k */
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#define TX_FCTRL_TXBR_850k 0x00002000UL /* Transmit Bit Rate = 850k */
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#define TX_FCTRL_TXBR_6M 0x00004000UL /* Transmit Bit Rate = 6.8M */
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#define TX_FCTRL_TXBR_SHFT (13) /* shift to access Data Rate field */
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#define TX_FCTRL_TR 0x00008000UL /* Transmit Ranging enable */
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#define TX_FCTRL_TR_SHFT (15) /* shift to access Ranging bit */
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/*offset 16 */
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#define TX_FCTRL_TXPRF_SHFT (16) /* shift to access Pulse Repetition Frequency field */
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#define TX_FCTRL_TXPRF_4M 0x00000000UL /* Transmit Pulse Repetition Frequency = 4 Mhz */
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#define TX_FCTRL_TXPRF_16M 0x00010000UL /* Transmit Pulse Repetition Frequency = 16 Mhz */
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#define TX_FCTRL_TXPRF_64M 0x00020000UL /* Transmit Pulse Repetition Frequency = 64 Mhz */
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#define TX_FCTRL_TXPSR_SHFT (18) /* shift to access Preamble Symbol Repetitions field */
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#define TX_FCTRL_PE_SHFT (20) /* shift to access Preamble length Extension to allow specification of non-standard values */
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#define TX_FCTRL_TXPSR_PE_16 0x00000000UL /* bit mask to access Preamble Extension = 16 */
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#define TX_FCTRL_TXPSR_PE_64 0x00040000UL /* bit mask to access Preamble Extension = 64 */
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#define TX_FCTRL_TXPSR_PE_128 0x00140000UL /* bit mask to access Preamble Extension = 128 */
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#define TX_FCTRL_TXPSR_PE_256 0x00240000UL /* bit mask to access Preamble Extension = 256 */
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#define TX_FCTRL_TXPSR_PE_512 0x00340000UL /* bit mask to access Preamble Extension = 512 */
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#define TX_FCTRL_TXPSR_PE_1024 0x00080000UL /* bit mask to access Preamble Extension = 1024 */
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#define TX_FCTRL_TXPSR_PE_1536 0x00180000UL /* bit mask to access Preamble Extension = 1536 */
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#define TX_FCTRL_TXPSR_PE_2048 0x00280000UL /* bit mask to access Preamble Extension = 2048 */
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#define TX_FCTRL_TXPSR_PE_4096 0x000C0000UL /* bit mask to access Preamble Extension = 4096 */
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/*offset 22 */
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#define TX_FCTRL_TXBOFFS_SHFT (22) /* Shift to access transmit buffer index offset */
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#define TX_FCTRL_TXBOFFS_MASK 0xFFC00000UL /* bit mask to access Transmit buffer index offset 10-bit field */
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/*offset 32 */
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#define TX_FCTRL_IFSDELAY_MASK 0xFF00000000ULL /* bit mask to access Inter-Frame Spacing field */
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/****************************************************************************//**
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* @brief Bit definitions for register TX_BUFFER
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**/
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#define TX_BUFFER_ID 0x09 /* Transmit Data Buffer */
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#define TX_BUFFER_LEN (1024)
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/****************************************************************************//**
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* @brief Bit definitions for register DX_TIME
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**/
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#define DX_TIME_ID 0x0A /* Delayed Send or Receive Time (40-bit) */
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#define DX_TIME_LEN (5)
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/****************************************************************************//**
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* @brief Bit definitions for register 0x08
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**/
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#define REG_0B_ID_RESERVED 0x0B
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/****************************************************************************//**
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* @brief Bit definitions for register RX_FWTO
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**/
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#define RX_FWTO_ID 0x0C /* Receive Frame Wait Timeout Period */
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#define RX_FWTO_OFFSET 0x00
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#define RX_FWTO_LEN (2) /* doc bug*/
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/*mask and shift */
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#define RX_FWTO_MASK 0xFFFF
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/****************************************************************************//**
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* @brief Bit definitions for register SYS_CTRL
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**/
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#define SYS_CTRL_ID 0x0D /* System Control Register */
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#define SYS_CTRL_OFFSET 0x00
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#define SYS_CTRL_LEN (4)
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/*masks */
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#define SYS_CTRL_MASK_32 0x010003CFUL /* System Control Register access mask (all unused fields should always be writen as zero) */
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/*offset 0 */
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#define SYS_CTRL_SFCST 0x00000001UL /* Suppress Auto-FCS Transmission (on this frame) */
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#define SYS_CTRL_TXSTRT 0x00000002UL /* Start Transmitting Now */
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#define SYS_CTRL_TXDLYS 0x00000004UL /* Transmitter Delayed Sending (initiates sending when SYS_TIME == TXD_TIME */
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#define SYS_CTRL_CANSFCS 0x00000008UL /* Cancel Suppression of auto-FCS transmission (on the current frame) */
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#define SYS_CTRL_TRXOFF 0x00000040UL /* Transceiver Off. Force Transciever OFF abort TX or RX immediately */
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#define SYS_CTRL_WAIT4RESP 0x00000080UL /* Wait for Response */
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/*offset 8 */
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#define SYS_CTRL_RXENAB 0x00000100UL /* Enable Receiver Now */
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#define SYS_CTRL_RXDLYE 0x00000200UL /* Receiver Delayed Enable (Enables Receiver when SY_TIME[0x??] == RXD_TIME[0x??] CHECK comment*/
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/*offset 16 */
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| 200 |
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/*offset 24 */
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#define SYS_CTRL_HSRBTOGGLE 0x01000000UL /* Host side receiver buffer pointer toggle - toggles 0/1 host side data set pointer */
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#define SYS_CTRL_HRBT (SYS_CTRL_HSRBTOGGLE)
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#define SYS_CTRL_HRBT_OFFSET (3)
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/****************************************************************************//**
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* @brief Bit definitions for register SYS_MASK
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**/
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#define SYS_MASK_ID 0x0E /* System Event Mask Register */
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#define SYS_MASK_LEN (4)
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/*masks */
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#define SYS_MASK_MASK_32 0x3FF7FFFEUL /* System Event Mask Register access mask (all unused fields should always be writen as zero) */
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/*offset 0 */
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| 213 |
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#define SYS_MASK_MCPLOCK 0x00000002UL /* Mask clock PLL lock event */
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#define SYS_MASK_MESYNCR 0x00000004UL /* Mask clock PLL lock event */
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#define SYS_MASK_MAAT 0x00000008UL /* Mask automatic acknowledge trigger event */
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#define SYS_MASK_MTXFRB 0x00000010UL /* Mask transmit frame begins event */
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#define SYS_MASK_MTXPRS 0x00000020UL /* Mask transmit preamble sent event */
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| 218 |
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#define SYS_MASK_MTXPHS 0x00000040UL /* Mask transmit PHY Header Sent event */
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| 219 |
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#define SYS_MASK_MTXFRS 0x00000080UL /* Mask transmit frame sent event */
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| 220 |
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/*offset 8 */
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| 221 |
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#define SYS_MASK_MRXPRD 0x00000100UL /* Mask receiver preamble detected event */
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| 222 |
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#define SYS_MASK_MRXSFDD 0x00000200UL /* Mask receiver SFD detected event */
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| 223 |
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#define SYS_MASK_MLDEDONE 0x00000400UL /* Mask LDE processing done event */
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| 224 |
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#define SYS_MASK_MRXPHD 0x00000800UL /* Mask receiver PHY header detect event */
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| 225 |
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#define SYS_MASK_MRXPHE 0x00001000UL /* Mask receiver PHY header error event */
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| 226 |
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#define SYS_MASK_MRXDFR 0x00002000UL /* Mask receiver data frame ready event */
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| 227 |
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#define SYS_MASK_MRXFCG 0x00004000UL /* Mask receiver FCS good event */
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| 228 |
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#define SYS_MASK_MRXFCE 0x00008000UL /* Mask receiver FCS error event */
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| 229 |
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/*offset 16 */
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| 230 |
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#define SYS_MASK_MRXRFSL 0x00010000UL /* Mask receiver Reed Solomon Frame Sync Loss event */
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| 231 |
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#define SYS_MASK_MRXRFTO 0x00020000UL /* Mask Receive Frame Wait Timeout event */
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| 232 |
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#define SYS_MASK_MLDEERR 0x00040000UL /* Mask leading edge detection processing error event */
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| 233 |
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#define SYS_MASK_MRXOVRR 0x00100000UL /* Mask Receiver Overrun event */
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| 234 |
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#define SYS_MASK_MRXPTO 0x00200000UL /* Mask Preamble detection timeout event */
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| 235 |
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#define SYS_MASK_MGPIOIRQ 0x00400000UL /* Mask GPIO interrupt event */
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| 236 |
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#define SYS_MASK_MSLP2INIT 0x00800000UL /* Mask SLEEP to INIT event */
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| 237 |
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/*offset 24*/
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| 238 |
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#define SYS_MASK_MRFPLLLL 0x01000000UL /* Mask RF PLL Loosing Lock warning event */
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| 239 |
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#define SYS_MASK_MCPLLLL 0x02000000UL /* Mask Clock PLL Loosing Lock warning event */
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| 240 |
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#define SYS_MASK_MRXSFDTO 0x04000000UL /* Mask Receive SFD timeout event */
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| 241 |
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#define SYS_MASK_MHPDWARN 0x08000000UL /* Mask Half Period Delay Warning event */
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| 242 |
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#define SYS_MASK_MTXBERR 0x10000000UL /* Mask Transmit Buffer Error event */
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| 243 |
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#define SYS_MASK_MAFFREJ 0x20000000UL /* Mask Automatic Frame Filtering rejection event */
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| 244 |
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| 245 |
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/****************************************************************************//**
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| 246 |
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* @brief Bit definitions for register SYS_STATUS
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| 247 |
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**/
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| 248 |
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#define SYS_STATUS_ID 0x0F /* System event Status Register */
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| 249 |
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#define SYS_STATUS_OFFSET 0x00
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| 250 |
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#define SYS_STATUS_LEN (5) /* Note 40 bit register */
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| 251 |
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/*masks */
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| 252 |
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#define SYS_STATUS_MASK_32 0xFFF7FFFFUL /* System event Status Register access mask (all unused fields should always be writen as zero) */
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| 253 |
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/*offset 0 */
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| 254 |
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#define SYS_STATUS_IRQS 0x00000001UL /* Interrupt Request Status READ ONLY */
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| 255 |
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#define SYS_STATUS_CPLOCK 0x00000002UL /* Clock PLL Lock */
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| 256 |
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#define SYS_STATUS_ESYNCR 0x00000004UL /* External Sync Clock Reset */
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| 257 |
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#define SYS_STATUS_AAT 0x00000008UL /* Automatic Acknowledge Trigger */
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| 258 |
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#define SYS_STATUS_TXFRB 0x00000010UL /* Transmit Frame Begins */
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| 259 |
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#define SYS_STATUS_TXPRS 0x00000020UL /* Transmit Preamble Sent */
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| 260 |
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#define SYS_STATUS_TXPHS 0x00000040UL /* Transmit PHY Header Sent */
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| 261 |
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#define SYS_STATUS_TXFRS 0x00000080UL /* Transmit Frame Sent: This is set when the transmitter has completed the sending of a frame */
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| 262 |
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/*offset 8 */
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| 263 |
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#define SYS_STATUS_RXPRD 0x00000100UL /* Receiver Preamble Detected status */
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| 264 |
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#define SYS_STATUS_RXSFDD 0x00000200UL /* Receiver Start Frame Delimiter Detected. */
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| 265 |
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#define SYS_STATUS_LDEDONE 0x00000400UL /* LDE processing done */
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| 266 |
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#define SYS_STATUS_RXPHD 0x00000800UL /* Receiver PHY Header Detect */
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| 267 |
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#define SYS_STATUS_RXPHE 0x00001000UL /* Receiver PHY Header Error */
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| 268 |
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#define SYS_STATUS_RXDFR 0x00002000UL /* Receiver Data Frame Ready */
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| 269 |
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#define SYS_STATUS_RXFCG 0x00004000UL /* Receiver FCS Good */
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| 270 |
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#define SYS_STATUS_RXFCE 0x00008000UL /* Receiver FCS Error */
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| 271 |
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/*offset 16 */
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| 272 |
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#define SYS_STATUS_RXRFSL 0x00010000UL /* Receiver Reed Solomon Frame Sync Loss */
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| 273 |
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#define SYS_STATUS_RXRFTO 0x00020000UL /* Receive Frame Wait Timeout */
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| 274 |
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#define SYS_STATUS_LDEERR 0x00040000UL /* Leading edge detection processing error */
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| 275 |
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#define SYS_STATUS_reserved 0x00080000UL /* bit19 reserved */
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| 276 |
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#define SYS_STATUS_RXOVRR 0x00100000UL /* Receiver Overrun */
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| 277 |
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#define SYS_STATUS_RXPTO 0x00200000UL /* Preamble detection timeout */
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| 278 |
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#define SYS_STATUS_GPIOIRQ 0x00400000UL /* GPIO interrupt */
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| 279 |
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#define SYS_STATUS_SLP2INIT 0x00800000UL /* SLEEP to INIT */
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| 280 |
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/*offset 24 */
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| 281 |
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#define SYS_STATUS_RFPLL_LL 0x01000000UL /* RF PLL Losing Lock */
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| 282 |
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#define SYS_STATUS_CLKPLL_LL 0x02000000UL /* Clock PLL Losing Lock */
|
| 283 |
|
#define SYS_STATUS_RXSFDTO 0x04000000UL /* Receive SFD timeout */
|
| 284 |
|
#define SYS_STATUS_HPDWARN 0x08000000UL /* Half Period Delay Warning */
|
| 285 |
|
#define SYS_STATUS_TXBERR 0x10000000UL /* Transmit Buffer Error */
|
| 286 |
|
#define SYS_STATUS_AFFREJ 0x20000000UL /* Automatic Frame Filtering rejection */
|
| 287 |
|
#define SYS_STATUS_HSRBP 0x40000000UL /* Host Side Receive Buffer Pointer */
|
| 288 |
|
#define SYS_STATUS_ICRBP 0x80000000UL /* IC side Receive Buffer Pointer READ ONLY */
|
| 289 |
|
/*offset 32 */
|
| 290 |
|
#define SYS_STATUS_RXRSCS 0x0100000000ULL /* Receiver Reed-Solomon Correction Status */
|
| 291 |
|
#define SYS_STATUS_RXPREJ 0x0200000000ULL /* Receiver Preamble Rejection */
|
| 292 |
|
#define SYS_STATUS_TXPUTE 0x0400000000ULL /* Transmit power up time error */
|
| 293 |
|
|
| 294 |
|
#define SYS_STATUS_TXERR (0x0408) /* These bits are the 16 high bits of status register TXPUTE and HPDWARN flags */
|
| 295 |
|
|
| 296 |
|
/* All RX events after a correct packet reception mask. */
|
| 297 |
|
#define SYS_STATUS_ALL_RX_GOOD (SYS_STATUS_RXDFR | SYS_STATUS_RXFCG | SYS_STATUS_RXPRD | \
|
| 298 |
|
SYS_STATUS_RXSFDD | SYS_STATUS_RXPHD | SYS_STATUS_LDEDONE)
|
| 299 |
|
|
| 300 |
|
/* All double buffer events mask. */
|
| 301 |
|
#define SYS_STATUS_ALL_DBLBUFF (SYS_STATUS_RXDFR | SYS_STATUS_RXFCG)
|
| 302 |
|
|
| 303 |
|
/* All RX errors mask. */
|
| 304 |
|
#define SYS_STATUS_ALL_RX_ERR (SYS_STATUS_RXPHE | SYS_STATUS_RXFCE | SYS_STATUS_RXRFSL | SYS_STATUS_RXSFDTO \
|
| 305 |
|
| SYS_STATUS_AFFREJ | SYS_STATUS_LDEERR)
|
| 306 |
|
|
| 307 |
|
/* User defined RX timeouts (frame wait timeout and preamble detect timeout) mask. */
|
| 308 |
|
#define SYS_STATUS_ALL_RX_TO (SYS_STATUS_RXRFTO | SYS_STATUS_RXPTO)
|
| 309 |
|
|
| 310 |
|
/* All TX events mask. */
|
| 311 |
|
#define SYS_STATUS_ALL_TX (SYS_STATUS_AAT | SYS_STATUS_TXFRB | SYS_STATUS_TXPRS | \
|
| 312 |
|
SYS_STATUS_TXPHS | SYS_STATUS_TXFRS )
|
| 313 |
|
|
| 314 |
|
|
| 315 |
|
/****************************************************************************//**
|
| 316 |
|
* @brief Bit definitions for register RX_FINFO
|
| 317 |
|
**/
|
| 318 |
|
#define RX_FINFO_ID 0x10 /* RX Frame Information (in double buffer set) */
|
| 319 |
|
#define RX_FINFO_OFFSET 0x00
|
| 320 |
|
#define RX_FINFO_LEN (4)
|
| 321 |
|
/*mask and shift */
|
| 322 |
|
#define RX_FINFO_MASK_32 0xFFFFFBFFUL /* System event Status Register access mask (all unused fields should always be writen as zero) */
|
| 323 |
|
#define RX_FINFO_RXFLEN_MASK 0x0000007FUL /* Receive Frame Length (0 to 127) */
|
| 324 |
|
#define RX_FINFO_RXFLE_MASK 0x00000380UL /* Receive Frame Length Extension (0 to 7)<<7 */
|
| 325 |
|
#define RX_FINFO_RXFL_MASK_1023 0x000003FFUL /* Receive Frame Length Extension (0 to 1023) */
|
| 326 |
|
|
| 327 |
|
#define RX_FINFO_RXNSPL_MASK 0x00001800UL /* Receive Non-Standard Preamble Length */
|
| 328 |
|
#define RX_FINFO_RXPSR_MASK 0x000C0000UL /* RX Preamble Repetition. 00 = 16 symbols, 01 = 64 symbols, 10 = 1024 symbols, 11 = 4096 symbols */
|
| 329 |
|
|
| 330 |
|
#define RX_FINFO_RXPEL_MASK 0x000C1800UL /* Receive Preamble Length = RXPSR+RXNSPL */
|
| 331 |
|
#define RX_FINFO_RXPEL_64 0x00040000UL /* Receive Preamble length = 64 */
|
| 332 |
|
#define RX_FINFO_RXPEL_128 0x00040800UL /* Receive Preamble length = 128 */
|
| 333 |
|
#define RX_FINFO_RXPEL_256 0x00041000UL /* Receive Preamble length = 256 */
|
| 334 |
|
#define RX_FINFO_RXPEL_512 0x00041800UL /* Receive Preamble length = 512 */
|
| 335 |
|
#define RX_FINFO_RXPEL_1024 0x00080000UL /* Receive Preamble length = 1024 */
|
| 336 |
|
#define RX_FINFO_RXPEL_1536 0x00080800UL /* Receive Preamble length = 1536 */
|
| 337 |
|
#define RX_FINFO_RXPEL_2048 0x00081000UL /* Receive Preamble length = 2048 */
|
| 338 |
|
#define RX_FINFO_RXPEL_4096 0x000C0000UL /* Receive Preamble length = 4096 */
|
| 339 |
|
|
| 340 |
|
#define RX_FINFO_RXBR_MASK 0x00006000UL /* Receive Bit Rate report. This field reports the received bit rate */
|
| 341 |
|
#define RX_FINFO_RXBR_110k 0x00000000UL /* Received bit rate = 110 kbps */
|
| 342 |
|
#define RX_FINFO_RXBR_850k 0x00002000UL /* Received bit rate = 850 kbps */
|
| 343 |
|
#define RX_FINFO_RXBR_6M 0x00004000UL /* Received bit rate = 6.8 Mbps */
|
| 344 |
|
#define RX_FINFO_RXBR_SHIFT (13)
|
| 345 |
|
|
| 346 |
|
#define RX_FINFO_RNG 0x00008000UL /* Receiver Ranging. Ranging bit in the received PHY header identifying the frame as a ranging packet. */
|
| 347 |
|
#define RX_FINFO_RNG_SHIFT (15)
|
| 348 |
|
|
| 349 |
|
#define RX_FINFO_RXPRF_MASK 0x00030000UL /* RX Pulse Repetition Rate report */
|
| 350 |
|
#define RX_FINFO_RXPRF_16M 0x00010000UL /* PRF being employed in the receiver = 16M */
|
| 351 |
|
#define RX_FINFO_RXPRF_64M 0x00020000UL /* PRF being employed in the receiver = 64M */
|
| 352 |
|
#define RX_FINFO_RXPRF_SHIFT (16)
|
| 353 |
|
|
| 354 |
|
#define RX_FINFO_RXPACC_MASK 0xFFF00000UL /* Preamble Accumulation Count */
|
| 355 |
|
#define RX_FINFO_RXPACC_SHIFT (20)
|
| 356 |
|
|
| 357 |
|
|
| 358 |
|
/****************************************************************************//**
|
| 359 |
|
* @brief Bit definitions for register RX_BUFFER
|
| 360 |
|
**/
|
| 361 |
|
#define RX_BUFFER_ID 0x11 /* Receive Data Buffer (in double buffer set) */
|
| 362 |
|
#define RX_BUFFER_LEN (1024)
|
| 363 |
|
|
| 364 |
|
|
| 365 |
|
/****************************************************************************//**
|
| 366 |
|
* @brief Bit definitions for register RX_FQUAL
|
| 367 |
|
**/
|
| 368 |
|
#define RX_FQUAL_ID 0x12 /* Rx Frame Quality information (in double buffer set) */
|
| 369 |
|
#define RX_FQUAL_LEN (8) /* note 64 bit register*/
|
| 370 |
|
/*mask and shift */
|
| 371 |
|
/*offset 0 */
|
| 372 |
|
#define RX_EQUAL_STD_NOISE_MASK 0x0000FFFFULL /* Standard Deviation of Noise */
|
| 373 |
|
#define RX_EQUAL_STD_NOISE_SHIFT (0)
|
| 374 |
|
#define STD_NOISE_MASK RX_EQUAL_STD_NOISE_MASK
|
| 375 |
|
#define STD_NOISE_SHIFT RX_EQUAL_STD_NOISE_SHIFT
|
| 376 |
|
/*offset 16 */
|
| 377 |
|
#define RX_EQUAL_FP_AMPL2_MASK 0xFFFF0000ULL /* First Path Amplitude point 2 */
|
| 378 |
|
#define RX_EQUAL_FP_AMPL2_SHIFT (16)
|
| 379 |
|
#define FP_AMPL2_MASK RX_EQUAL_FP_AMPL2_MASK
|
| 380 |
|
#define FP_AMPL2_SHIFT RX_EQUAL_FP_AMPL2_SHIFT
|
| 381 |
|
/*offset 32*/
|
| 382 |
|
#define RX_EQUAL_PP_AMPL3_MASK 0x0000FFFF00000000ULL /* First Path Amplitude point 3 */
|
| 383 |
|
#define RX_EQUAL_PP_AMPL3_SHIFT (32)
|
| 384 |
|
#define PP_AMPL3_MASK RX_EQUAL_PP_AMPL3_MASK
|
| 385 |
|
#define PP_AMPL3_SHIFT RX_EQUAL_PP_AMPL3_SHIFT
|
| 386 |
|
/*offset 48*/
|